JP2910315B2 - Bus lock control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit connected to a bus having a bus lock function, and more particularly to a central processing unit and a bus control unit having different conditions for starting and ending a bus lock. The present invention relates to a bus lock control device that can operate without contradiction by adding a bus lock control circuit to a device .

[0002]

2. Description of the Related Art Conventionally, a bus lock function of this kind was provided.
In the bus lock control device , the start of the bus lock is when the central processing unit starts the memory read with the bus lock, for example, to execute a test and set instruction, and the release of the bus lock is performed by the central processing unit. Irrespective of the data read at the end of the instruction, that is, even if it is not necessary to update the data due to the read data, the bus lock is always released by performing a memory write with a bus lock. Was.

[0003]

SUMMARY OF THE INVENTION The above-mentioned conventional bass liner
When the central processing unit executes a bus lock instruction such as a test-and-set instruction, the central control unit reads data from the memory with a lock instruction, and determines from the data to update the memory data. Even when there is no lock, the lock is released by writing the same data as the contents of the memory as a dummy with an instruction with a hook.

Therefore, when it is not necessary to update the data in the memory, in a central processing unit in which the read-modify-write cycle signal is made inactive and writing to the memory is not performed, the conventional bus control device controls the bus. In this case, there is a problem that the bus lock may not be released.

[0005]

SUMMARY OF THE INVENTION A bus lock control according to the present invention.
The device is an arithmetic processing unit connected to a bus having a bus lock function, and a read-modify-write cycle for requesting a bus lock during a first read cycle at the time of executing a bus lock instruction such as a test and set instruction. When the signal is active and the bus lock needs to be continued according to the read data, the read-modify-write cycle signal is kept active after the end of the bus cycle. It has the function to make the read-modify-write signal inactive at the end of the bus cycle.
A central processing unit having a function of suppressing access to the outside and a write-through type buffer memory, in which memory access is performed without referring to the contents of the buffer memory according to a lock memory access instruction from the central processing unit side. A buffer memory device with a function,
An access control unit connected to the buffer memory device and the central processing unit, for controlling data and control signals between the central processing unit and the buffer memory device, and connected to the buffer memory and a bus; When a memory read request with a bus lock is input, a bus use request signal is output, and when a bus use permission signal is input, a memory read access to the bus is performed with the first bus lock signal activated. For the subsequent memory access in the state where the first bus lock signal is active, the memory which uses the bus without outputting the bus use request signal and does not accompany the subsequent bus lock request is used. A bus control device that makes the first bus lock signal inactive in a write cycle. The buffer memory device, the bus control device, and the bus controller are connected to a bus, and a memory access without lock is always performed on the bus controller. The first bus lock signal output from the bus controller is a bus. When the buffer memory device starts memory access to the bus control device while the central processing unit activates the read-modify-write cycle signal, the second Outputting a bus lock signal, and inputting a halt signal to the central processing unit to inhibit the next bus cycle,
When the read modify write cycle signal is active in response to the read modify write cycle signal from the central processing unit after the bus control device completes memory access, the second bus port on the bus is activated. The halt signal to the central processing unit is released while the read signal is active, and when the read modify write cycle signal is inactive, the second bus lock signal on the bus is inactive; A function for canceling the halt signal of the central processing unit;
When the bus lock signal is inactive ,
A bus use request signal from the bus control device is output to the bus, a bus use permission signal from the bus is returned to the bus control device, and when the second bus lock signal is active, the bus use request from the bus control device is output. A bus use permission signal is immediately returned to the bus control device to the bus control device without outputting a request signal to the bus.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.
1 is an arithmetic processing unit, and 2 is a bus having a lock function. In the arithmetic processing unit 1, 11 is a central processing unit, 12 is an access control unit, 13 is a buffer memory device, and 14 is a bus control device. The central processing unit 11
During a non-divided bus cycle, a read-modify-write cycle signal 118 is output, and the lock control circuit 15
Inputs the halt signal 119 to the central processing unit 11. The bus control device 14 has the first bus lock signal 146 but does not output the first bus lock signal 146 to the bus.
Is output.

FIGS. 2 and 3 are detailed diagrams of the arithmetic processing unit 1 (the left and right terminals in FIG. 2 and FIG. 3 may be connected to each other), and the central processing unit 11 supplies an address strobe signal. (AS negative) 113, function code (FC0-2) and address (A0-31) 114,
The data size (SIZE0, 1) 117 is output. When the address strobe signal 113 is active, the function code, the address 114, and the data size 117
Indicates that is valid. The function code indicates the type of the address space accessed by the central processing unit 11, and is assigned as shown in Table 1.

[0009]

Data (D0-31) 111 is a 32-bit bidirectional data line input / output by the central processing unit 11. The data size (SIZE0, 1) 117 indicates the number of valid bytes of 32-bit data. The data strobe signal (DS negation) 115 indicates that the buffer memory device 13 should output data in the read cycle,
The write cycle indicates that the central processing unit 11 is outputting valid data. Data acknowledge signal (DA
CK No) 116 indicates that the buffer memory device 13 has completed the data transfer, and when the central processing unit 11 detects the data acknowledge signal 116 in the read cycle, the data is latched and the bus cycle ends. The central processing unit 11 outputs a halt signal (HAL).
When (T No) 119 is input, the activity of all the buses of the central processing unit is stopped at the time of completion of the bus cycle being executed. Also, the read modify write cycle signal (R
MC negative) 119 indicates that the current bus cycle by the central processing unit 11 is a read-modify-write cycle that is not divided, and is active during that time. The read / write signal [R / (W negation)] 112 indicates a read cycle when high and a write cycle when low.

Reference numeral 13 denotes a write-through type buffer memory device, which is a processor strobe signal (PAS) of an input signal.
No) The rising edge of 122 indicates the rising timing of the bus cycle of the central processing unit, and the falling edge indicates A1.
Latch the addresses for. Also, the processor command strobe signal (PCS negative) 1
23 latches the address tag (A11-27) and the status (ST0-2) 125 at the fall, and indicates the end of the bus cycle of the central processing unit 11 at the rise.
The data lines (D0-31) 111 are latched. The status (ST0 to ST2) 125 indicates the type of access from the central processing unit 11, and is assigned as shown in Table 2. The processor ready signal (PRDY negation) 126 is
The read cycle indicates that preparation for data output to the central processing unit 11 is completed, and the write cycle indicates that preparation for receiving the next cycle from the central processing unit 11 is completed. When the cache output enable signal (CAEN negative) 127 is at a low level, the buffer memory device 13 becomes operable. The processor byte enable signal (PBE0 to PBE3 negative) 128 indicates a valid byte data position in 32-bit data in a write cycle.

[0012]

In the access control unit 12, an address strobe signal 113 inputted from the central processing unit 11 is provided.
Are synchronized with the processor clock (CLK1) 121 to generate a PAS negation 122 and a PCS negation 123. When the exclusive OR of FC0 and FC1 is 1, CAEN negation 12
7 as active, and the status signals (ST0 to ST2) 1
25 is 001 when the RMC negation signal 118 is active, and 010 when the RMC negation signal 118 is inactive.
Output as Stay signal (ST0-2) 125
Is 001, that is, at the time of memory access, the address input from the central processing unit 11 and the address tag inside the buffer memory device 13 are checked, and when they match in the read cycle, the data line (D0-31) is immediately 11
1 is output, and the PRDY negation signal 126 is activated. Further, when the write cycle is completed, the data in the buffer memory device 13 is invalidated. When there is a mismatch in the read cycle and in the write cycle, the buffer memory device 13 causes the bus control device 14 to start an external memory access. PBE0-3 Negative signal 1
28 is SIZE0, 1117 from the central processing unit 11
And A0,1 to form as shown in Table 3.

[0014]

In the buffer memory device 13, the memory address strobe signal (MAS negation) 139 is used in combination with the memory data strobe signal (MDS negation) 137. When the MDS negation 137 is inactive, that is, when the memory bus outputs an address. During the cycle, the data on the bus 2 of the address data lines (AD0-31) 133 and 136 is used as a signal for latching the data on the bus 2 at the rising edge of the MAS negation 139, and when the MDS negation 137 is active, that is, the memory bus Internal address data lines (AD0-31) 133, 13
6 indicates that the data is valid. The internal address data lines (AD0 to 31) 133 and 136 are buses connecting the buffer memory device 13 and the bus control device 14, and the meaning of output signals in the cycle of outputting an address is as shown in Table 4. Bus request signal (BRQ negation) 1
34 is a request signal for becoming a bus master of the memory bus, and a bus acknowledge signal (BAK negative) 135 is a permission signal for becoming a bus master from the memory bus. The MBE0 to 3 NOT 132 is used as a byte enable signal of 1 byte each of 4 bytes of the data bus at the time of writing in the address output cycle. In the data input / output cycle, MBE0 NOT is corrected to the last bus cycle (EOC negative) and MBE1 NOT is corrected. Unable error (UERR negation), MBE2 negation is wait cycle (WAIT negation), MBE3 negation is correctable error (CERR negation)
Is shown.

[0016]

In the bus control device 4, the command start (CST negative) 142 corresponds to the bus address data line (A
D'0-31) 144 indicates that a command has been output, and the bus address data lines (AD'0-31) 14
The meaning of the address 4 is as shown in Table 5. The bus controller 5 knows from the ready signal (RDY negation) 143 that the preparation for data transfer on the memory side is completed, and the last bus cycle signal (EOC negation) 145 indicates that the current transfer is the last bus cycle. Know. These signals are all input and output in synchronization with the bus clock (CLK2) 141. First bus lock signal (LOCK1 negative)
146 is not output to the bus.

[0018]

In the lock control unit 15, when the MDS negative signal 137 from the buffer memory device 13 is active and the buffer memory device 13 is performing data input / output, the data of the AD 29 is directly input to the bus control device 14. When the buffer memory device 13 is outputting an address, the internal address data line (AD29) 136
Is always input to the bus controller 14 as 0 (15
1).

This means that the bus control unit 14 always performs the lockless memory access. When the BRQ negation signal 134 is input from the buffer memory device 13 to the bus control device 14, the bus control device 14 outputs the UBRQ negation signal 15 unless the bus is locked.
2 is output. Bus control device 1 by lock control unit 15
4, the bus controller 14 always outputs the UBRQ negation signal 152 when the BRQ negation signal 134 is input from the buffer memory device 13 because the control is performed so that the memory access without lock is always performed. Become. U
The BRQ negation signal 152 is not directly output to the bus 2 but is once input to the lock control unit 5 to determine whether or not the bus is currently locked. When the bus is locked, the bus request signal is output to the bus 2. Bus controller 14 without output to
Relative Returns UBAK negative signal 153, when not in the bus lock, 'outputs (negative 154, U bus acknowledge signal (UBAK from the bus U bus request signal UBRQ)' to the bus 2 receives a negative) 155 Is returned to the bus control device 14.

The central processing unit 11 receives an RMC negation signal 118
When the buffer memory device 13 starts memory access to the bus control device 14 in a state in which the bus control device 14 is activated, a second bus lock signal (LOCK2 negation) 156 is output to the bus, and the halt signal is sent to the central processing unit 11. 1
Input 19 to inhibit the next bus cycle. And
After the bus controller 14 finishes the memory access, it checks the RMC negation signal 118 from the central processing unit 11 and checks the RM
When C NOT signal is active, LOCK2 NOT signal 15
The HALT signal 119 to the central processing unit 11 is released while 6 remains active, and the read-modify-write cycle is continued. When the RMC negative signal is inactive, the LOCK2 negative signal is made inactive, the halt signal 119 of the central processing unit 11 is released, and the read-modify-write cycle is ended.

[0022]

As described above, according to the information processing apparatus according to the present invention, the information processing apparatus having the conventional bus lock function, that is, the start of the bus lock is performed by the central processing unit by, for example, a test and set instruction. For the execution of
When the memory read with the bus lock is started, the bus lock is released regardless of the data read by the central processing unit at the end of the instruction, that is, even if it is not necessary to update the data with the read data. However, when it is not necessary to update data in the memory for an information processing apparatus in which the bus lock is released by always performing the memory write with the bus lock,
There is an effect that a central processing unit in which the read-modify-write cycle signal is made inactive and the memory is not written can be connected without contradiction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram (left side) illustrating a configuration of the arithmetic processing device according to the embodiment;

FIG. 3 is a block diagram (right side) illustrating a configuration of an arithmetic processing device according to the embodiment;

[Explanation of symbols]

Reference Signs List 1 arithmetic processing unit 2 bus 11 central processing unit 12 access control unit 13 buffer memory device 14 bus control device 15 bus lock control device 111 data line (D0 to 31) 112 read / write signal [R / (W negative)] 113 address strobe Signal (AS negation) 114 Function code (FC0-2) and address (A0-31) 115 Data strobe signal (DS negation) 116 Data acknowledge signal (DACK negation) 117 Data size (SIZE0, 1) 118 Read modify write cycle signal (R
MC not) 119 Halt signal (HALT not) 121 Processor clock (CLK1) 122 Processor address strobe signal (PAS)
No) 123 Processor command strobe signal (PCS
No) 124 Address (A0-27) 125 Status signal (ST0-2 No) 126 Processor ready signal (PRDY No) 127 Cache output enable signal (C
AEN negative) 128 Processor byte enable signal (PBE0
否定 3 negative) 131 Memory address strobe signal (MAS negative) 132 Memory byte enable signal (MBE0-3)
No) 133 Internal address data line (AD0-28,3
0, 31) 134 Bus request signal (BRQ negation) 135 Bus acknowledge signal (BAK negation) 136 Internal address data line (AD29) 137 Memory data strobe signal (MDS negation) 141 Bus clock (CLK2) 142 Command start signal (CST negation) 143 Ready signal (RDY negation) 144 Bus address data line (AD0-31) 145 Final transfer cycle signal (EOC negation) 146 First bus lock signal (LOCK1 negation) 151 Internal address data line (AD29 ') 152 U bus Request signal (UBRQ negation) 153 U bus acknowledge signal (UBAK negation) 154 U bus request signal (UBRQ 'negation) 155 U bus acknowledge signal (UBAK' negation) 156 Second bus lock signal (L CK2 negative)

Claims (1)

(57) [Claims] An arithmetic processing unit connected to a bus having a bus lock function, wherein a read modify requesting a bus lock during a first read cycle at the time of executing an instruction for locking a bus such as a test and set instruction. When the write cycle signal is active and the bus lock needs to be continued in accordance with the read data, it is necessary to keep the read modify write cycle signal active even after the end of the bus cycle to continue the bus lock. A central processing unit having a function of making the read-modify-write signal inactive at the end of a bus cycle when there is no input, and a function of suppressing access to the outside after the current bus cycle when an external halt signal is input. Device and write-through type buffer memory,
A buffer memory device having a function of accessing the memory without referring to the contents of the buffer memory by a command of a bypass memory access with a lock from the central processing unit, and connected to the buffer memory device and the central processing unit; An access control unit that controls data and control signals between the central processing unit and the buffer memory device;
A bus use request signal is output when a memory read request with a bus lock is input from the buffer memory and the bus, and a first bus lock signal is input when a bus use permission signal is input. A memory read access to the bus is performed in an active state, and for a subsequent memory access in a state in which the first bus lock signal is active, the bus is output without outputting the bus use request signal. A bus control device for inactivating the first bus lock signal in a memory write cycle without a bus lock request thereafter, wherein the buffer memory device, the bus control device, and the bus Connected to the bus control device so that a memory access without lock is always performed. The first bus lock signal output from the control device is prevented from being output to the bus, and the buffer memory device sends a memory to the bus control device while the central processing unit activates the read modify write cycle signal. When you start access,
A second bus lock signal is output to the bus, a halt signal is input to the central processing unit to suppress the next bus cycle, and after the bus control device completes the memory access, a signal from the central processing unit is output. In response to the read modify write cycle signal, when the read modify write cycle signal is active, the halt signal to the central processing unit is released while the second bus lock signal on the bus remains active. When the read-modify-write cycle signal is inactive, the second bus lock signal on the bus is made inactive to release the halt signal of the central processing unit. When the bus lock signal is inactive, the bus use request signal from the bus control device is output to the bus, The bus use permission signal is returned to the bus control device, and when the second bus lock signal is active, the bus use request signal from the bus control device is not output to the bus, and the bus use permission signal is immediately transmitted to the bus control device. A bus lock control device comprising a bus use permission signal returned to a bus control device.