JP3145479B2 - Multiprocessor system and cache memory control method and apparatus therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for controlling a cache memory in a tightly-coupled multiprocessor, and more particularly to a method and an apparatus for controlling a cache memory suitable for keeping the contents of cache memories consistent. .

[0002]

2. Description of the Related Art Cache memories are widely used in recent high-performance computers in order to improve the memory access speed. This cache memory is a technology that can achieve remarkable performance improvement in a computer consisting of a single processor.However, in a tightly coupled multiprocessor system in which a plurality of processors share memory, a system bus or memory which becomes a bottleneck is used. Produce more important effects to reduce access to the Therefore, although the control is complicated, a copy-back type cache memory, which is said to be excellent in performance, is increasingly used.

[0003] In a copy-back type cache memory in a multiprocessor system, data matching control (referred to as coherence control or coherence control) is an important technical problem. This matching control is a method of controlling the contents of a cache memory connected to each processor so as not to always contradict (mismatch).
(James Archibald etal: Cache Coherence Protocols
; Evaluation Using a Multiprocessor Simulation Mo
del, ACM Transaction on Computer System, Vol. 14, N
o.4, Nov. 1986, pp273-298) Several methods are introduced in "Cache Coherency Protocol: Using Multiprocessor Simulation Model".

[0004]

What is problematic when implementing these protocols is the exclusive write state realizing method. That is, exclusive control must be performed by hardware before writing is performed so that a plurality of processors do not write simultaneously on the same line. A method for solving this problem is described in JP-A-3-40047 "Cache line store method". However, this conventional technique requires a large amount of special hardware and is not suitable for an inexpensive multiprocessor system.

An object of the present invention is to provide a cache memory control method and an apparatus for realizing exclusive writing with a small amount of hardware using basic functions of a microprocessor in a multiprocessor system using a general-purpose microprocessor. is there.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an instruction execution unit, a copy-back type cache memory connected to the instruction execution unit, for reading and storing a part of the contents of a main memory via a system bus. A bus interface connected to the back-type cache memory and interfacing with the main memory; and a bus monitoring device connected to the copy-back type cache memory and monitoring memory access performed via a system bus. In a multiprocessor system having a plurality of processing devices having a retry function, the bus monitoring device may include:
When detecting that a processing device other than the own processing device has performed an access for updating a line held in the own copy-back type cache memory, the bus interface cancels a memory access request held in the bus interface, In response to the cancel request, the bus interface cancels access to the bus interface held in the copy-back cache memory, and cancels access to the copy-back cache memory to the instruction execution unit. This is achieved by performing the retry after that.

[0007]

The external access from the instruction section of a certain processing unit is a write access, and when a cache memory line is updated for the first time, the cache memory issues an exclusive write state request access to the system bus. Upon detecting this exclusive write state request access, the other processing device issues an access cancel request to its own bus interface unit and cache memory, and further issues an external access retry function request to the command unit. Then, the cache memory invalidates the line targeted for the exclusive write state request before the instruction unit starts retry.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is an overall configuration diagram of a tightly-coupled multiprocessor system according to one embodiment of the present invention. 1 (1-a
To 1-n) are processing devices (hereinafter, referred to as BPUs).
And accesses the memory 2 via the system bus 4 to process data. Reference numeral 3 denotes a peripheral device (IO), including a disk device and the like.

FIG. 1 is a diagram showing the internal configuration of the BPU 1. 2
01 is, for example, Motorola's 32-bit MC68
Although it is a microprocessor (hereinafter, referred to as MPU) like 040, a general-purpose microprocessor can be used without being limited to MC68040. Reference numeral 202 denotes an external cache memory (EC). Reference numeral 203 denotes a system bus interface unit which temporarily holds access from the cache memory and acquires the system bus right, and then accesses the memory 2 or the peripheral device 3 via the system bus 4. Reference numeral 204 denotes a bus monitor (generally called a snooper: SNP) that monitors accesses issued from other BPUs or peripheral devices. Then, when the same address appears on the system bus 4, according to the function (for example, read / write) at that time,
The invalidation address and the invalidation information are stored in a FIFO (First)
in First out) buffer 209.

Reference numerals 205 and 206 denote address and data signals, respectively. Reference numeral 207 denotes a signal line for transmitting an access cancel request from the bus monitor 204 to the bus interface 203. Reference numeral 208 denotes a bus interface unit 203 from the MPU 201 and the cache memory 2
02 is a signal line for transmitting an access cancel request.
211 is a signal line for transmitting invalidation request information from the FIFO 209 to the cache memory 202, and 212 is a signal line for transmitting an access signal from the cache memory 202 to the bus interface 203.

FIG. 3 is a diagram showing the internal configuration of the cache memory 202. Reference numeral 301 denotes a data unit that holds data, and 302 denotes a tag unit that holds the address and status of data. 303 is an address line 2 in the BPU 201
This is a comparator that compares the address on the tag 05 with the address on the tag unit 302. Reference numeral 304 denotes a control circuit that controls the entire cache memory 202.

FIG. 6 is a detailed configuration diagram of the data unit 301, and FIG. 7 is a detailed configuration diagram of the tag unit 302. As shown in FIG. 6, the data section forms one line with 16 bytes (8 long words), and has a parity for each byte. As shown in FIG. 7, the tag unit 302 has an area for storing the physical address of the line (17th to 5th bits) and an area for storing the state of the line (STATUS). When there is an external access from the MPU 201, the cache memory 202 searches the tag unit 302 and finds a line necessary for the access (hit).
It is determined whether the MPU 201 does not exist (miss hit) or not (miss hit), and the access from the MPU 201 is processed according to the state transition shown in FIG.

That is, when a hit occurs in the read access (801-a, b), the data unit 30 is sent to the MPU 201.
1 data is supplied and a read miss occurs (802)
, The bus interface unit 203
A request is made to read a required line from the main memory 2 (FIG. 2). In order to store the data read at this time in the cache memory 202, if the existing line to be replaced is an "updated state" (a content mismatch state with the main memory 2; hereinafter, referred to as a MOD state), this line is replaced. After writing back (copy back) to the main memory 2, a line read request is made.

When a hit occurs in a write access (80
3, 804), the operation differs depending on whether the line has already been updated (MOD) or not ("no update state" (contents match state with main memory: hereinafter referred to as UMD state). At (803), the process is terminated without any change, and at the time of UMD (804), an exclusive write (invalidation of cache memory of another processor) state request is sent to the bus interface unit 20.
The data is output to the system bus 4 via 3 and the cache memory of the other processor is invalidated, and then the data is written and the processing is terminated.

In the case of a write miss (805)
Request the bus interface unit 203 to read the line with the invalidation request. At this time, in order to store the read data in the cache memory 202, if the existing line to be replaced is in the MOD state, this line is copied back, and then the line with the invalidation request is read. Update of.

FIG. 4 is a detailed block diagram of the bus monitor 204. Reference numeral 402 denotes a tag unit having the same contents as the cache memory 202. A comparator 403 compares the address on the system bus address line 4 with the address of the tag unit 402. A control circuit 404 controls the entire bus monitor 204. The bus monitor 204 monitors accesses on the system bus 4 and determines whether a line corresponding to an access from another BPU exists (hit) or not (miss hit) by searching for a tag. Then, according to the state of the line, access from another BPU is processed according to the state transition shown in FIG.

That is, the simple line read access hits and the line has already been updated (MOD state).
In the case (901), a request is made to the cache memory 202 via the FIFO 209 to write back the data in the data portion to the main memory 2 (copy back) and shift the status to the UMD state. Simple line read access hits and the line is not updated (UMD state)
In the case (902), nothing is performed. When a hit occurs due to an invalidation request access of another BPU, the operation differs depending on whether the line has already been updated (MOD state) or not (UMD state). Here, invalidation request access means simple invalidation request access, line read with invalidation request, and read / write of line size (16 bytes or less).
Includes write access. In the case of MOD (903),
To supply the data in the data section (copy back)
A request is made to the cache memory 202, a request is made to invalidate the line, and a cancel signal 207 is output to the bus interface unit 203, thus ending the processing. However, in the case of line write, even if copy-back is performed, the entire line is rewritten and there is no meaning in copy-back, so only an invalidation request is output.
In the case of UMD (905), the cache memory 202
Requesting that the line be invalidated, and further output a cancel signal 207 to the bus interface unit 203 to end the processing.

FIG. 5 shows that the bus monitor 204 is
FIG. 9 is a format diagram of a request stored in a cache memory and transmitted to a cache memory. ADR 501 is an address for indicating a line, PTY 502 is an address parity, STATUS 503 is a tag status of the next cache memory, and FUNC 504 is a function indicating the content of the request. FUNC includes an invalidation request and a copy back request.

FIG. 10 is a diagram for explaining the operation of the cache memory control method in the above-described multiprocessor system, and specifically describes a method for realizing the exclusive write state. FIG. 10 shows the movement in each BPU and in the system bus in a time-series manner. Each cache memory (EC) of the BPUs # 1 and # 2 has a UMD of the same address.
MPU # 1 and MP
U # 2 is for the UMD state line of the same address,
It is assumed that write access was performed (1001, 1002) (assuming that MPU # 1 accessed slightly earlier than MPU # 2).

At this time, the EC # 1 hits by a write access, and since the line is a UMD, an exclusive write (invalidation of the cache memory of another processor) state request is sent to the bus interface unit (BI).
U) Output to the system bus via # 1 (1003), and wait until the cache memory (EC) of another processor (such as BPU # 2) is invalidated (1005).

On the other hand, the cache memory (E
C) Similarly, # 2 is hit by a write access, and the line is UMD. Therefore, an exclusive write (invalidation of the cache memory of another processor) state request is sent to the system via the bus interface unit (BIU) # 2. Output to the bus (1004) and attempt to wait for the cache memory of another processor to be invalidated. However, since the system bus is already used by BPU # 1, the bus interface unit (BIU)
At # 2, a bus right waiting state is set (1006).

During this time, the bus monitor (SN) of BPU # 2
P) # 2 detects the invalidation request access from BPU # 1, and the own bus interface unit (BIU) #
Then, a cancel is issued to No. 2 (1007: Cancel 207 in FIG. 1). In response to the cancel signal from the bus monitor (SNP) # 2, the bus interface unit # 2 cancels the waiting for the bus right and issues a cancel to its own cache memory # 2 and its own MPU # 2 (1008: FIG. 1 cancel 208). The cache memory # 2 that has received the cancel signal cancels the “invalidation request” requested in the above 1004, and the MPU # 2 temporarily stops the external access,
Preparation for retry of write access is started (1011).
In the case of the MC68040 processor, the cancellation to the MPU can be easily realized by simultaneously returning the transfer end signal and the bus error signal. Also, bus monitor # 2 is
Via the FIFO 209, data requesting invalidation of the line is issued to the cache memory # 2 (100
9). In response to this request, the cache memory # 2 changes the status of the line to an invalid state accordingly.

On the other hand, on the BPU # 1 side, the bus monitor # 2
Receives the signal indicating that the invalidation access has been detected from the BPU # 1, recognizes that the exclusive write state has been established, updates the data in its own cache memory # 1, and ends the processing ( 1010).

In BPU # 2, MPU # 2
The retry prepared in step 1 is executed (1012). At this time, since the line is in an invalid state, a request is made to the bus interface unit # 2 to read the line with the invalidation request (1013), and the latest data copied back from the BPU # 1 is cached. memory#
After that, the line is updated (1014).

In this embodiment, an MC68040 processor and a cache memory / bus interface unit / bus monitor configured as an external circuit are used.
It is possible to use another type of processor having an external access retry function instead of the 68040,
Further, it is apparent that a processor in which the cache memory / bus interface unit / bus monitor is integrated on one chip is also applicable.

[0026]

According to the present invention, even if a plurality of processing units try to update the same line at the same time, the processing unit that has acquired the system bus right can exclusively update the line. There is no need to worry about inconsistent data. Further, by using the external access retry function of the microprocessor, such an exclusive write state can be realized with simple hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a processing device configuring a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a multiprocessor system.

FIG. 3 is a configuration diagram of a cache memory shown in FIG. 1;

FIG. 4 is a configuration diagram of a bus monitor shown in FIG. 1;

FIG. 5 shows a format required for a cache memory.

FIG. 6 is a configuration diagram of a data section of a cache memory.

FIG. 7 is a configuration diagram of a tag unit of the cache memory.

FIG. 8 is a transition diagram of a tag state of the cache memory.

FIG. 9 is a diagram illustrating a tag state transition diagram of the bus monitor.

FIG. 10 is an explanatory diagram of an operation when an exclusive write state request is made.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... BPU, 2 ... memory, 3 ... peripheral devices, 4 ... system bus, 201 ... processor, 202 ... cache memory, 203 ... bus interface unit, 204 ... snooper (bus monitor), 209 ... FIFO, 207, 2
08: Access cancel signal.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Masayuki Tanji 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Omika Plant (56) References JP-A-2-287740 (JP, A) JP-A-2-184944 (JP, A) JP-A-4-95152 (JP, A) JP-A-4-251350 (JP, A) JP-A-3-25541 (JP, A) (58) Int.Cl. ⁷ , DB name) G06F 12/08

Claims (7)

(57) [Claims] 1. A memory for storing instructions and data, and a plurality of processing units connected to the memory via a system bus and processing data in accordance with the instructions in the memory, wherein each processing unit includes an instruction execution unit A copy-back cache memory connected to the instruction execution unit and storing a part of the contents of the memory; a bus interface connected to the copy-back cache memory and interfacing with the memory; cache of a device and a bus monitoring device for monitoring memory accesses are performed via a system bus connected to the memory
In the memory control method , the bus monitoring device has tag information having the same content as that of the copy-back type cache memory , monitors the memory access, and allows a processing device other than its own processing device to hold a line held by its own copy-back type cache memory. When an access for updating is performed, the access is detected, and the bus interface cancels the memory access request held in the bus interface. The bus interface responds to the cancel request, and the bus interface responds to the cancel request. A cache memory control method for canceling access to the bus interface held in the cache memory and canceling access to the copy-back type cache memory also to the instruction execution unit. 2. The bus interface according to claim 1, wherein the cancel of the bus interface is canceled by discarding a memory access request held in the bus interface.
So, cancel the copy-back type cache memory is canceled by discarding access, the instruction execution unit
Cancellation is canceled by retrying access
Cache memory control method comprising Rukoto allowed. 3. A memory for storing instructions and data, and a plurality of processing units connected to the memory via a system bus for processing data in accordance with the instructions in the memory, wherein each processing unit includes an instruction execution unit and A copy-back cache memory connected to the instruction execution unit and storing a part of the contents of the memory; a bus interface connected to the copy-back cache memory and interfacing with the memory; A cache memory control device including a bus monitoring device connected to a memory and monitoring a memory access performed via a system bus, wherein the bus monitoring device includes a tag information storage area having the same content as the copy-back cache memory, By monitoring the system bus, a processing device other than the own processing device Means for detecting whether or not to make an access to update a line held by a backup type cache memory, and a cancel request for canceling a memory access request held by the own bus interface with respect to the own bus interface and means, the bus interface, said copy-back against the instruction execution unit causes cancel the access to the bus interface that the in response to a cancellation request held in the copy-back type cache memory A cache memory control device comprising means for canceling access to a cache memory. 4. The bus interface according to claim 3, wherein said bus interface includes means for canceling by discarding a memory access request held in said bus interface, and said copy-back type cache memory cancels by discarding access. the provided, the instruction execution unit cache memory control device comprising a call <br/> with means for canceling by retrying the access. 5. The cache memory control device according to claim 3, wherein said processing device is constituted by a single chip. 6. An instruction execution unit, a copy-back type cache memory connected to the instruction execution unit for reading and storing a part of the contents of a main memory via a system, and a copy-back type cache memory connected to the copy-back type cache memory. A plurality of processing units including a bus interface for interfacing with a memory, and a bus monitoring device connected to the copy-back type cache memory and monitoring a memory access performed via a system bus and having an access retry function; Multiprocessor system cache
In the memory control method , the bus monitoring device may store
The memory held in the bus interface with respect to the bus interface when monitoring the re-access and detecting that a processing device other than the own processing device has made an access for updating the line held in the own copy-back type cache memory. to cancel the access request, the bus interface cancel access to the bus interface holding in response to the cancellation request to the copy-back type cache memory Rutotomoni,
The cancel access to the copy-back type cache memory to said instruction execution unit, then the command
The write access in response to the cancellation by the execution unit
A cache memory control method characterized by retrying the following. 7. An instruction execution unit, a copy-back type cache memory connected to the instruction execution unit, for reading and storing a part of the contents of a main memory via a system bus, and connected to the copy-back type cache memory. a bus interface for interfacing with the main memory, Ru with a retry function of the access becomes a bus monitoring device for monitoring memory accesses are performed via a system bus connected to said copy-back cache memory <br / In a multiprocessor system having a plurality of processing devices, the bus monitoring device includes means for detecting that a processing device other than its own processing device has made an access to update a line held by its own copy-back type cache memory; For the interface, the message held in the bus interface Key to cancel the re-access request
A Yanseru requesting unit, said bus interface
Includes means for canceling the access to the bus interface in response to the cancel request held in the copy-back type cache memory, canceling the access to the copy-back type cache memory to the instruction execution unit and means for, the instruction execution
The line section is for the write access in response to the cancel.
Multiprocessor system characterized by comprising means for causing a retry.