JP2902746B2 - Virtual computer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a multiprocessor system provided with a real vector computer, a virtual computer control method that makes switching control of a virtual vector computer more efficient, uses a VM monitor for saving and restoring vector registers. In order to reduce the overhead, a virtual vector computer is tied to a real vector computer and assigned so that a single real vector computer is not used by multiple virtual vector computers in competition as much as possible. An activation control unit and a dispatch control unit that saves and restores a vector register only when a real vector computer is used in competition with another virtual vector computer are provided. Also, a priority execution instructing means for externally designating a virtual vector computer to be preferentially executed, and an activation control unit for controlling the virtual vector computer for which the priority execution instruction has been issued to a specific real vector computer are provided. Constitute.

[Industrial applications]

The present invention relates to a virtual computer control method in a multiprocessor system including a real vector computer, which makes switching control of a virtual vector computer more efficient.

In order to process a large amount of data at high speed, a vector computer having a vector operation function called a supercomputer has been frequently used. Accordingly, it is necessary to realize a virtual vector computer in a virtual computer, and efficient allocation control is required.

 In the following description, the following terms are used.

• VM monitor means a control program that controls the entire virtual machine system.

・ VM-CPU is the CP of a virtual machine (VM)
Means U.

-Vector-CPU means a CPU that has a vector register (VR) and has a vector operation function.

-Vector-VM means a virtual machine having one or more vector-CPUs.

・ VM-vector-CPU is the vector-CPU of the virtual machine
Means

[Conventional technology]

Conventionally, when multiple VM-CPUs are operated on a computer that has a multiprocessor configuration, the VM-CPUs are assigned to a specific real CPU.
It was not tied to a specific real CPU, such as running on only one. That is, the VM monitor repeats the following processes (1) to (5).

(1) At the same time as restoring the contents of the registers used by the next VM-CPU, a special timer for giving time quantum is set.

(2) Transfer control to the next VM-CPU (dispatch the next VM-CPU).

(3) When the time set in the special timer arrives (this is called "time quantum end occurs"), an interrupt occurs in the VM monitor.

(4) Save the contents of the registers of the VM-CPU in which the time quantum end has occurred.

(5) Next, a VM-CPU to which control is to be passed is determined. The VM-CPU to which control is to be passed next is the VM-C with the highest execution priority among the VM-CPUs to which no real CPU has been assigned at that time.
PU. At this time, any VM-CPU has the right to be assigned the real CPU. This is why no VM-CPU is tied to a specific real CPU.

By the way, among CPUs, there is a so-called vector-CPU which is mainly good at scientific and technical calculations. Vector-CPU
Is in addition to the general-purpose registers that a normal CPU has,
It has a large capacity vector register (VR). Generally, since the capacity of the vector register is large, it takes a considerable amount of time to save and restore the vector register.

[Problems to be solved by the invention]

Become a time quantum end and replace the real CPU with another VM-CPU
When assigning to registers, it is necessary to save and restore registers including vector registers. However, according to conventional thinking, if the contents of vector registers are saved at each time quantum end and the contents of vector registers are restored at each dispatch, There is a problem that it takes time to perform those processes, and the overhead of the VM monitor increases.

An object of the present invention is to solve the above-described problem and to reduce the overhead of a VM monitor for saving and restoring a vector register.

[Means for solving the problem]

 FIG. 1 shows a configuration example of the present invention.

The hardware configuration of the virtual machine system for realizing the present invention is, for example, as shown in FIG.
Are configured to share the main storage device 10. Some of the CPUs 11-1, 11-2,... Have a vector register and can execute a vector operation instruction, and some have no vector register.

The configuration of the virtual computer system realized on this
This is as shown in FIG.

In FIG. 1 (b), 12 is a VM configuration information file for storing configuration definition information of a virtual machine, 13 is a VM monitor for controlling the entire virtual machine system, and 14 is a virtual machine switching at each time quantum end. A dispatch control unit that performs control, 15 is a start control unit that generates and starts a virtual machine, 16 is a command receiving unit that receives and processes commands related to operations of the virtual machine, 17 is an operator console for inputting commands and the like, Reference numeral 18 denotes priority execution instructing means, 19 denotes a queue for holding information on virtual machines having real CPU assignments, and VM1 and VM2 denote virtual machines.

When a command such as a VM creation command, a VM start command, or a VM end command is input from the operator console 17, the command receiving unit 16 executes a process specified by the command. In the VM generation command, information such as a VM identification name, the number of CPUs, whether or not to use a vector register, and an input / output device to be used can be specified as parameters. In particular, in the present invention, whether or not to execute the virtual vector computer with priority can be designated in this parameter.

When a VM generation command is input, the command receiving unit 16 analyzes the command and stores the analysis result in the VM configuration information file 12 as VM configuration information.

When a VM start command is input, the command receiving unit 16
Notifies the activation control unit 15 of the VM identifier to be activated. On the other hand, the start control unit 15 reads the configuration information of the relevant virtual machine from the VM configuration information file 12, generates the virtual machine, and creates a queue managed by the dispatch control unit 14.
Connect the management control table of the virtual machine to 19.

If there is a virtual vector computer that uses a vector register among the virtual machines to be activated, the activation control unit 15 prevents one virtual vector computer from conflicting with another virtual vector computer as much as possible. , And performs control of allocating a virtual vector computer to a real vector computer.

In addition, when a virtual vector computer to be executed preferentially is specified from the outside, the activation control unit 15 ties the virtual vector computer to a specific real vector computer and assigns another virtual vector computer to the specific real vector computer. Performs control that is not assigned to a vector computer.

The dispatch control unit 14 saves and restores the vector register only when the virtual vector computer is dispatched when a time quantum end occurs and the real vector computer is used in competition with another virtual vector computer. When there is no conflict with other virtual vector computers, only saving and restoring of general-purpose registers are performed, and saving and restoring processing of vector registers is omitted.

[Action]

 The problems of the prior art are as follows.

(1) When the time quantum end of the VM-vector-CPU occurs, a VM-vector-CPU different from the VM-vector-CPU may operate on the real CPU thereafter, and the contents of the vector register Must be evacuated.

(2) The VM-CPU to which control is to be passed next is the VM-vector-CPU
In this case, the content of the vector register on the real CPU at that time is not always the content expected by the VM-vector-CPU to which control is passed, and the vector register needs to be restored.

As is clear from the analysis of this problem, if there is one VM-vector-CPU running on one real CPU, the real C
There is no worry about the contents of the PU vector register being destroyed.
There is no need to save and restore vector registers.

The present invention focuses on this point, and the activation control unit 15 reduces the number of VM-vector-CPUs operating on one real CPU to one as much as possible, and the dispatch control unit 14 The save / restore process is omitted to reduce the overhead of the VM monitor 13.

〔Example〕

FIG. 2 is an explanatory diagram of the joining control according to the embodiment of the present invention, FIG. 3 is an explanatory diagram of saving and restoring of the vector register according to the embodiment of the present invention, and FIG. 4 is a CPU according to the embodiment of the present invention.
5 is an example of priority assignment according to the embodiment of the present invention, FIG. 6 is an example of stopping the connection to the real CPU in the embodiment of the present invention, and FIG. 7 is an example of the embodiment of the present invention. FIG. 8 shows an example in which starting of a new VM is not permitted, FIG. 8 shows an example of allocation to four real CPUs according to the embodiment of the present invention, and FIG. 9 shows a processing flow of the dispatch control unit according to the embodiment of the present invention.

In the example shown in Fig. 2, there are three real CPUs,
The PUs 11a and 11b have vector registers, and the real CPU 11c has no vector registers. The virtual machines VM1 to VM6 each use one CPU, and among them, VM1 and VM2 use vector registers.

When starting the VM1 and the VM2, the start control unit 15 shown in FIG. 1 performs a start with the real CPUs connected, such as operating the VM1 only on the real CPU 11a and operating the VM2 only on the real CPU 11b. . VM3 to VM6 without using other vector registers
The four units can be operated by arbitrary real CPUs 11a to 11c.

For example, as shown in FIG.
Therefore, when VM1 using the vector register and VM3 not using the vector register operate, VM3 does not destroy the contents of the vector register during operation. Therefore, when VM1 reaches the time quantum end, it is not necessary to save the vector register used by VM1.
Restoration is not required when the operation is resumed.

As shown in Fig. 3 (b), one real CPU
Only when two or more VM1 and VM2 using vector registers operate on 1, the vector registers need only be saved and restored.

According to the present invention, as shown in FIG.
Since the actual CPUs are connected so as not to cause a vector-CPU conflict, saving and restoring the vector registers can be omitted in most cases.

If the number of activated VM-vector-CPUs is greater than the number of real CPUs having vector registers, a conflict occurs.
It is also possible to prevent U from competing and speed up the processing.

Next, an example of the assignment when there are two real CPUs is shown below.
This will be described with reference to FIG.

1) Assume that the number of real CPUs is two. At this point, the VM
-Vector-CPU is not running.

2) When vector-VM1 is newly activated, the VM
-Vector-Check the number of CPUs.

If there is one VM-vector-CPU, the VM-vector-CPU is tied to the real CPU1 or real CPU2. Note that the selection order of the connection to the real CPU is, for example, the VM-vector-CPU in the real CPU to which the CPU has not yet been connected.
For example, a real CPU having the youngest CPU address or a real CPU having the oldest CPU address can be considered. For convenience of explanation, it is assumed here that it is attached to the real CPU1.

When VM1 uses two VM-vector-CPUs, one VM-vector-CPU is attached to the real CPU1 and the other VM-vector-CPU is attached to the real CPU2. At this time, the algorithm of connection to the real CPU is, for example, the lowest address VM-CPU
Can be tied to the real CPU at the youngest address.

In this case, there are no more than three VM-vector-CPUs. Because such VMs are checked at startup,
This is because it is not started.

3) Next, it is assumed that the vector -VM2 is activated. Also at this time, the VM-vector-CPU number is checked.

If the number of VM-vector-CPUs in vector-VM1 is one and the number of VM-vector-CPUs in vector-VM2 is also one, the actual CPU2 with no VM-vector-CPU attached
Next, the VM-vector-CPU of vector-VM2 is connected. In this case, there is only one VM-vector-CPU for VM1 and VM2, and since they are tied to different real CPUs, there is no competition between VM-vector-CPU and the overhead of the VM monitor increases. There is no.

In other cases, no matter how the VM-vector-CPU is tied to the real CPU, a conflict occurs. In this case, the following method can be adopted depending on the difference in the concept of how to handle the overhead of the VM monitor.

(A) Give priority to a specific VM-vector-CPU so that the VM-vector-CPU does not compete with others. This specification may be performed by, for example, a VM system user, or may be automatically determined by a VM monitor.

(B) The VM-vector-CPU that was previously tied to the real CPU without providing the priority VM-vector-CPU as described above
Also stop the control of the connection.

(C) The activation of the vector-VM in which the binding conflict occurs is not permitted.

Any one of (a) to (c) may be arbitrarily selected as an option of the virtual machine system.

FIG. 5 shows an example in which the above-mentioned (a) priority assignment is performed.

In the example of FIG. 5A, the second VM-vector-of VM2
There is a priority execution instruction for CPU2, and the actual CPU2 is attached. This VM-vector-CPU alone does not compete with other VM-vector-CPUs.

In the example of FIG. 5 (b), since there is a priority execution instruction for the VM-vector-CPU of VM1, the VM-vector-CPU
Runs only on real CPU2.

FIG. 6 shows an example in which the above-mentioned connection (b) is stopped.

Before starting VM2, the VM-vector-CPU of VM1 is
As a rule, when VM2 that uses two VM-vector-CPUs is started, a conflict always occurs. So in this example,
Stop connection to the specific real CPU for all VM-vector-CPUs. In this case, it is necessary to save and restore the vector register at the time of dispatch, as in the conventional case.

FIG. 7 shows a new VM in which the above-mentioned conflict (c) occurs.
An example is shown in which the activation of is not permitted.

The activation of VM1 is permitted because no conflict occurs at that time. If you try to start a new VM2,
Since a conflict occurs, the activation is not permitted, and the activation of VM2 is permitted after the termination of VM1.

FIG. 8 shows an example of assignment when there are four real CPUs.

1) The number of real CPUs is four. At this point, as shown in FIG. 8, VM1 to VM5 have been activated and conflicts have occurred, but each is tied to the real CPU.

2) Assume that VM2 has ended. At this time, since there is “vacancy” in the real CPU3, change the connection and change the VM-
Attach the vector CPU to the real CPU3.

3) After that, it is assumed that VM1 is terminated. An “empty” occurs in the real CPU 2. Therefore, the VM-vector-CPU of VM4 is attached to the real CPU1 and the real CPU2, respectively.

The number of real CPUs is not limited to two or four, and any number of CPUs can be similarly connected as in this embodiment. The connection information is, for example, the queue shown in Fig. 1.
It is managed by marking which real CPU can be operated in the control table of the VM-CPU connected to 19. For this mark, for example, a CPU address can be used.

The dispatch control unit 14 shown in FIG. 1 performs the processing shown in FIG. 9, for example, for each time quantum end. Hereinafter, description will be made in accordance with the flowcharts shown in FIG.

If the time set in the special timer comes and the time quantum end is reached, the target VM-CPU
Is a VM-vector-CPU. If it is not VM-vector-CPU, skip to the process and do not save the vector register.

If it is a VM-vector-CPU, it is checked whether or not the real CPU is used in competition with another VM-vector-CPU. If there is no conflict, the process proceeds.

Only when there is a conflict with another VM-vector-CPU, the contents of the vector register are saved.

Save other registers such as general-purpose registers.

Next, a VM-CPU to be given control is selected from the queue and determined.

It is determined whether the selected VM-CPU can be operated on a real CPU that has been operating and has become available. Other real C
If it is tied to the PU, it is inoperable, so it returns to the processing and performs the processing for the next VM-CPU.

It is checked whether the determined VM-CPU is VM-vector-CPU. If not VM-vector-CPU, go to processing.

If VM-vector-CPU, another VM-vector-C
Find out if there is a conflict with the PU. That is, it is determined whether the vector register needs to be restored. If there is no need to restore, move on to the process.

The vector register is restored from a predetermined save area.

Restore other registers.

Transfer control to the new VM-CPU and end dispatching.

〔The invention's effect〕

Saving and restoring a vector register takes a long time due to the large amount of data. However, according to the present invention, at the time quantum end of a virtual machine, the contents of all registers of the virtual machine must be saved and restored. Therefore, the overhead of the VM monitor on the vector computer is reduced. Further, when there are a plurality of virtual machines using the vector register, it is possible to perform processing at high speed by giving priority to a specific one.

[Brief description of the drawings]

FIG. 1 is a configuration example of the present invention, FIG. 2 is an explanatory diagram of a joining control according to an embodiment of the present invention, FIG. 3 is an explanatory diagram of saving and restoring of a vector register according to the embodiment of the present invention, FIG. FIG. 5 is an example of CPU allocation according to the embodiment of the present invention, FIG. 5 is an example of priority allocation according to the embodiment of the present invention, FIG. 6 is an example of stopping binding to the real CPU in the embodiment of the present invention, FIG. FIG. 7 is an example in which the activation of a new VM is not permitted in the embodiment of the present invention, FIG. 8 is an example of allocation to four real CPUs according to the embodiment of the present invention, and FIG. 9 is dispatch according to the embodiment of the present invention. The processing flow of the control unit is shown. In the figure, 10 is a main storage device, 11-1, 11-2,... Are CPUs, 12 is a VM configuration information file, 13 is a VM monitor, 14 is a dispatch control unit, 15
Denotes a start control unit, 16 denotes a command receiving unit, 17 denotes an operator console, 18 denotes a priority execution instruction unit, 19 denotes a queue, and VM1 and VM2 denote virtual machines.

Claims (2)

(57) [Claims] In a virtual computer control system in a multiprocessor system having at least one real vector computer, a plurality of virtual vector computers use one real vector computer so as not to compete with each other as much as possible. In addition, the activation control unit (15) that controls the virtual vector computer to be allocated to the real vector computer, and the case where the real vector computer is used in conflict with another virtual vector computer when dispatching the virtual vector computer And a dispatch control unit (14) for saving and restoring a vector register. 2. A virtual machine control method in a multiprocessor system having at least one real vector computer, wherein priority execution instructing means for externally designating a virtual vector computer to be executed preferentially; When a virtual vector computer to be executed by a user is specified from outside, the virtual vector computer is tied to a specific real vector computer, and the other virtual vector computers are
A start control unit (15) for performing control that is not assigned to the specific real vector computer.