JP2901882B2 - Computer system and method of issuing input / output instructions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a method for issuing input / output instructions in the computer system.
More specifically, the present invention relates to a computer system capable of giving a plurality of input / output instructions to a plurality of input / output devices by one input / output activation instruction, and a method of issuing an input / output instruction.

[0002]

2. Description of the Related Art A control method of an input / output device (input / output device) in a conventional computer system will be described. Lord C
When a PU (central processing unit) performs an input / output operation,
Send an I / O command to an I / O device. As a result, the input / output device starts processing. After sending the input / output command to the input / output device, the main CPU can perform other tasks until the transfer of the input / output data is completed. The input / output device notifies the main CPU by an interrupt when the processing is completed.

The above method reduces the load on the main CPU. In an actual computer, an input / output adapter (called an input / output channel in some computers) is interposed between the main CPU and the input / output device, and a plurality of input / output devices are connected to the input / output adapter. Connected.

FIG. 31 shows a reference (Harry Katzan, Jr .: Comput).
er organization and the system / 370, Van Noatrand Re
inhold Company, 1971). An input / output architecture with an input / output device using an input / output channel will be described with reference to FIG.

[0005] The main CPU issues an input / output activation command 20 to start an input / output operation. The input / output activation instruction 20 is
Includes instruction code, channel address, and device address. The channel address and the device address are addresses for specifying an input / output device for performing an input / output operation and an input / output channel.

The CAW (Channel Address Word) 21 is
The first CCW (Channe
l Command Word) 22 stores the address on the main storage device. The CCW 22 provides information about an input / output operation to be performed to the input / output channel. CCW
22 is a command code, data address, count,
And flags. The flags are cd flag and c
Contains the c flag.

The command code of the CCW 22 specifies an operation to be executed, for example, an input or an output. The data address specifies the head address of the data 23 to be subjected to the input / output operation. The count specifies the number of bytes used for input / output operations.

The cd flag specifies a data chain. The data chain indicates that the same input / output operation is performed on different data areas in the next CCW. The cc flag specifies a command chain. The command chain indicates that a different input / output operation is performed in the next CCW. All bits of the flag are 0
Indicates that the CCW 22 is the last CCW.

The CSW (Chan-nel Status Word) 24 is
It is recorded after an input / output interrupt or an input / output start command is received, and indicates the state (busy or the like) of an input / output device or an input / output channel.

A procedure for executing an input / output operation in the above input / output interface will be described below. First, the main CPU operates as follows.

The required CCW 22 is made. It may be prepared in advance or created during execution of the program. As shown in FIG. 31, there may be a series of a plurality of CCWs 22 called a channel program. The CAW 21 is set (the address of the head CCW 22 is set). Load channel address and device address. Disable I / O interrupts. Issue an input / output activation instruction 20.

When the main CPU executes the input / output
After issuing 0, the I / O channels of the computer system
It works as follows.

The channel takes out the CAW 21 and checks the validity. The channel retrieves the CCW 22 and checks its validity. Executes input / output operation by the specified device. The completion information of the input / output operation is recorded in the CSW 24. An input / output interrupt is activated from the input / output channel.

[0014]

In the above-described input / output interface, an input / output activation instruction (a set of a series of CCWs 22 shown in FIG. 31) is issued once, so that a single input / output device can be executed a plurality of times. Can be continuously performed. Now, consider a case in which input / output operations for a plurality of input / output devices are continuously performed with such a conventional input / output interface.

FIG. 32 shows an input / output operation procedure in an input / output interface with a plurality of input / output devices via an input / output adapter (input / output channel). In particular, a case where an input / output instruction 1 for the device 1 and an input / output instruction 2 for another device 2 are successively issued is shown.

First, the CPU issues an input / output instruction 1, and in response to this, the input / output adapter performs input / output operations with the device 1. While the input / output adapter is performing input / output operations with the device 1, the CPU can perform other tasks. When the input / output operation with the device 1 is completed, the input / output adapter issues an interrupt, and the CPU performs interrupt processing 1, whereby the input / output is completed. Continue with CPU
Issues an input / output instruction 2, and executes input / output with the device 2 in the same manner.

As described above, in the input / output operation of the conventional input / output device, the input / output command for one input / output device is issued, the other work is processed, and the end of the input / output device operation is known by the interrupt. Therefore, when inputting / outputting data to / from a different input / output device continuously, the input / output command must be issued again. That is, it is necessary to issue an input / output command for each input / output device.

By the way, in recent years, with the performance improvement of CPU,
In particular, a technique such as a cache memory is used to speed up memory access. On the other hand, the speed of the input / output device has not increased much. Therefore, C
The speed difference between the PU and the input / output device has increased.

For example, in a multi-line connection communication server computer, it is necessary to connect a large number of input / output devices in order to cope with multi-line. Directly connect these input / output devices to CP
When connected to the U bus, due to the speed difference mentioned above, CP
U performance cannot be used effectively.

In order to avoid this, there is an idea to measure the hierarchies of the buses (the main bus and the I / O bus are separated and both are connected by a bus adapter). However, when the bus is hierarchized, the distance between the CPU and the input / output device becomes large as a result. The command and the end interrupt operation are executed via the bus adapter. Therefore, CPU performance, I / O performance, and bus performance are consumed for such an operation. This is a significant problem particularly for a communication server for multi-line connection. Hereinafter, the reason will be described.

FIG. 33 shows an example of a large-scale online processing system using a communication server computer (hereinafter simply referred to as a communication server) 100 for a multi-line connection, which is a conventional example and an application example of the present invention.

The communication server 100 exists in the head office and in each local branch. Communication server 100 in branch
, A plurality of in-store terminals 101 are connected via a telephone line, and a large number of remote terminals 101 are connected via a public network. The head office has a host computer 102 which manages a large-scale database. The host computer 102 and the communication server 100 at the head office have a high-speed L
They are connected by FDDI which is AN. The communication server 100 at the head office and the communication server 100 at the branch are connected by a high-speed line.

A request for updating the database is sent from each terminal 101 to the host computer 102 via the communication server 100. After the database is updated, a response is sent from the host computer 102 to the corresponding terminal 101 again via the communication server 100. Sent. Such processing is called transaction processing. In particular, accounting transaction processing is
Occurs during a specific period, such as before a holiday. Since these are all processes involving the input / output operations of the communication server 100, the input / output overhead due to a large number of input / output devices (lines) generated in a concentrated manner poses a problem in the communication server 100.

As described above, in the conventional example, it is possible to perform a plurality of input / output operations for one input / output device by issuing an input / output activation instruction once, but to issue the input / output activation instruction once. Since a plurality of input / output operations cannot be performed for a plurality of input / output devices, input / output overhead in a communication server or the like has been a problem.

A first object of the present invention is to provide a device (including an input / output interface information format) capable of executing a plurality of input / output commands for a plurality of devices with a single input / output command, and an input / output adapter capable of receiving the input / output commands. (Input / output channel) The purpose of this is to provide a control mechanism (processing logic) for the device.

A second object of the present invention is to provide not only a mechanism for issuing a command group but also a mechanism for issuing a command group of an amount corresponding to the state (acceptability) of an input / output adapter, in other words. It is another object of the present invention to provide an input / output interface which allows the user to easily understand how many command groups can be accepted without being busy.

Another object of the present invention is to provide a method for efficiently issuing a command group consisting of a read command for instructing an input operation in data transfer via the input / output adapter device.

Another object of the present invention is to provide an efficient command group issuing method related to communication protocol processing, particularly window control and packet division processing, in data transfer via the input / output adapter device.

[0029]

SUMMARY OF THE INVENTION The present invention provides a plurality of input / output devices, an adapter device coupled to the plurality of input / output devices, and an input / output request to the input / output devices via the adapter device. In a computer system having a main processing device, a plurality of input / output commands for a plurality of input / output devices are issued as one input / output activation command from the main processing device. A plurality of input / output commands for a plurality of input / output devices included in the instruction are specified as input / output commands to which input / output device, and the input / output commands are provided to the specified input / output devices. .

If the main processing unit cannot immediately process the I / O request, the I / O request is stored and managed in a waiting request management table. In accordance with the I / O requests stored in the waiting request management table, a command sequence, which is a sequence of I / O commands to be given to each I / O device, is created for each I / O device. 1
Is issued to the adapter device as an input / output activation command for the first time.

The process of issuing a plurality of I / O requests stored in the wait request management table into one I / O activation instruction and issuing the I / O requests as described above is triggered when the I / O requests can be processed as described above. However, in addition, the processing may be performed when the processing of the input / output command is completed and a termination interrupt is issued from the input / output device to the main processing device.

The plurality of command strings are, for example, a block including, as a basic unit, a block including address information for specifying a head position of the command string and identifier information for specifying one input / output device to be executed by each command in the command string. The block is managed by a table having a structure in which a plurality of blocks are continuous.
Flag information indicating whether or not the data has been taken into the adapter device from the main processing device may be provided.

The main processing unit roughly includes an application execution unit for issuing an input / output request to the input / output device, and a driver unit for creating an input / output command from the input / output request and issuing the command to the adapter device. . In particular, it is preferable that, before the driver unit receives a data input request from the application execution unit, a plurality of input commands for a plurality of input / output devices are sent to the adapter device as one input / output activation command.

More specifically, a first storage means for storing a first specified number indicating the maximum number of input commands issued to the input / output device, and a trigger for re-issuing the input command sequence. Second storage means for storing a second prescribed number and third storage means for recording the number of uncompleted input commands for each input / output device are provided. A sequence of input commands for a specified number of 1 is created for each input / output device and issued to the adapter device, and the number of input commands issued to each input / output device is recorded in the third storage means. Each time a completion report of an input command is received from each of the input / output devices, the number of incomplete input commands of the corresponding input / output device stored in the third storage means is reduced by one. Completion input frame When the number of commands reaches the second prescribed number, the difference between the number of uncompleted input commands stored in the third storage means and the first prescribed number recorded in the first storage means is calculated. An input command sequence in which input commands are repeated by the number of the differences is re-issued to the adapter device.

When the input / output device is a line control device, the protocol processing unit divides the data relating to the data transfer request issued from the application execution unit, and places the communication protocol control at the beginning of each of the divided output data. A plurality of fragmented packets are created by adding information. At this time, if the number of the plurality of divided packets is equal to or less than the number of continuous transfers, which is the number of packets that can be continuously transferred without a delivery confirmation from the other party at that time, based on the plurality of divided packets, By generating a plurality of input / output commands and issuing the generated plurality of input / output commands as one input / output activation instruction, the output data of the plurality of divided packets can be transferred by one input / output operation. I do.

When data is divided into a plurality of packets and transmitted by such protocol processing, a header (communication protocol control information) is added to the head of each of the divided output data. At this time, the header portion and the output data constitute one logically connected packet, but actually exist in another area, and each may be managed by another data management information block. is there. In this case, since the command is created for each data management information block, the command for transferring the header portion and the command for transferring the output data are connected by a data chain, that is, a plurality of commands. Therefore, according to the present invention, when necessary, the header section and the output data are set in a physically continuous area, repacked so as to point to one data management information block, and passed to the driver section. Thus, the driver unit can execute the command as one command.

Whether to perform refilling is determined based on the magnitude of the overhead. That is, by comparing the overhead required for the adapter device to process the command for transferring the communication protocol control information with the overhead required for copying the output data to an area continuous with the communication protocol control information, the latter overhead is reduced. If it is smaller, refill it. In other words, the time required for the adapter device to follow a chain (data chain) between commands is equal to the time required for the main processing device to copy data of a certain length. When transmitting input / output data in which the header part created by the protocol processing and the user data part are connected by a chain, before creating the command,
The output data length is determined, and if shorter than the reference value, the user data is copied to an area after the header part. That is, the header and the user data are recreated into one continuous input / output data.

[0038]

A plurality of input / output commands for a plurality of input / output devices are issued from the main processing unit as one input / output activation instruction, and the adapter device outputs a plurality of input / output commands included in the one input / output activation instruction. Since a plurality of input / output commands for a device are specified as input / output commands to which input / output device and the input / output commands are given to the specified input / output device, a plurality of input / output commands are issued by one input / output start command. An input / output operation of the output device is performed.

A plurality of command strings to be collectively passed to the adapter device are managed by a table having a structure in which a plurality of blocks including the address information and the identifier information for specifying the input / output device are continuous. By providing flag information indicating whether or not the data is taken into the adapter device from the device, it is possible to smoothly exchange a command string between the main processing device and the adapter device. Commands can be requested at once.

By sending a plurality of input commands to a plurality of input / output devices to the adapter device as one input / output activation command, the overhead of the input operation can be reduced.

In the case where data is divided into a plurality of packets and transmitted by the protocol processing, a series of command sequences including output commands for transferring the packets for the number of packets that can be transmitted at one time are created. When the command sequence is executed by the input / output operation of the driver unit,
By one input / output activation instruction, a plurality of divided packets are collectively transferred to the input / output device side.

According to the present invention, when necessary, by performing the above-described refilling process, the data transfer process can be executed as continuous data from the position indicating the header portion without the adapter device following the data chain.
Thereby, the input / output processing overhead including the input / output adapter processing can be optimized.

[0043]

Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, five embodiments 1 to 5 will be described. Before that, a basic processing procedure in the input / output interface according to the present invention will be described with reference to FIG.

In FIG. 1, the CPU starts the input / output operation for the two input / output devices 1 and 2 by issuing one input / output instruction. When the CPU issues only one input / output instruction, the input / output (IO) adapter continuously performs input / output operations with the device 1 and input / output operations with the device 2. The IO adapter interrupts the CPU when the input / output operation with the device 1 is completed, and the CPU performs interrupt processing 1. After interrupt processing 1, the CPU
It is not necessary to issue an input / output activation command for the device 2, and another task can be performed. When the input / output operation with the device 2 is completed, the IO adapter interrupts the CPU, and the CPU performs interrupt processing 2.

An embodiment of the present invention which operates according to such a basic procedure will be specifically described below.

(Embodiment 1) This embodiment shows an embodiment in which the input / output adapter device is an input / output channel device.

FIG. 2 is an explanatory diagram focusing on the functional structure of a computer system using an input / output channel device to which the present invention is applied, particularly the function of an input / output channel (hereinafter, referred to as CH) 142. The CPU 140 is a central processing unit of the CISC type. The MS 141 is a main storage device.
The CH 142 is mutually connected to the CPU 140 and the MS 141 via a bus.

The IOCU 147 is an input / output control device, and is connected to the CH 142. Also, one CH1
A plurality of IOCUs 147 are connected to 42. Similarly, one IOCU 147 is connected with a plurality of input / output devices (hereinafter, referred to as DEVs) 148. I
The OCU 147 controls the connected DEV 148.

The CH 142 includes a bus interface control unit 143, a data transfer control unit 144, and a CCW execution unit 14.
5 and an IOCU control unit 146.
The bus interface control unit 143 receives an input / output start command, notifies an interrupt to the CPU,
This is a block for controlling the access to the device 1 and the like. CC
The W execution unit 145 is a block that analyzes the CCW and controls data transfer such as transmission and reception. IOCU control unit 14
6 is an IOC according to an instruction from the CCW execution unit 145.
This block controls the path to U147. The data transfer control unit 144 transfers data on the MS 141 to the IOCU 147 according to an instruction of the CCW execution unit 145,
Alternatively, it is a functional block for storing data from the IOCU 147 in the MS 141.

FIG. 3 shows the configuration of the CH 142 and the CPU 140 of FIG.
FIG. 3 is a diagram for explaining an interface definition with the interface, particularly showing an interface expression of a portion different from the conventional one in detail.

In FIG. 3, the input / output activation instruction 200 is
This is obtained by adding an extension flag 201 to the conventional input / output activation instruction 20 shown in FIG. When giving a plurality of IO commands to a plurality of devices, the CPU 140
Turns on the extension flag 201 and sends the input / output activation instruction 200 to the CH device (IO
To which the device DEV 148 desired to perform is connected
Device) 142. At this time, the device address information in the input / output activation command 200 has no meaning.

The extended CAW 301 is obtained by adding a stop bit 302, a channel address 303 and a device address 3
A block (hereinafter referred to as a command block) to which the command 04 has been added is sequentially arranged in plural numbers (for the number of devices that give commands) from a predetermined fixed address on the MS 141.

The command address in the command block indicates the head address of the CCW column as in the prior art. Also, a channel address 303 and a device address 304
Is address information for identifying a target device that executes the CCW sequence. Each CC constituting the CCW column
W22 is the same as the conventional CCW22 of FIG.

Stop bit 30 in command block
Reference numeral 2 denotes information indicating whether or not the command block is the last command block of the extended CAW 301.
The stop bit of the last command block is on (1), and the stop bits of the other command blocks are off (0).

The CPU 140 sets the above interface information and executes the extended input / output start command 200. Upon receiving this, the CH 142 starts the input / output operation according to the setting.

FIG. 4 is a flowchart showing the main processing logic of the CH 142. The CH 142 that has received the extended input / output activation instruction 200 first takes in the first command block of the extended CAW 301 starting from the determined address into an internal register (step 310).
1). Next, processing of the CCW column indicated by the command address of the fetched command block is executed (step 3103).

Next, the stop bit 302 of the fetched command block is checked (step 310).
5). If the stop bit is on, that is, if the value is 1, the process is terminated. If not, the pointer pointing to the command block of the extended CAW 301 to be fetched is updated (step 3107), and the processing is executed again from step 3101. That is, the processing of the CCW sequence is repeated until the stop bit of the extended CAW 301 becomes 1.

FIG. 5 shows the CC of the above-mentioned processing step 3103.
It is a processing flowchart of W execution processing. This processing has the same logic as the conventional one, but this will be described.

First, the head CCW of the CCW column indicated by the command address of the fetched command block is fetched (step 3201). Next, a path is opened by selecting the target device DEV 148 identified by the device address of the fetched command block (step 3203). Next, a command is issued to the target device, and a response is waited (step 3205).

Next, data transfer processing is performed using the data transfer control section 144. Note that the data transfer control unit 144
Also performs a CCW data chain process (step 32).
07). Next, check the CCW command flag,
If the command chain flag is on, step 321
Go to step 5; otherwise, go to step 3211 (step 3209).

Step 3215 is a process for fetching the next CCW. Thereafter, the process is repeated from step 3205 again. Step 3211 is a process of creating an end status. Finally, an interrupt to the CPU 140 is generated (step 3213). This concludes the description of the CCW execution process.

Next, the process of issuing input / output commands for a plurality of devices on the CPU 140 side will be described. Here, a case where CPU 140 issues an input / output command for data communication will be described as an example.

FIG. 6 shows the relationship between the detailed configuration of the processing program executed by CPU 140 for data communication and CH 142. The communication management 340 provides communication services (data transmission and data reception) for a plurality of application programs (APs) 34. The communication management 340 includes a manager (MGR) 341 for managing computer resources such as buffers and timers, an application interface (API) 342 for receiving a communication request from the AP 34, and processes and controls communication data according to a communication protocol. And a driver 345 for controlling the interface with the CH 142.

Various input / output requests for data communication are issued from the AP 34 to the communication management 340. Communication management 34
0, the API 342 is set to A under the management of the MGR 341.
Accepts an input / output request from P34 and executes protocol processing 3
43 processes and controls the communication data and issues an input / output request to the driver 345. The driver 345 sets the various information described in FIG. 3 in response to the received input / output request, and issues an input / output activation command 200 to the CH 142.

FIG. 7 shows a management information table referred to when the driver 345 issues an input / output activation command.

The wait request management table 330 is a table for storing the request 33 from the upper protocol processing 343 when the driver 345 cannot immediately process the request 33 (CH 142 is busy or the like). The request 33 from the host includes the address of the buffer 30 for storing the data (PDU) used by the protocol processing 343, together with the address of the next request and the type of request (transmission / reception). The waiting request management table 330 indicates that these requests 3
In order to manage the number 3, the start address of the series of requests 33, the last address thereof, the number of the series of requests, and the like are held.

The completion wait management table 331 is stored in the CH 14
2 has been issued and CH142 is still
This is a table for managing commands for which no command end response has been returned. The configuration and management method of this table 331 are the same as those of the wait request management table 330.

FIG. 8 is a flowchart showing the processing logic of the driver 345 after receiving the request 33 from the higher-level protocol processing 343.

First, the driver 345 examines the waiting request management table 330, and finds that there is no request waiting and
It is checked whether the state of the CH 142 is not busy (step 3501). If there is no request waiting and the CH 142 is not busy, the process proceeds to step 3503. If there is a request waiting or if CH142 is busy, step 3
Proceeding to step 509, the waiting request management table 330 is updated to enqueue the newly received request 33 (step 3509). Then, the process ends.

If the determination in step 3501 is true, a CCW sequence is created according to the request 33 (step 3).
503). Next, the extended CAW 301 is created by setting the head address of the CCW string created in the above step (step 3505). Next, CH14 to be activated
2 is loaded, and an input / output start instruction 200 is issued (step 3507).

The above is a description of a series of processes for issuing a command in response to a request from the higher-level protocol process 345.

FIG. 9 is a flowchart showing the command reissue processing logic of the driver 345 after receiving a termination interrupt from the CH 142. When receiving the end interrupt from the CH 142, the driver 345 executes the end interrupt processing. After executing the end interrupt processing, the driver 345 executes the command reissue processing of FIG.

First, the driver 345 checks the waiting request management table 330 to determine whether there is a request waiting and
It is checked whether the state of CH 142 is not busy (step 3601). If there is a request waiting and CH 142 is not busy, the process proceeds to step 3603. If there is no request waiting or the CH 142 is busy, the process ends.

At step 3603, it is checked whether or not there is a waiting request in the waiting request management table 330 (step 3603). If there is a waiting request, the waiting request is dequeued from the waiting request management table 330 (step 3605), and the CCW is executed in accordance with the dequeued request 33.
A column is created (step 3607). Then, the extended CAW 301 is created by setting the head address and the like of the CCW column created in the above step (step 360).
9). Next, the processing from step 3603 is repeated again.

As described above, steps 3603 to 3609 are performed.
Is repeatedly executed for all the waiting requests in the waiting request management table 330 to create the CCW column and the extended CAW 301 as described with reference to FIG.

If no waiting request is found in step 3603, the stop bit of the extended CAW 301 is set (step 3611). Specifically, the extended CAW 301
Of the last command block is turned on (1), and the stop bit of the previous command block is turned off (0). Next, CH142 to be activated
Is loaded, and the input / output start instruction 200 is executed (step 3613).

When the waiting request is dequeued from the waiting request management table 330 in step 3605, the dequeued waiting request is added to the completion waiting management table 331. Then, when the input / output processing ends and an interrupt is issued from the CH 142, the completion of the input / output is confirmed in the end interrupt processing, and the waiting request is deleted from the completion waiting management table 331.

The description of the command reissuing process after accepting the end interrupt has been completed.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings. The second embodiment is an example in which the present invention is applied to the communication server 100 described with reference to FIG.

FIG. 10 shows a communication server 1 to which the present invention is applied.
FIG. 2 shows a hardware configuration of 00. The display 121 is a display device for displaying a message for an operator (or an operator). The keyboard 122 is an input device for an operation command given by the operator. The CPU 123 is a processing device for software such as an online processing program. MU (storage unit)
124 stores the software programs, various control tables and buffers. CPU123
And the MU 124 are connected by a main bus.

The main bus includes a BA (bus adapter) 1
An input / output bus 25 is connected to the input / output bus 25. The reason for separating the main bus and the I / O bus is that if the CPU is directly connected to the slower I / O device, the bus speed must match the speed of the slower I / O device.
This is because the performance is deteriorated.

Further, the communication server 100 includes a DKU (disk unit) 129 and an MCI (multi-line controller) 1
23 and the like. These input / output controller and input / output bus are connected to an IOA (input / output adapter) 12.
8 are connected. In particular, the MCI 130 has one I
A plurality of OAs 128 are connected via a local bus (SCSI bus). The reason is that, since the number of lines 131 that can be connected to one MCI 130 is limited, depending on the business scale of the user, it is necessary to connect a plurality of MCIs 130 as described above to connect a large number of lines. is there. The input / output bus includes an FDDIA (FDDI adapter) 126, which is a high-speed LAN adapter device, and a CCU.
(Console control unit) 127 is connected.

This embodiment is, of course, a different embodiment from the first embodiment described above.
The IOA 128 of FIG. 10 corresponds to the CH 142 of the first embodiment, and the MCI 130 corresponds to the IOCU 147 and the DEV 148 of the first embodiment.

The outline of the input / output operation will be described based on the configuration of the apparatus shown in FIG. The IOA 128 starts its input / output operation by receiving an input / output command from the CPU 123 via the BA 125. For data transmission, I
The OA 128 transfers the data specified by the MU 124 to the corresponding MCI 130. In the case of data reception, BA125 is assigned from the MCI 130 to the designated area of the MU 124.
To transfer data through. The MCI 130 has a buffer for storing data.

As described above, the CPU 123 has the authority to transfer data between the MCI 130 as the input / output control device and the MU 124. The input / output command from the CPU 123 includes an instruction to the IOA 128 and the line 13
1. This input / output command is
Execution of I130 causes data communication via the line.

FIG. 11 shows information stored in the MU 124. It consists of three main parts. The three parts are an execution program of various software, a reference table thereof, and a buffer area.

Various kinds of software include an OS kernel for performing storage management and process management, a console control for performing input and output with the display 121 and the keyboard 122,
A control software group includes a file management for updating a log file and the like, a communication management for performing data communication via a line and an FDDI, and various application programs for online processing. A reference table and a buffer area are provided for each.

The communication management program is the same as the communication management program 340 described with reference to FIG. In particular, the driver in the communication management program prepares interface information having a structure shown in FIG.
An I / O activation command is issued to the IOA 128. Hereinafter, when describing the communication management driver and the protocol processing of the second embodiment, the numbering shown in FIG. 6 is used.

FIG. 12 is a block diagram showing the internal structure of IOA 128. The IOA 128 includes the following functional blocks. A bus interface LSI 401 for controlling an interface between an external bus, which is an input / output bus, and a local bus, which is an internal bus of the IOA 128, and an MPU 402, which is a processing device similar to the CPU (to be distinguished from the CPU 123 which is a processing device of the main body 100, MPU), local memory (LM) 403, and SCSI
The protocol processor 404.

The instruction from the CPU 123 to the IOA 128 is accepted by the bus interface LSI 401.
It is. The bus interface LSI 401 is composed of the following four functional blocks. The external bus control unit is a block that controls opening and closing of a data bus path and controls an interrupt signal to the CPU according to the value of the address signal of the CPU. The architecture register control unit uses C
This is a block for controlling a register group for interface with the PU 123 and access to the register group (writing of input / output information, interruption to the MPU 402, etc.). The external bus-local bus conversion unit is a block that performs mapping between an address signal on the external bus and an address signal on the local bus. The local bus control unit is a block that controls opening and closing of the local bus.

The local memory (LM) 403 has an IO
A control program (C / W object) and information (command entry, command chain, trace, work) necessary for control are recorded. For this information,
It will be described later. The SCSI protocol processor 404 uses S
It has both a SCSI control unit having a CSI bus control function and a data transfer control unit having a DMA transfer function.

FIG. 13 shows IOA1 via the SCSI bus.
This is an internal structure of the MCI 130 that performs data input / output processing for each line according to a series of commands passed from the MCI 28. The MCI 130 is roughly composed of the following two parts. LP510 and LC520.

The LP 510 is a processor module that processes the communication protocol of the second layer. On the other hand, LC52
Reference numeral 0 denotes a processor module that processes an interface with a physical line, and a plurality of processor modules exist. The LP 510 corresponds to the IOCU 147 of the first embodiment, and the LC 520 corresponds to the DEV 148 of the first embodiment.

The LP 510 includes a SCSI controller 511 for controlling a SCSI bus interface, a SCSI controller memory 512, a global memory 513 serving as a buffer for communication data, an MPU 514, and an MP.
It comprises a U memory 515. On the other hand, LC520 is LC
An LCP 521, which is a processor device for LCP, and an LCP memory 522.

Referring to FIGS. 14 and 15, an input / output sequence in this embodiment will be described. FIG. 14 shows a sequence at the time of data transmission. FIG. 15 shows a sequence at the time of data reception.

Referring to FIG. 14, a sequence at the time of data transmission will be described. The CPU 123 first executes the command 505
(Described later) is created and set in the command entry 504 (described later). Next, the IO command register 501
By accessing (described later), the IOA 128 is activated. Next, the activated IOA 128 fetches the command entry 504 into the LM 403. IOA128
Finds the command from the fetched command entry information and analyzes its contents. And the target M
After connecting the bus with the CI 130, a command is issued to the MCI 130. The above sequence operation is
The same applies to the data reception in FIG.

First, the transmission operation will be described. After sending the send (send) command, the IOA 128
The transmission data is DMA-transferred from the MU 124 to the global memory 513 of the MCI 130. The MCI 130
The IOA 128 that has received the data transfer completion notification from the
At the same time as releasing the CSI bus, the completion information is
Write to. And by the command end interrupt,
Inform the CPU 123 of the end of the command. The CPU 123 activated by the interruption checks the completion information.

Next, the reception sequence will be described with reference to FIG. As described above, the sequence up to before the transmission of the reception (read) command is the same as that in FIG.

After transmitting the reception (read) command,
IOA 128 waits for a signal from MCI 130.
If there is no received data in the MCI 130, the IOA 12
8 releases the bus in response to a bus release request from the MCI 130. After receiving the data, the MCI 130 issues a reception notification to the IOA 128. IOA1 that received the notification
28 reconnects the bus with the MCI 130,
The received data is transferred to the MU 124 by the A transfer. The subsequent sequence is the same as the case of the transmission described with reference to FIG.

FIG. 16 shows a CPU referred to during input / output operations.
FIG. 4 is a diagram showing a relationship of interface information between IOAs. In this embodiment, since a RISC processor is used for the CPU 123, a dedicated instruction cannot be used as an input / output activation instruction. Therefore, a memory mapped IO method is adopted as the IO method. This is because a part of the memory space of the CPU 123 is stored in the IO command register 501 of the IOA 128.
This is the method assigned to. Executing a load instruction for this address refers to accessing the IO command register 501, which is equivalent to issuing an input / output activation instruction.

The command entry address 502 is the MU
It is information arranged at a fixed address in the IP address 124 and records the address of the first command entry 504 to be read by the IOA 128. Of course, IO
A128 knows the address of the command entry address 502. The command interface 503 is
This is an array (array) in which two command entries 504 are continuously arranged. By arranging the powers of two, IO
The pointer update in the command entry reference processing of A128 is simplified.

Each command entry 504 contains a command 5
It has a pointer to 05. The command 505 has information of the transfer area 506 and pointer information to the next command 505. Command 505 is the next command 50
5 are linked by a pointer to 5 to form a command sequence. 1
Since one command entry 504 points to a single command string, a plurality of command strings are pointed by the command interface 503 as a whole.

The transfer area 506 is an area for storing transmission data at the time of transmission, a buffer for storing reception data at the time of reception, and an area for storing reception data after completion of a command.

FIG. 17 is a diagram describing the command 505 in detail. The next command address is pointer information for composing a command string, and is a pointer to the next command 505. The flag eoc is information indicating the end of the command sequence. When the flag eoc is 0, it indicates that the next command exists after the command, and the flag eoc
Indicates that the command is the last command in the command sequence. The device ID is information for identifying a line.

The flag area includes the following three flags. The three flags are dc, crep, and int.

The dc flag is a flag for forming a data chain. A data chain is when the command is the same as the next command. That is, when the next command is a command for performing the same input / output operation as that command for another data area, the dc flag of the command is set to 1. Otherwise, dc
The flag is set to 0. Different commands are referred to as a command chain. The crep flag is information for instructing creation of completion information when the operation by the command is completed. The int flag is information instructing generation of a termination interrupt when the operation by the command is completed. In this embodiment, the specification is such that completion information is received by interruption after each command is completed.

The IOA command is information meaning a DMA start request. The transfer area address is the address of the transfer area 506 described above, and the transfer length is that length. The SCSI command is a command (read / send, etc.) to be executed by the MCI 130. The completion information area is an area where the IOA 128 records the completion information. The command 505 is composed of eight words so that the IOA 128 can easily refer to the command.

FIG. 18 is a diagram describing the command entry 504 in detail. The flag busy is set to IOA128
Changes the command entry 504 from the MU 124 to the LM4
03 is a flag indicating whether or not the data has been captured. That is, the CPU 123 stores the command entry 504 in the MU12
When creating in IOA4, set 1 and IOA12
8 is activated, and the IOA 128
When "04" is read, "0" is set.

Device ID in Command Entry 504
Is identifier information that is the same as that of the command 505 and indicates a device (line in this example) that performs input and output. The device I of the command entry 504
One device designated by D is a target of input / output of a series of commands 505 pointed from the command entry 504. Therefore, each command 5 in FIG.
It can be said that there is no need for the device ID column of 05,
It is provided for use in processing at the time of failure.

Referring again to FIG. 18, a value indicating DMA transfer is written in the command entry command in command entry 504. The command string start address is
This is the address of the command 505 at the head of the command sequence.
The failure information storage address is an address of an area for storing information at the time of failure occurrence. The fault information storage area length is the size of the above area. The command entry 50
4 is composed of eight words so that the IOA 128 can easily refer to the word.

Next, the processing logic of the IOA 128 will be described. FIGS. 19, 20 and 21 are flowcharts for explaining the processing logic of the MPU 402 in the IOA 128 shown in FIG. FIG. 22 shows an information structure on the LM 403 referred to by the processing logic.

Before describing the processing logic of the IOA 128, the information structure on the LM 403 will be described with reference to FIG. The command entry copy management table 580 includes:
This is a table for managing the command entry fetched from the MU 124 by the IOA 128. The command entry copy 581 is a table for storing a copy of the fetched command entry and the like. The execution command processing table 582 is a table that is referred to when processing a command.

Command entry copy management table 58
0 manages a series of command entry copies 581 linked by a chain, so that the address of the first command entry copy 581 and the last command entry copy 5
81 are held. The command entry copy number is the number of command entry copies 581 managed by the table 580. The execution command entry copy address is the command entry copy 5 being executed.
81 address.

The command entry copy 581 is information created by fetching a command entry.
An area in which necessary information from the command entry 504 is copied, an address of the execution command processing table 582, and pointer information of the next command entry copy.

The execution command processing table 582 is a processing table in which information necessary for command transfer processing is recorded. The execution command processing table 582 indicates an execution command address indicating the position of the command being executed, the number of remaining commands, a read command issued flag, and the like. Consists of

Hereinafter, the processing logic of the IOA 128 will be described in accordance with the processing sequence described with reference to FIGS.

FIG. 21 is a flowchart showing the processing logic of the command entry fetch processing.
As described with reference to FIG. 14 and FIG.
(And the driver 345 of the communication management 340) are shown in FIG.
The command 505 shown in FIG. 18 is created and set in the command entry 504 shown in FIG. 18. Finally, the interface information having the structure shown in FIG. 16 is created in the MU 124 to access the IO command register 501. Causes an interrupt.

By the interruption from the CPU 123,
In the IOA 128, the command entry fetching process of FIG. 21 starts. In this processing, M in the IOA 128
The PU 402 starts processing from the command entry 504 indicated by the value of the command entry address 502.

First, the information of the command entry 504 set in the MU 124 by the CPU 123 is copied to the command entry copy area in the LM 403 (step 5701). Next, the command entry copy 58 just created is added to the command entry copy management table 580.
1 (FIG. 22) is registered (step 5703).

In these processes, a new command entry copy 581 is added to the end of a chain of a series of command entry copies 581. That is, first, a new command entry copy 581 is created in the command entry copy area in the LM 403, and the information of the command entry 504 is copied there. Then, the address of the newly created command entry copy 581 is set as the value of the next command entry copy field of the last command entry copy 581 of the chain of the command entry copy 581. Further, the address of the last command entry copy in the command entry copy management table 580 is updated, and the number of command entry copies is updated.

Of course, at the time of the first registration, the address of the first command entry copy and the address of the execution command entry copy are also set (step 5703). The initial value of the address of the execution command entry copy is the address of the head command entry copy 581.

Next, the setting processing of the execution command processing table 582 is executed (step 5707). Specifically, an execution command processing table 582 is newly created,
Command entry copy 5 created in step 5701
The address of the execution command processing table 582 is set in the column of the execution command processing table 81. In the execution command address column of the execution command processing table 582, the command string start address (FIG. 18) of the command entry copy 581 is set. Furthermore, the command string chained from the command string head address is checked, and the number of command chains constituting the command string is recorded in the remaining command number column of the execution command processing table 582.

Next, a next command entry determination process is performed (step 5707). That is, after clearing the busy flag of the command entry 504, the address of the next command entry 504 is calculated, and the
Check the sy flag. If the flag is set, the command entry 504 has not yet been taken into the IOA, and therefore, the processing is repeated from step 5701.
Continue capturing command entries. Step 570
If the busy flag is not set in step 7, this interrupt processing ends (step 5707).

The main logic of the command processing in the IOA 128 will be described with reference to FIGS. FIG.
9 is the processing of the transmission system described in FIG. 14, and FIG. 20 is the processing of the reception system described in FIG.

First, the processing of the transmission system will be described with reference to FIG. The storage address of the command to be executed (the execution command address of the execution command processing table 582) is obtained by following the chain from the execution command entry copy address of the command entry copy management table 580. Whether this value is null or read
It is checked whether the issued flag is set (step 5501).

If the value is null or the flag is set, the command entry copy management table 580 is used to obtain an execution command for a different device.
Is updated (updated so as to point to the next command entry copy 581) (step 5527), and the process returns to step 5501.

If it is not the above in step 5501, the process of obtaining the address of the target MCI to be executed by the command from the device ID of the command entry copy 581 pointed to by the execution command entry copy address of the command entry copy management table 580 is executed. Perform (step 5503). Next, a bus connection request is issued to the SCSI protocol processor 404 by designating the address obtained in step 5503 to open the bus with the target MCI (step 550).
5).

Next, the command is checked. Here, the subsequent processing is distributed depending on whether the command is a send command or a read command (step 5507).
The processing of the read system will be described later.
The d-system processing will be described.

The MPU 402 requests the SCSI protocol processor 404 to send a send command to the target MCI. As a result, the send command is transmitted from the target MCI via the previously opened bus.
(Step 5509). Next, in order to transfer the transmission data from the MU 124 to the memory on the target MCI, the processor 404 is instructed with an execution command and issues a DMA transfer start request. Processor 404
Refers to the execution command and transfers the transmission data (connected by the data chain) by the DMA method (step 5).
511).

Next, the MPU 402 checks the execution command c
The rep bit is checked (step 5513). If this bit is on, the completion information is written in the completion information area in the command 505 based on the completion report from the target MCI (step 5515). If the crep bit is off, or after step 5515, in
The t bit is checked (step 5517).

If the int bit is ON, the interrupt signal line is operated to generate a termination interrupt for the CPU 123 (step 5519). If the int bit is off or after step 5517, the eoc bit is checked (step 5521).

If the eoc bit is on, release processing of the command entry copy 581 is performed (step 55).
25). That is, the number of command entry copies is reduced by one from the table 580, and the address of the executed command entry copy is updated (the next command entry copy 581).
After that, the command entry copy 581 is deleted. If the eoc bit is off, the execution command address of the execution command processing table 582 is updated (updated so as to point to the next command) (step 5523).

After step 5525, step 550 is executed.
Repeat from 1. After step 5523, step 5
Repeat from 507.

The read-based processing will be described with reference to FIG. When the command to be executed in the above processing step 5507 is a read command, the MPU 402
Read M command to processor 404
Make a request to send to CI. As a result, the read command is transferred via the previously opened bus (step 5601).

Next, the response from the target MCI is checked to check whether there is no received data in the target MCI, that is, whether or not to release the bus (step 5601). If there is no received data, the bus is released, and a bus release request is made to the processor 404 (step 5605). Then, the Read issued flag of the execution command processing table 582 is turned on (step 5697). Then, step 55
27 to process commands for different devices.

If the bus is not released in step 5603,
That is, if there is received data, a DMA transfer start request is issued to transfer the received data from the target MCI to the MU 124 (step 5609). afterwards,
The processing is executed from step 5513.

Next, with reference to the flowchart in the lower part of FIG. 20, a description will be given of the processing when the received data is generated after the bus is released in step 5605. This processing is re
IOA128 from MCI that has issued ad-related command
Triggered by an interrupt generated by reconnecting the bus with

First, the target MCI is recognized by identifying the device ID of the MCI that caused the interrupt.
The received message is accepted by specifying the issued command by searching the command entry copy 581 and the execution command processing table 582 (step 5611). Next, the Read issued flag of the table 582 is turned off (step 5613). Then, by issuing a DMA transfer request, the received data is transferred from the target MCI to the MU 124 (step 5).
615).

Thereafter, command bit processing is executed (steps 5617 to 5625), similarly to the processing from step 5513 to step 5521 in FIG. Here, if it is on in the eoc bit determination processing in step 5621, the command entry copy is released (step 5627).

The main processing of the IOA 128 has been described above.

(Example 3) In Examples 1 and 2,
The driver reads after receiving a reception request from the AP.
The command has been issued to the CH 142 and the IOA 128.
On the other hand, in the third embodiment, a read command is issued to the IOA 128 (or CH) in advance before receiving a reception request from the AP. A processing module that performs this processing is called a read advance processing. Here, the second embodiment (mainly the driver 345) described above
An example in which the function of the ad advance processing is added will be described.
It can be applied to the first embodiment.

FIG. 23 is a configuration diagram of the advance read command management table 400 referred to by the read advance processing. FIG. 24 is a flowchart illustrating the processing logic of the read advance processing.

With reference to FIG. 23, the advanced read command management table 400 will be described in detail. The table 400 holds the total number of devices and the maximum number of read issues. The total number of devices is the total number of devices that can be input / output by this driver. The maximum number of read commands is the maximum number of read commands when a read command is first issued to each device. In other words, this is the upper limit of the number of commands when a plurality of read commands are grouped in a command chain and issued in advance on each device.

The table 400 has a plurality of pairs of device IDs (for the total number of devices) and the number of issued reads. The device ID is identifier information for identifying each device. The number of issued reads is
R issued in the device corresponding to each device ID
This is the number of commands for which the command operation has not been completed in the "head" command. The number of issued reads has been cleared to zero at the time of initialization.

Next, the processing logic will be described with reference to FIG. First, first (first after driver initialization)
Is executed from step 4109. Here, the total number of devices in the table 400 is substituted into the variable y, and a pointer variable indicating the initial device ID (initially, the device ID in FIG. 23 indicates 0x00) is set (step 410).
9). Next, the subsequent processing is sorted according to the value of the variable y. y
If> 0, the process proceeds to step 4117; otherwise, the process proceeds to step 4113 (step 4111).

The description will begin with the case where y> 0. Table 4
00, the value of the number of issued reads corresponding to the device ID indicated by the pointer variable is obtained, and the maximum read
The value of the issued read number is subtracted from the issued number, and the result is substituted into a variable z (step 4117). Next, the value of the corresponding issued read number in the table 400 is updated to the maximum read issued number (step 4115).

Next, a command chain consisting of z read commands is created (step 4119). Then, the command chain is registered in the command entry 504 (step 4121). Next, the value of the variable y is decremented by one, and the pointer variable is updated (to point to the next device ID) (step 4123).
Return to 11. Thus, steps 4111 to 4123
Is executed for all the devices, and a first read is issued to each device for the maximum number of issued reads.

If y> 0 is not satisfied in step 4111, I
Activate the OA 128 and start input / output (step 411)
3). Thus, a series of processes from the time of initialization is completed.

Next, a case will be described in which the present process is started from the extension of the end interrupt of the read command.

The corresponding device ID is specified from the information of the end interrupt, and the number of issued reads of the corresponding device ID is obtained from the table 400 (step 410).
1). Since one input / output process for the device has now been completed, the number of issued reads −1 is substituted for the variable x (step 4103), and the value of x is set to the number of issued reads in the table 400. Update is performed (step 4107).

Next, it is determined whether the expression x = <0 (step 4).
105). If the judgment value is true, the current issued read
Since the value of the number is 0 or less,
The process is executed from step 4109 to issue an ad.
If not, the process from the interrupt ends. According to this processing, when the advance read in a certain device is lost, the read for a plurality of devices is triggered.
ad commands can be issued together.

(Embodiment 4) In Embodiments 1 to 3 described above,
Although the processing of the driver 345 (FIG. 6) has been described, the relation between the protocol processing 343 and the input / output command has not been described. In the fourth embodiment, in consideration of these relations, when data is divided into a plurality of packets by the protocol processing and transmitted, a series of write commands for transferring the number of packets that can be transmitted at one time is used. An example in which a command string is created and issued will be described.

Here, an example in which the above functions are added to the second embodiment (especially, an interface between the protocol processing 343 and the driver 345 in FIG. 6 to which the processing described later is added) will be described. The same applies to the examples.

First, the communication protocol processing 343 will be described. In the communication protocol, a fixed-length data unit called a packet is used as a unit for transmission and reception. The packet is
The original data is obtained by adding protocol control information called a header to the head of the original data. Therefore, the protocol processing 343
Then, when the original data (data from the AP 34) is larger than the above packet size, it must be divided and a plurality of packets must be created. This processing is called packet division processing.

Referring to FIG. 25, a description will be given of a method of packet division processing in this embodiment. In the figure, the upper side of the horizontal line indicates the original data before division and the data management information block (hereinafter referred to as SPB) SPB0 of the data, and the lower side indicates the data after the packet division processing and its SPB.

First, before the packet division processing, the original data D0 is stored in the buffer Bf0 and one SPB
0 manages the original data D0 by holding the address of the original data and its data length. The SPB has a field indicating the next SPB address and the like. Original data is 1
If the data cannot be stored in one buffer, the original data is managed by a plurality of SPBs. At this time, the next SP is
B addresses (this is called an SPB data chain).

In FIG. 25, since the original data D0 is stored in one buffer, the value of the next SPB address of SPB0 is null. The value null is a value indicating the end of the chain. Therefore, null here indicates the end of the SPB data chain.

Referring to FIG. 25, a description will be given of a method of packet division processing for creating two packets from original data D0. The packet division processing is executed in the protocol processing 343.

First, in the packet division processing, the original data D0
The data length of the data is checked to determine whether or not the data is to be divided, and if the data is to be divided, the data dividing position is determined. Here, the original data D0
Is divided into data D1 and D2.

To create the first packet, a buffer BF1 for storing the first header is reserved, and the header is created. In order to create an SPB for managing the first packet, the address of the first header and its data length are recorded, and the SPB1 in which the address of the subsequent SPB0 is recorded is created. Then, the data length of SPB0 is changed from the length of data D0 to the length of data D1.

Next, in order to create a second packet, a buffer Bf2 for storing the second header is secured and a header is created. In order to create an SPB for managing the second packet, an SPB2 for managing the header and an SPB3 for managing the divided data are created. SPB2
Is the same as SPB1. SPB3 is created by recording the address of data D2 and its data length. As described above, in the present embodiment, a packet division method that does not perform data movement processing is employed.

Next, the relationship between packet division processing and command creation processing (processing for creating data as shown in FIG. 16 by the driver 345) will be described.

The window control will be described as the control of the protocol of the network layer. The window control is a control method in which a plurality (predetermined number) of data packets are continuously transmitted without confirming the delivery of each data packet, and the delivery is confirmed collectively. The transmitting side determines the window size from the reception sequence number (Pr) returned from the other party to WS.
Then, a data packet having a transmission sequence number (Ps) up to WS + Pr-1 can be transmitted without acknowledgment. That is, the window size (Ws) indicates the maximum number of data packets that can be continuously transmitted without confirmation of delivery from the other party.

Here, assuming that the transmission sequence number of the newest transmitted packet is PS, the number of continuous transfers is defined as WS + Pr-1-PS. The number of continuous transfers indicates the number of data packets that can be continuously transmitted at present without confirming delivery from the other party. In the present embodiment, a method is adopted in which an input / output command in which packets within the number of continuous transfers are combined is created, and these are collectively transferred to the line controller. According to this method, input / output efficiency is improved as compared with a method in which individual packets are transferred one by one.

This process is called packet division batch io process. Moving to the description of this processing. First, the number of continuous transfers is recorded as protocol control information. When the number of continuous transfers is not 0 and there is a staying packet, the processing is shifted from the packet division processing to the packet division batch io processing. The staying packet is a fragmented packet created by the packet dividing process. When shifting from the packet division processing to the packet division batch io processing, the total number of divided packets created in the packet division processing is delivered as the number of staying packets, and the address of each packet is also delivered.

FIG. 27 is a flowchart showing the packet division batch io processing logic. FIG. 26 is a diagram showing the data structure created by the packet division batch io process and the data structure of the interface to the driver. In particular, FIG. 26 shows the result of processing the lower data structure (divided by the packet division process) of FIG. 25 by the packet division batch io process.

First, in the packet division batch io process, the number of continuous transfers (that is, the number of packets that can be continuously transmitted without a delivery confirmation for each packet at the present time) and the number of staying packets (the divided packets divided by the packet division process). Is compared with the number (step 531). If the number of staying packets is equal to or greater than the number of continuous transfers, connect the packets of the number of continuous transfers from the beginning of the staying packets by a command chain,
The remaining packets are retained (step 53).
5). Conversely, if the number of staying packets is smaller than the number of continuous transfers, all the staying packets are connected by a command chain (step 533).

After steps 533 and 535, a transmission request is made to the driver (step 537). Next, the number of continuous transfers is updated (step 539). Specifically, the number of packets connected in steps 533 and 535 is subtracted from the value of the number of continuous transfers to obtain a new number of continuous transfers.

The processing of linking packets by a command chain (steps 533, 535) will be supplementarily described by taking the lower part of FIG. 25 and FIG. 26 as examples. In order to obtain the data structure shown in FIG. 26 from the data structure shown in the lower part of FIG. 25, first, each SPB is provided with a command chain pointer field (the initial value is null). Next, following the SPB chain following SPB1, which is the first packet, the last S
The process of setting the address of SPB2, which is the second packet, to the command chain pointer of PB (SPB0 in this example) is performed. If there are more packets to be connected, the same procedure may be repeated.

FIG. 28 is a flowchart showing the processing logic of the driver 345 for creating a command chain from the data structure as shown in FIG. 26 created by the packet division batch io processing.

First, the driver 345 checks the SPB (head S
The command 505 (FIGS. 16 and 17) is created based on the PB (processing is started) (step 54).
1). Next, the next SPB address of the SPB is null.
1 is determined (step 543). The SPB
If the next SPB address is not null, there is data to follow, so the next command 505 is secured, the chain field of the command 505 is set, and the data chain bit (dc bit) is set (step 545). Then, the processing from the command creation (step 541) is repeated again.

If the decision result in the step 543 is null,
If it is 1, it is determined whether or not the value of the command chain pointer of the SPB is null (step 547). As a result, if it is not null, the next command 505 is secured, the chain field of the command 505 is set, the data chain bit (dc bit) is cleared,
Set an interrupt bit (int bit) (step 5
49). Then, create an io command again (step 5).
Repeat from 41). If null, the end bit (eoc) of the command is set and the process ends. By this processing, a command string connected by a chain for transmitting a plurality of packets in one io operation is created.

(Embodiment 5) Embodiment 5 is a modification of the above-described Embodiment 4 for improving the performance. A feature of the fifth embodiment resides in a refilling process. With reference to FIG. 29, the refilling processing method will be described.

In FIG. 29, packet division processing 603
Is the packet division process described in the fourth embodiment. The transmission data structure in the case where there is no packet division in the packet division processing 603 is shown in the upper part of FIG. If there is no packet division, SPB1 which is the SPB for the header
And a transmission data structure composed of two parts, SPB0, which is a data SPB.

For this reason, by sending this transmission data as it is to the driver 345 to create a command string,
Since the driver 345 always creates one command for one SPB, a command string including two commands is created. This command string is referred to as IOA1
Execution of 28 will process two commands. These two commands are linked by a command chain. However, the overhead of buffer switching in the DMA processing is large, so that the data transfer processing time is long and the performance is reduced. A process for completing the above process with one command in order to improve the performance is a refill process 601.

The middle part of FIG. 29 shows a packet represented by one SPB created by the refilling process 601. FIG. 30 is a flowchart illustrating the processing logic of the refilling process 601.

First, the refilling process 601 determines whether or not repacking is necessary by comparing the data length indicated by SPB0 with the data length determination information 600 (step 61).
1).

Here, the value of the data length determination information 600 will be described. Now, the overhead of the IOA processing one command is defined as O (c). Assuming that the data length (bytes) is D1 and the overhead required to move one byte of data is O (m1), the overhead of moving the data of length D1 (O (md)) is O (m1). * It can be represented by D1. Assuming that the refill method is effective when O (c) is greater than O (md), the data length D1 in that case is D1 <O
The condition (c) / O (m1) is satisfied. Therefore,
O (c) / O (m1) is calculated, and data length determination information 60 is calculated.
It is set to 0 when the computer is started.

In step 611, the data length indicated by SPB0 is compared with the data length judgment information 600,
If the data length indicated by 0 is smaller than the data length determination information 600, it is determined that refilling is necessary, and if not, it is determined that refilling is unnecessary.

If it is determined in step 611 that refilling is necessary, the data stored in the data buffer Bf0 is moved to an area after the header of the header buffer Bf1 (step 613). Next, the buffer Bf0 that is the data move source is released (step 61).
5). The SPB chain is updated by writing null to the next SPB address of SPB1 (step 61).
7). And SPB0 which is the SPB of the data move source
Is released (step 619), thereby ending a series of processing.

By the above processing, the header and the data are stored in one buffer and managed by one SPB. By passing this to the driver 345, one command 505
Is created.

In the above embodiment, a communication server computer (including a number of input / output devices such as line controllers) for performing data exchange and file processing with a number of terminals and host computer systems and performing part of online processing. An example in which the present invention is applied has been described with reference to FIG. 33), but the present invention is not limited to this and can be generally applied to a computer system. For example, the main CPU is connected to a plurality of slave CPUs (device processors) via an input / output processor (input / output adapter device).
When data is generated asynchronously in the slave CPU and it is necessary to distinguish between data generated in one slave CPU and data generated in another slave CPU in a computer system configuration connected to Connect an asynchronous device,
When each data must be processed separately, the local memory and the main CP managed by the slave CPU
The present invention can also be applied to a case where an input / output command sequence (specific to a slave CPU) for controlling data transfer between main storage devices managed by U is issued from the main CPU to a plurality of slave CPUs.

[0183]

As described above, according to the present invention,
The following effects are obtained. Pending I / O requests to multiple I / O devices,
By executing these operations in a single input / output operation, the number of input / output operations can be reduced. In particular, a CPU connected to a large number of input / output devices (where n is the number)
The control overhead with the input / output adapter is reduced to 1 / n by the present invention. The command issuing efficiency can be improved by adjusting the number of command strings for requesting commands collectively according to the state of the input / output adapter (command reception busy). By issuing input requests (read commands) to a plurality of input / output devices collectively, the overhead of the data input operation can be reduced. By creating a command sequence for collectively transferring a plurality of packets created by the packet division processing and activating the input / output adapter, the input / output overhead can be reduced. By optimizing the input / output operation of short data including the data transfer processing of the input / output adapter device, the input / output efficiency is improved, and the input / output performance is improved.

[Brief description of the drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 is a configuration diagram of input / output devices in the computer according to the first embodiment.

FIG. 3 is a diagram showing interface information according to the first embodiment;

FIG. 4 is a flowchart of a main operation of a channel according to the first embodiment.

FIG. 5 is a flowchart of CCW execution processing of a channel according to the first embodiment.

FIG. 6 is a structural diagram of communication management in the first embodiment.

FIG. 7 is a structural diagram of an input / output request management table in the first embodiment.

FIG. 8 is a flowchart illustrating the operation of a driver that has received a request in the first embodiment.

FIG. 9 is a flowchart illustrating a command issuing operation after accepting an input / output interrupt in the first embodiment.

FIG. 10 is a hardware configuration diagram of a communication server according to a second embodiment.

FIG. 11 is a diagram showing information stored in a storage unit of the communication server.

FIG. 12 is a structural diagram of an IO adapter.

FIG. 13 is a structural diagram of a multi-line control device.

FIG. 14 is an input / output sequence diagram during data transmission.

FIG. 15 is an input / output sequence diagram at the time of data reception.

FIG. 16 is a configuration diagram of interface information according to the second embodiment.

FIG. 17 is a diagram illustrating a command configuration according to the second embodiment;

FIG. 18 is a configuration diagram of a command entry.

FIG. 19 is a flowchart (part 1) illustrating processing of an IO adapter;

FIG. 20 is a flowchart (part 2) showing the processing of the IO adapter.

FIG. 21 is a flowchart (3) showing the processing of the IO adapter;

FIG. 22 is a view showing a processing table of an IO adapter.

FIG. 23 is a configuration diagram of an advance Read command management table;

FIG. 24 is a flowchart showing a Read command issuance process;

FIG. 25 is an explanatory diagram of a packet division processing method.

FIG. 26 is a diagram showing a relation between a plurality of packets created by the collective IO method;

FIG. 27 is a flowchart showing processing of the batch IO method.

FIG. 28 is a flowchart showing the command creation logic of the driver.

FIG. 29 is an explanatory diagram of a refilling processing method.

FIG. 30 is a flowchart showing a refilling process;

FIG. 31 shows a conventional channel interface.

FIG. 32 is a diagram showing a conventional input / output operation for a plurality of devices.

FIG. 33 is a network configuration diagram of an online system using a communication server which is a conventional example and an application example of the present invention.

[Explanation of symbols]

 124 memory unit 128 IO adapter 501 IO command register 502 command entry address 503 command interface 504 command entry 505 command 506 transfer area

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuo Matsunaga 5030 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Software Development Division (56) References JP-A-63-208147 (JP, A) Kaisho 63-259753 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 13/12 G06F 13/10

Claims (20)

(57) [Claims] 1. A computer comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. The system, further comprising: means for issuing a plurality of input / output commands to the plurality of input / output devices as one input / output activation command; Means for specifying a plurality of input / output commands for a plurality of input / output devices included in the start instruction as an input / output command for which input / output device; A computer system, comprising: means for providing input / output devices. 2. A computer comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. A main processing unit, the main processing unit comprising: a waiting request management table for storing and managing an input / output request to the input / output device; Means for storing the input / output request in the waiting request management table when the output request cannot be processed immediately; and storing the input / output request in the waiting request management table at that time when the processing of the input / output request becomes possible. A command sequence, which is a sequence of input / output commands to be given to each of the input / output devices, is created for each input / output device based on the input / output request. When Means for issuing to the adapter device, wherein the adapter device specifies a plurality of command strings included in the one input / output activation command as a command string to which input / output device; Means for giving each input / output command of a plurality of command strings to the specified input / output device. 3. The input / output device further comprises means for issuing a termination interrupt to the main processing device when processing of a given input / output command is completed, wherein the main processing device receives the input / output command from the input / output device. As a trigger of the output command end interrupt, it is determined whether or not the processing of the input / output request is possible.If possible, based on the input / output request stored in the waiting request management table at that time, Means for generating a command sequence, which is a sequence of input / output commands to be given to each input / output device, for each input / output device, and issuing the plurality of command sequences to the adapter device as one input / output activation command The computer system according to claim 2, comprising: 4. A plurality of command strings issued from said main processing unit to said adapter device as said one input / output start command include address information designating a head position of the command string and execution of each command of the command string. 4. The computer according to claim 2, wherein a block including identifier information specifying one target input / output device is used as a basic unit and managed by a table having a structure in which a plurality of blocks are continuous. system. 5. Each block of the table is provided with flag information indicating whether or not the adapter device has fetched a command sequence corresponding to the block, and when the main processing device issues the input / output activation command, 5. The computer system according to claim 4, wherein the flag information is issued as ON, and the flag information is turned OFF when the adapter apparatus receives a command sequence of the input / output activation instruction. 6. An input / output device comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. The main processing unit is a computer system including an application execution unit that executes an application program and a driver unit that processes an input / output request issued from the application execution unit, wherein the driver unit of the main processing unit includes: Means for generating an input / output command based on an input / output request issued from the application execution unit, and issuing a plurality of input / output commands to a plurality of input / output devices as one input / output activation command, The adapter device sends a plurality of input / output commands for a plurality of input / output devices included in the one input / output start command. Means for specifying an input / output command for the input / output device; and means for giving each of the plurality of input / output commands for the plurality of input / output devices to the specified input / output device. Computer system. 7. An electronic apparatus comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. The main processing unit is a computer system including an application execution unit that executes an application program and a driver unit that processes an input / output request issued from the application execution unit, wherein the driver unit of the main processing unit includes: A wait request management table for storing and managing the input / output requests issued from the application execution unit, and when an input / output request from the application execution unit occurs, when the input / output request cannot be processed immediately, Means for storing the input / output request in the waiting request management table, and when the input / output request can be processed, At that time, based on the input / output requests stored in the waiting request management table, a command string, which is a sequence of input / output commands to be given to each of the input / output devices, is created for each input / output device. Is issued to the adapter device as a single input / output activation command. The adapter device outputs a plurality of command sequences included in the single input / output activation command to any one of the input / output A computer system comprising: means for specifying a command sequence for a device; and means for giving each of the input / output commands of the plurality of command sequences to the specified input / output device. 8. The driver unit of the main processing unit, before receiving a data input request from the application execution unit, converts a plurality of input commands to the plurality of input / output devices into a single input / output activation command and outputs the input / output activation command to the adapter unit. The computer system according to claim 6, further comprising a means for preloading the device. 9. An input command advance means, comprising: first storage means for storing a first specified number indicating a maximum number of input commands issued to the input / output device; and an input command sequence for reissuing the input command sequence. A second storage unit for storing a second specified number for defining the timing of the operation; and a third storage unit for storing the number of uncompleted input commands for each of the input / output devices. After the initialization, an input command sequence in which the input commands are connected for the first prescribed number is created for each input / output device, issued to the adapter device, and issued to the third storage means to each input / output device. The number of input commands is recorded, and thereafter, each time an input command completion report is received from each of the input / output devices, the number of incomplete input commands of the corresponding input / output device stored in the third storage means is reduced by one, By this processing When the number of uncompleted input commands in the input / output device reaches the second prescribed number, the number of uncompleted input commands stored in the third storage means and the first number of uncompleted input commands stored in the first storage means are set. 9. The computer system according to claim 8, wherein a difference from a prescribed number is calculated, and an input command sequence in which input commands are linked by the difference is reissued to the adapter device. 10. The input / output device is a line control device, and the main processing device divides data relating to a data transfer request issued from the application execution unit, and sets a head of each of the divided output data. A protocol processing unit that adds communication protocol control information to the packet to generate a plurality of fragmented packets, wherein the driver unit of the main processing unit is configured to continuously transmit the number of the plurality of fragmented packets without confirming delivery from the other party at that time. When the number of packets that can be transferred is equal to or less than the continuous transfer number, a plurality of input / output commands are created based on the plurality of divided packets, and the created plurality of input / output commands are issued as one input / output start instruction. 8. The method according to claim 6, wherein the output data of the plurality of divided packets is transferred by one input / output operation. The placing of the computer system. 11. The input / output device is a line control device, wherein the main processing device divides data relating to a data transfer request issued from the application execution unit, and points to the divided output data. Each of the management information blocks is created, and communication protocol control information to be logically added to the beginning of the divided output data, wherein the communication protocol control information and the output data logically constitute a divided packet. A protocol processing unit that creates such communication protocol control information and creates a data management information block that points to the communication protocol control information, and the data processing information block that is pointed to by another data management information block output from the protocol processing unit. For the communication protocol control information and the output data, the adapter device By comparing the overhead of copying the overhead and the output data required to process the command to transfer the Col control information region continuous to the communication protocol control information,
When the latter overhead is smaller, the communication protocol control information and the output data are set in a continuous area, a data management information block that points to the area is created, and a refill processing unit to be passed to the driver unit. The computer system according to claim 6, further comprising: 12. A computer comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. A method of issuing an input / output command in a system, comprising: a plurality of input / output commands for the plurality of input / output devices from the main processing device, as one input / output activation command;
Issuing the input / output command, and specifying which input / output device is the input / output command for the input / output devices for the input / output devices included in the one input / output activation command; Providing each of the plurality of input / output commands for the plurality of input / output devices to the specified input / output device. 13. A computer comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. A method of issuing an input / output instruction in a system, wherein, when an input / output request to the input / output device is generated in the main processing unit, the input / output request cannot be processed immediately, a request for waiting for the input / output request is issued. Storing and managing the input / output request in the management table; and when the processing of the input / output request becomes possible, based on the input / output request stored in the waiting request management table at that time, A command sequence, which is a sequence of input / output commands to be given, is created for each input / output device, and these command sequences are issued to the adapter device as one input / output activation command. A step of identifying a plurality of command strings included in the one input / output activation command as a command string to which input / output device, and the input / output command of each of the plurality of command strings. Providing an input / output command to the specified input / output device. 14. When the input / output device has completed processing of a given input / output command, issuing a termination interrupt to the main processing device; As a trigger of the output command end interrupt, it is determined whether or not the processing of the input / output request is possible.If possible, based on the input / output request stored in the waiting request management table at that time, Creating a command sequence, which is a sequence of input / output commands to be given to each input / output device, for each input / output device, and issuing the command sequences to the adapter device as one input / output activation command 14. The method for issuing an input / output instruction according to claim 13, further comprising: 15. An input / output device comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. The main processing device is a method for issuing an input / output command in a computer system including an application execution unit that executes an application program and a driver unit that processes an input / output request issued from the application execution unit. Issuing a plurality of input / output commands to the plurality of input / output devices from the driver unit of the processing device as a single input / output activation command; and including the input / output activation command by the adapter device in the single input / output activation command Identifying a plurality of input / output commands for a plurality of input / output devices to be input / output commands for the input / output devices , Issuing method of input and output commands, characterized in that a step of providing each for a plurality of input and output devices respectively are the specific input command to the plurality of input and output devices. 16. An input / output device comprising: a plurality of input / output devices; an adapter device coupled to the plurality of input / output devices; and a main processing device for giving an input / output request to the input / output device via the adapter device. The main processing device is a method for issuing an input / output command in a computer system including an application execution unit that executes an application program and a driver unit that processes an input / output request issued from the application execution unit. In the driver unit of the processing device, when an input / output request from the application execution unit occurs, if the input / output request cannot be processed immediately, storing and managing the input / output request in a waiting request management table; When I / O requests can be processed, the I / O requests stored in the waiting request management table at that time On the basis of the request, a command sequence that is a sequence of input / output commands to be given to each of the input / output devices is created for each input / output device. Issuing to the adapter device, in the adapter device, identifying a plurality of command sequences included in the one input / output activation command as a command sequence to which input / output device, and each of the plurality of command sequences Applying the input / output command to each of the specified input / output devices. 17. The driver of the main processing unit,
16. The method according to claim 15, further comprising, before receiving a data input request from the application execution unit, sending a plurality of input commands to the plurality of input / output devices to the adapter device as one input / output activation command. 16. The method for issuing an input / output instruction according to any one of items 16. 18. The method according to claim 18, wherein, after initializing the driver unit, an input command sequence in which the input commands are connected for a predetermined maximum issuance number is created for each input / output device, and the adapter device is initialized. Issuing the command, recording the number of input commands issued to each input / output device, and each time a completion report of the input command is received from each of the input / output devices, the stored incomplete input command of the corresponding input / output device is stored. If the number of uncompleted input commands in the input / output device is reduced to a predetermined number or less by this processing, the difference between the stored number of uncompleted input commands and the maximum number of issued commands is calculated. 18. The method for issuing an input / output instruction according to claim 17, further comprising: re-issuing an input command sequence in which input commands are connected by the number of differences to the adapter device. 19. The main processing unit divides data relating to a data transfer request issued from the application execution unit, and adds a plurality of pieces of communication protocol control information to the head of each of the divided output data to add a plurality of pieces of communication protocol control information. Performing a protocol process for generating a fragmented packet; and in the driver unit of the main processing device, the number of continuous transfers in which the number of the plurality of fragmented packets is the number of packets that can be continuously transferred at that time without confirmation of delivery from the other party. In the following cases, a plurality of input / output commands are created based on the plurality of fragmented packets, and the created plurality of input / output commands are issued as one input / output activation command, thereby Transferring the output data by one input / output operation.
6. The method for issuing an input / output instruction according to any one of 6. 20. In the main processing unit, data relating to a data transfer request issued from the application execution unit is divided, and data management information blocks each pointing to the divided output data are created. Communication protocol control information that is to be logically added to the beginning of the output data, and that forms a logically divided packet with the communication protocol control information and the output data. A protocol processing step for creating data management information blocks each pointing to communication protocol control information; and for the communication protocol control information and the output data pointed to by another data management information block output from the protocol processing step, Adapter device transfers the communication protocol control information By comparing the overhead required to process the command to be performed with the overhead required to copy the output data to an area continuous with the communication protocol control information, if the latter is smaller, the communication protocol control 17. The refilling step according to claim 15, further comprising the steps of: setting information and the output data in a continuous area; creating a data management information block pointing to the area; and passing the data management information block to the driver unit. The issuance method of the input / output instruction described in (1).