JP2900674B2 - IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester, and more particularly to an IC tester capable of correcting the timing of an output signal .

[0002]

2. Description of the Related Art A conventional IC tester tests an electrical characteristic of an IC under test by applying a power supply voltage or a signal to the IC under test and comparing an output signal from the IC under test with an expected value. It is. FIG. 5 is a diagram schematically showing a system for generating a signal to be applied to an IC under test. FIG. 5 is an example of an IC tester having a configuration having n timing generators and m tester pins. In the figure, reference numeral 10 is a control unit, reference numeral 30 is a basic timing generation unit, reference numerals 401 to 40n are timing generation units, reference numerals 601 to 60n are switching units, reference numerals 701 to 70n are format units, reference numerals 801 to 80n are deskew units, and reference numerals are reference numerals. 90 is a bus. Tester pins (not shown) correspond to the format sections 701 to 70n and the deskew sections 801 to 80n in a pair. The function of the switching units 601 to 60n in the figure is to output one timing generation unit input to any of the format units 701 to 70n, and the bus 90 includes these timing generation units and the format units 701 to 70n. Refers to the signal system between them.

The basic timing generator 30 sends a clock signal as a basic timing to each of the timing generators (TG) 401 to 40n. The control unit 10 sends clock timing data to be generated by each of the timing generation units 401 to 40n to each of the timing generation units 401 to 40n according to the test information.
-60n, and sends a connection control signal between each of the timing generation units 401 to 40n and each of the format units 701 to 70n. The timing generators 401 to 40n include the switching unit 6
A predetermined clock is transmitted to the format units 701 to 70n via 01 to 60n. Formatting parts 701-7
0n generates a signal waveform to be applied to the IC under test based on the clock timing of the timing generators 401 to 40n.

FIG. 6 shows an outline of the timing of these signals. The format section signal rises at the same timing as the edge A, which is the rise of the TG output clock in the figure, and a signal to the IC under test is generated with a delay of time t. . This delay time is determined by the deskew unit 80
It is created by 1-80n data . The signal timing to each tester pin is determined by each of the timing generators 401 to 40
n, switching units 601 to 60n and format units 701 to 701
By the electrical characteristic variations of 70n, it is not the same and the like. Therefore, the respective deskew units 801 to 80n change the circuit constants in the respective deskew units 801 to 80n,
It is used to match the timing of the signal at each terminal end of the IC under test identically for each tester pin. Matching the timing of each tester pin is called timing correction. FIG. 7 shows the timing generators 401 to 40.
4 shows signals to the IC under test before timing correction by the combination of n and each tester pin.

[0005] In order to correct variations of this such timing, prior to testing under test IC, taken timing data by all combinations of the timing generator 401~40n each tester pin of FIG. 7, this The skew data as shown in FIG. 8 is stored in the memory in the control unit 10 based on the data. FIG. 9 shows an example of a test flow in the case where the combination of each tester pin and the timing generator is different for each tester. FIGS. 10 to 12 show the skew conditions in FIG. 9, and the hatched portions indicate combinations of the timing generators 401 to 40n and tester pins selected in those tests. In this example, a test is performed while setting a skew condition that matches each test.

[0006]

In the above-described conventional IC tester, timing data is collected by all combinations of TG and tester pins, and it takes a long time to create skew data of all combinations based on these data. In addition, the skew data necessary for each test is read from the control unit at any time and set in the deskew unit, which results in an increase in test time. For example, the time to create skew data for all combinations of TG and tester pins is as follows: when the number of TGs is 20, the number of clocks per phase is 2, and the number of tester pins is 512 pins, 100 ms per 1 × 1 pin clock. , About 34 minutes (= 100 ms × 20 phases × 2 clocks × 512 pins). In addition, the time required to set the skew data required for each test in each deskew unit is proportional to the number of tester pins and the number of tests, and the skew data setting time becomes longer as the number of pin testers increases.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the prior art, and to collect and correct timing skew data of an IC tester in a short time.

[0008]

According to the present invention, a preset
N timing generators for sending out the clock signal
Based on the clock output from the timing generator.
M signal generators that generate signal waveforms to be applied to the IC under test
And a format part. Also, each timing generation
Clock output from the section to any format section.
N switching units that can be connected, and each switching unit and each timing generator
Provided between the live part and caused by each timing generator
N timing generation disks for correcting the first skew
Queue part. In addition, the format from each switching unit
To each tester pin connected to the IC under test via the
Skew caused by variation in electrical characteristics of
M deskew sections and each of the tester pins
With first skew data between timing generators
I have. In addition, any given timing generator
Skew from each switching unit to each tester pin
And a first unit stored in the correction unit.
Skew data and second skew data
Set each timing generation deskew section and each deskew section.
And a control unit for setting the value . This aims to achieve the above-mentioned object.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The embodiment shown in FIGS. 1 to 3 comprises a correction unit 2 for storing or transmitting timing correction data between a plurality of timing generators 41 to 4n and timing correction data between tester pins,
There are provided timing generation deskew units 51-5n for correcting the timing between the timing generation units 41-4n based on the timing correction data sent from the unit, and deskew units 81-8n for correcting the timing between the tester pins.

More specifically, in FIG. 1, reference numeral 1 denotes a control unit, reference numeral 2 denotes a correction unit, reference numeral 3 denotes a basic timing generation unit, reference numerals 41 to 4n denote timing generation units, and reference numeral 5 denotes a timing generation unit.
1 to 5n are timing generation deskew units (TG deskew units ).
) , Reference numerals 61 to 6n indicate a switching unit, reference numerals 71 to 7n indicate a format unit, reference numerals 81 to 8n indicate a deskew unit, and reference numeral 9
Is a bus. 2 and 3 show timing skew data according to the present invention. FIG. 2 shows skew data between each tester pin in the TG 41, and FIG. 3 shows skew data between each TG in the tester pin 1 pin. FIG. 4 shows the skew data of FIGS. 2 and 3 stored in the correction unit 2. Prior to the test execution, skews between tester pins are created for the number of tester pins based on the tester pin variance data as shown in FIG. 2 as shown in FIG. A skew between TGs is created for the number of TGs based on the data, and stored in the correction unit 2. Immediately after the execution of the test, the correction unit 2 controls each TG under the control unit 1.
The skew data is sent to each of the TG deskew sections 51 to 5n, and is set to be sent to the deskew section between the tester pins. Thus, pre-skew data collected creation time, according to the present real施例about reduced by a factor of (TG number) fraction, and skew data to be set deskew portion of each test is not required. Furthermore, each TG skew data is stored in each format unit, and the format unit can correct the signal timing with the skew data corresponding to the TG assigned for each test and send it to the deskew unit. Becomes Other configurations and operations are the same as those of the above-described conventional example.

As described above, in the present embodiment, the timing variation with respect to the timing correction by all combinations of the TG tester pins of the conventional IC tester is as follows.
Focusing on the fact that it can be separated into the variation due to the path from the format section to the tester pin and the variation due to the selected timing generator, the timing data between the tester pins in one arbitrary TG and the one arbitrary By performing the timing of the combination of all the TGs and the tester pins based on the timing data between the TGs at the tester pins, there is an advantage that the time for collecting the skew data and the time for setting the skew data to the deskew section can be reduced. is there.

[0012]

As described above, according to the present invention, a TG deskew section for correcting skew between TGs, a TG deskew section for correcting the skew, and a correction section for sending and setting skew data to the deskew section of each tester pin are provided. Based on the timing data between tester pins in one arbitrary TG and the timing data between each TG in one arbitrary tester pin, the timing of all TG and tester pin combinations is corrected. Therefore, an unprecedented excellent IC that can reduce the time required to collect skew data and the time required to set the deskew data in the deskew section.
A tester can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing timing between tester pins according to FIG. 1;

FIG. 3 is an explanatory diagram showing a variation in timing between TGs.

FIG. 4 is an explanatory diagram showing skew data for correcting timing variations in FIGS. 2 and 3;

FIG. 5 is a block diagram showing an outline of a timing generation system of a conventional IC tester.

FIG. 6 is an explanatory diagram showing signal waveform timing from a TG to an IC under test.

FIG. 7 is an explanatory diagram showing a variation in timing due to a combination of a tester pin and a TG.

FIG. 8 is an explanatory diagram showing skew data for correcting timing variations in FIG. 7;

FIG. 9 is an explanatory diagram showing a test flow for setting skew data for each test.

10 to 12 are explanatory diagrams showing skew data for each test of FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control part 2 Correction part 3 Basic timing generation part 41-4n Timing generation part 51-5n TG deskew part 61-6n Switching part 71-7n Format part 81-8n Deskew part 9 Bus

Claims (1)

(57) [Claims] 1. A predetermined clock signal is transmitted.
Based on n timing generators and clocks output from the timing generators
M channels for generating a signal waveform to be applied to the IC under test
The mat section and the clock output from each of the timing generation sections are optional.
And n switching units connectable to the format unit, and provided between the switching units and the timing generation units.
And a first skew caused by each of the timing generators.
The timing test deskew unit for correcting the error, and the test unit from each of the switching units via the format unit.
Of electrical characteristics up to each tester pin connected to the test IC
M deskews to correct the second skew caused by
And each of the timing generators in any of the tester pins
The first skew data between the
In the raw section, the first section from each switching section to each tester pin
A skew data stored in the correction unit and the first skew data stored in the correction unit and the second skew data.
And the skew data of
It has a skew section and a control section that is set for each deskew section.
An IC tester characterized by: