JP2897796B2 - Auto gain controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auto gain controller, and more particularly to an auto gain controller for detecting a peak value of a data signal output from an amplifier and changing the amplification factor of the amplifier.

[0002]

2. Description of the Related Art In a data communication apparatus, communication data is attenuated in a communication path, but the attenuation rate is not uniform depending on the distance between communication devices and the type of signal cable. Therefore, some communication devices have an automatic gain controller (AGC) to compensate for the amount of attenuation. The auto gain controller detects a peak voltage of the data signal attenuated in the communication path within a certain period, changes the amplification factor of the amplifier by comparing the peak value with the reference value, and always amplifies the signal to a level at which data can be identified. Is a circuit for controlling the amplifier. The gain controlled by the auto gain controller depends on the peak voltage of the data signal,
The change in the amplification factor is digital. The amplification factor decreases in a certain step, such as decreasing the one-step amplification factor when the peak voltage exceeds a certain value, and increasing the amplification factor one step when the peak voltage falls below a certain value. Changes to

FIG. 3 is a block diagram of a conventional auto gain controller of this kind. In the figure, reference numeral 1 denotes an amplifier that amplifies an input signal and transmits the amplified signal to a data discriminating circuit. This is a sample and hold circuit that holds the detection value of the value detection circuit 2.

Reference numeral 4 denotes a frame generation circuit for resetting the peak value detection circuit 2 and generating a frame signal for defining the sampling timing of the sample / hold circuit 3, and reference numeral 5 denotes a peak value held by the sample / hold circuit 3. The comparator 9a compares the reference value with the reference value, and counts the output value of the comparator 5 at the timing of the frame signal.
An AGC control counter for giving a down instruction.

Next, the operation of the conventional example will be described with reference to the timing chart of FIG. The frame generation circuit 4 outputs a frame signal at regular intervals, as shown in FIG. Here, one frame is defined between the frame signals. The received data signal is
The signal is input to the amplifier 1, amplified at the current amplification factor of the amplifier 1, and output to the data identification circuit. The amplified data signal is also input to the peak value detection circuit 2 and used for detecting the peak value of the data signal [(b) of FIG. 4].

The sample and hold circuit 3 to which the output signal of the peak value detection circuit 2 is input holds the peak value of the data signal for one frame [FIG. 4 (c)]. During this hold operation, the peak value detection circuit 2 is reset by the frame signal and searches for the peak value of the next frame. The held peak voltage is compared with a reference voltage by the comparator 5.

The result of this comparison [FIG. 4 (d)] indicates that the peak voltage> the reference voltage → decrease the amplification factor (step down) according to the relationship between the peak voltage and the reference voltage, and the peak voltage <the reference voltage → increase the amplification factor. The signal is input to the AGC control counter 9a as an up / down signal for performing (step-up) control, and the count value is increased / decreased in synchronization with the frame signal [(e) in FIG. 4]. A
The amplification rate determined by the count value is instructed from the GC control counter 9a to the amplifier 1, and the amplifier amplifies the data signal at the amplification rate.

FIG. 5 is a graph showing the relationship between the peak value of the data signal and the amplification factor. As shown in the figure, when the peak value is A, the amplification factor of the amplifier is adjusted to B.

[0009]

In the conventional automatic gain controller of the peak value detection type described above, when noise is included in the data signal, the data signal is erroneously detected as A as shown in FIG. As a result, the gain is detected as A ', and as a result, an inappropriate amplification factor B' is adjusted. Therefore, the conventional example has a problem that an error occurs at the time of data identification.

[0010]

Auto gain co <br/> controller of SUMMARY OF THE INVENTION The present invention performs a peak detection circuit for detecting a peak voltage of the output signal of the amplifier for amplifying a data signal, a sample-and-hold data A sample and hold circuit,
A comparator that compares the peak voltage with the reference voltage, and counts a continuous period in which the output value of the comparator is equal to or greater than a certain value, and the output value of the comparator is equal to or less than a certain value.
Turning a first counter that will be reset when the counts the continuous time output value is less than or equal to a predetermined value of said comparator, the output value of the comparator is turned more than a certain value
Changing the amplification factor of the amplifier according to an output value of the comparator when the second counter that will be reset, the count value of the first counter or the second counter exceeds a predetermined value when the Means.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 denotes an amplifier that amplifies an input signal and transmits the amplified signal to a data discriminating circuit. This is a sample and hold circuit that holds the detection value of the value detection circuit 2.

Reference numeral 4 denotes a frame generation circuit for resetting the peak value detection circuit 2 and generating a frame signal defining the sampling timing of the sample / hold circuit 3, and 5 denotes a peak value held by the sample / hold circuit 3. A comparator for comparing with a reference value, 6 is a counter for counting a continuous up signal output from the comparator 5, 7 is a counter for counting a continuous down signal output from the comparator 5, and 8 is a counter for counting the counters 6 and 7. The run / stop control circuit 9 outputs a run instruction when the value exceeds a predetermined value. The run / stop control circuit 9 increases the count value according to the output value of the comparator 5 when the run instruction is issued from the run / stop control circuit 8. Or down
The AGC control counter instructs the amplifier 1 to step up / down the amplification rate according to the count value.

Next, the operation of this embodiment will be described.
As in the conventional example, an up / down signal corresponding to the peak value of the data signal output from the amplifier 1 is output from the comparator 5.
Output from This output signal is input to the counters 6 and 7 for each frame, and the counters 6 and 7 perform the following operations, respectively.

The counter 6 counts up when a "step-up signal" is input, and the "step-down signal"
Is reset (count value = 0). The counter 7 counts up when a “step-down signal” is input, and is reset (count value = 0) when a “step-up signal” is input.

The run / stop control circuit 8 outputs the following instruction to the AGC counter 9 according to the values of the counters 6 and 7. When the counter 6 is 4 or more or the counter 7 is 4 or more → The run instruction is output. When the counter 6 is less than 4 and the counter 7 is less than 4 → output the stop instruction. By the run instruction of the run / stop control circuit 8, AG
The C control counter 9 performs a step change operation on the amplifier 1 and stops the step change operation by the stop command (the count operation is also stopped). Counters 6, 7 and run /
FIG. 2 shows an operation example of the stop control circuit.

In the prior art, as shown in FIG. 4, the step change is repeated without interruption. In the present embodiment, however, the step change is performed only when the up signal or the down signal is repeated a predetermined number of times. Fewer times. Since the amplification factor is not erroneously changed due to noise or the like, the amplification factor of the amplifier can be appropriately maintained. In this embodiment, the counter r
Although the un / stop determination value is set to 4, this value can be changed as appropriate.

[0017]

As described above, according to the present invention, when the comparator for comparing the peak voltage with the reference voltage continuously outputs the up signal or the down signal, the amplification factor of the amplifier is changed stepwise. Therefore, according to the present invention, it is possible to prevent the noise from being erroneously recognized as a normal signal and changing the amplification factor. Therefore, according to the present invention, the amplification factor of the amplifier can always be appropriately maintained,
Data reading errors can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the embodiment of FIG. 1;

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is an operation explanatory diagram of a conventional example.

FIG. 5 is a characteristic diagram for explaining an AGC operation.

[Explanation of symbols]

 Reference Signs List 1 amplifier 2 peak value detection circuit 3 sample and hold circuit 4 frame generation circuit 5 comparator 6, 7 counter 8 run / stop control circuit 9, 9a AGC control counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03G 3/20

Claims (1)

(57) [Claims] 1. A peak value detection circuit that detects a peak voltage of a signal output from an amplifier and is reset every predetermined period, a comparator that compares a peak voltage within a predetermined period with a reference voltage, and an output of the comparator. Count the continuous period when the value is above a certain value, and when the output value of the comparator is below a certain value
A first counter that will be reset when turned on, counts the continuous time output value is less than or equal to a predetermined value of said comparator, the output value of the comparator is a predetermined value or more
A second counter that will be reset when turned on, the amplification factor of the first counter or the count value of said second counter in response to the output value of the comparator when it exceeds a predetermined value amplifier An automatic gain controller comprising: