JP2897737B2 - Logic synthesis device and logic synthesis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis device and a logic synthesis method for generating a logic circuit described at a gate level from a logic circuit described in a hardware description language. The present invention relates to a logic synthesis method for synthesizing a device and a spare circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration of a conventional logic synthesizer of this type for generating a logic circuit described at a gate level from a logic circuit described in a hardware description language.

[0003] As shown in FIG.
Inputs the hardware description file 100, generates and outputs a logic synthesis result file 120. In the hardware description file 100, a logic circuit is described in a hardware description language. Logical synthesis result file 102
Describes a logic circuit at a gate level. The logic synthesis device 110 includes an input analysis unit 111 for analyzing the structure of the hardware description file 100, and an input analysis unit 111
Synthesis unit 113 for logically synthesizing the analysis result by the logic, logic optimization unit 114 for optimizing the processing result by the logic synthesis unit 113, and converting the processing result by the logic optimization unit 114 into a logic circuit described at the gate level. And an output format conversion unit 115 for outputting a logic synthesis result file 102 in EDIF format.

In the LSI circuit design, a spare logic circuit (hereinafter, referred to as a spare circuit) may be provided separately from a regular logic circuit (hereinafter, referred to as a regular circuit). The spare circuit is provided so that when a failure is found after the manufacture of the LSI, it can be corrected in a short time with a small number of steps only by changing the wiring. FIG. 4 shows an example of a logic circuit provided with such a spare circuit.

The illustrated logic circuit comprises a first inverter gate G01 and a second inverter gate G02 forming a normal circuit, and an inverter gate G1 forming a spare circuit.
It has a one- and three-input NAND gate G12 and a three-input NOR gate G13. The first inverter gate G01 is
The input terminal is connected to the wiring n01, and the output terminal is connected to the wiring n02.
Connect to The second inverter gate G02 has an input terminal connected to the wiring n02 and an output terminal connected to the wiring n03. The wiring n01 and the wiring n03 are connected to the gate of another regular circuit (not shown). Inverter gate G11
Connects the input terminal to the wiring n02 and connects the output terminal to the wiring n02.
Connect to 11. The three-input NAND gate G12 has an input terminal connected to the wiring n11 and an output terminal connected to the wiring n12. The three-input NOR gate G13 connects the input terminal to the wiring n0.
2 and the output terminal is connected to the wiring n13. The other ends of the wirings n12 and n13 connected to the gates G12 and G13 are not connected. Spare circuit gates G11, G1
2. G13 can be used as a correction gate by changing the wiring connected to the input terminal and the output terminal when a failure occurs.

Conventionally, when a logic circuit including a spare circuit as described above is logically synthesized, the hardware description file 100 replaces a part corresponding to each gate of the spare circuit with another gate during logic synthesis. It is necessary to add a constraint (don-replace) to be prohibited. When the hardware description file 100 to which the wiring use prohibition constraint is added is input to the logic synthesis device 110, first, the input analysis unit 111 analyzes the structure of the hardware description file 100. Next, the logic synthesis unit 113 executes the constraint (don-repl) described in the portion of the hardware description file 100 corresponding to the spare circuit.
ace) is interpreted as a constraint (dont-replace).
The part where is added is logically synthesized without being replaced by another gate. Next, the logic optimizing unit 113 optimizes the logic circuit that has undergone the logic synthesis. Next, the output format converter 1
15 converts the optimized logic circuit into a gate-level description and outputs a logic synthesis result file 102 in EDIF format. The logic synthesis result file 102 generated in this way includes the gate of the spare circuit.

[0007] As described above, the conventional logic synthesizer includes:
In general, there is no means for synthesizing the above-described spare circuit when performing logic synthesis of a logic circuit. Therefore, in the hardware description file, the wiring use prohibition constraint is not added to the net of the spare circuit portion, and the net between the gates of the spare circuit is connected to the gate of another normal circuit by the logic synthesis process.

[0008]

The above-described conventional logic circuit logic synthesizer has the following problems. The first problem is that the fault of the logic circuit is corrected because the net of the spare circuit part is connected to the gate of the regular circuit other than the connection gate described in the hardware description file at the time of logic synthesis. Therefore, the gate of the spare circuit cannot be easily used. The reason is that, according to the conventional logic synthesis device, the wiring use prohibition constraint is not added to all or some of the nets of the spare circuit unit during logic synthesis, so that the net between the gates of the spare circuit unit may be different. Is connected to the gate of the normal circuit.

A second problem is that when a logic circuit is large-scale, it is difficult to designate a net of a spare circuit portion in a hardware description file before logic synthesis. The reason is that it is not easy to detect all the nets between the gates of the spare circuit portion in the hardware description file.

An object of the present invention is to provide a logic synthesis device and a logic synthesis method for executing logic synthesis of a logic circuit without connecting a net of a spare circuit to logic of a regular circuit not intended by a designer.

Another object of the present invention is to provide, in addition to the above objects, a logic synthesizing apparatus and a logic synthesizing apparatus for automatically extracting all nets between gates of a spare circuit portion in a hardware description file when executing logic synthesis. The purpose is to provide a synthesis method.

[0012]

A logic synthesizing apparatus according to the present invention for achieving the above object inputs a file of a logic circuit described in a hardware description language and analyzes the structure of the described logic circuit. An input analysis unit, based on the analysis result of the input analysis unit, detects a cell to which a replacement prohibition attribute is added from the logic circuit, and detects a net connected to an output terminal of the cell; Means for automatically adding a replacement prohibition attribute to the logic circuit, logic synthesis means for performing logic synthesis on a logic circuit to which the replacement prohibition attribute has been added by the inter-gate net protection means, and logic synthesis by the logic synthesis means. Optimizing means for optimizing the specified logic circuit, and converting the logic circuit optimized by the logic optimizing means into a logic circuit described at a gate level to perform logic synthesis And an outputting format conversion means for outputting the result file.

According to a second aspect of the present invention, in the logic synthesizing apparatus according to the present invention, the inter-gate net protection means detects a replacement prohibited gate from the logic circuit analyzed by the input analyzing means and extracts a cell name. Means, an output terminal detecting means for detecting an output terminal of a cell having a cell name extracted by the replacement gate detecting means and extracting a pin name, and a pin having a pin name extracted by the output terminal detecting means. A connection net detecting unit that detects a connection net and extracts a net name; and a replacement prohibition attribute adding unit that adds a replacement prohibition attribute to a net having the net name extracted by the connection net detection unit. I do.

According to a third aspect of the present invention, the logic synthesizing unit does not replace the cell to which the replacement prohibition attribute is added with another cell, and outputs the net to which the replacement prohibition attribute is added. Performing logic synthesis of the logic circuit output from the gate-to-gate net protection unit without connecting to a net other than the net describing the connection on the hardware description file; 3. The logic synthesizing apparatus according to claim 1, wherein the logic circuit optimizes the logic circuit without violating restrictions included in an output of the logic synthesizing unit.

A logic synthesis method according to the present invention that achieves the above object includes a first step of inputting a file of a logic circuit described in a hardware description language and analyzing the structure of the described logic circuit; Based on the analysis result of the input analysis unit, a cell to which a replacement prohibition attribute is added is detected from the logic circuit, a net connected to an output terminal of the cell is detected, and the net is automatically replaced with the net. A second step of adding a prohibition attribute, a third step of performing logic synthesis on the logic circuit to which the replacement prohibition attribute has been added by the inter-gate net protection means, and a logic circuit synthesized by the logic synthesis means. A fourth step of optimizing, and converting the logic circuit optimized by the logic optimization means into a logic circuit described at a gate level and outputting a logic synthesis result file Characterized in that it comprises a fifth step.

In the logic synthesis method according to the present invention, the second step of adding a replacement prohibition attribute to the predetermined gate-to-gate net includes detecting a replacement prohibition gate from the logic circuit analyzed by the input analysis means. Extracting the cell name by detecting the output terminal of the cell having the cell name extracted by the replacement gate detecting means, and extracting the pin name; and extracting the pin name by the output terminal detecting means. Detecting a connection net of a pin having a net name and extracting a net name; and adding a replacement prohibition attribute to the net having the net name extracted by the connection net detection means.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a logic synthesis apparatus according to one embodiment of the present invention.

Referring to FIG. 1, a logic synthesizer 20 according to the present embodiment includes an input analyzer 21 and a gate-to-gate net protector 2.
2, a logic synthesis unit 23, a logic optimization unit 23, and an output format conversion unit 25. As illustrated, the logic synthesis device 20 receives a hardware description file 10 including a logic circuit described in a hardware description language, and generates a logic synthesis result file 30 including a logic circuit described at a gate level. Output. In the drawing, only the characteristic configuration of the present embodiment is described, and other general configurations are omitted. Actually, it is needless to say that an input device for inputting various operation commands, a storage device for storing the input hardware description file 10 and a file subjected to predetermined processing are provided.

The hardware description file 10 is described in a hardware description language, and includes a hardware description portion of a regular circuit portion and a description portion of a spare circuit portion. FIG.
FIG. 3 is a diagram showing an example in which a logic circuit to be designed is described in a hardware description language.
Part of. The spare circuit is provided with an attribute indicating a replacement prohibition attribute that prohibits the cell from being changed to another cell during logic synthesis. FIG. 4 is a diagram showing an example of a circuit diagram corresponding to contents described in the hardware description language shown in FIG.

In the logic synthesizer 20, the input analyzer 2
1 is realized by a CPU or the like controlled by a program, inputs a hardware description file 10, and analyzes the structure of the described logic circuit.

The gate-to-gate net protection unit 22 is realized by a CPU or the like controlled by a program, detects a description of a spare circuit part based on the analysis result of the input analysis unit 21, and changes the wiring of the spare circuit part to another gate. Add a constraint (replacement prohibition attribute) that prohibits connection to. As shown in FIG.
The inter-gate net protection unit 22 includes a replacement prohibition gate detection unit 2.
21, an output terminal detection unit 222, and a connection net detection unit 2
23 and a replacement prohibition attribute adding unit 224.

The replacement prohibition gate detecting section 221 detects a cell of the spare circuit in which the replacement prohibition attribute is added to the cell based on the output of the input analysis section 21. Output terminal detector 2
22 detects an output terminal of the cell detected by the replacement prohibition gate detection unit 221. The connection net detection unit 223 detects a wiring connected to the output terminal detected by the output terminal detection unit 222. The replacement prohibition attribute adding unit 224 adds a replacement prohibition attribute to the wiring detected by the connection net detection unit 223.

The logic synthesizing unit 23 is realized by a CPU or the like controlled by a program, inputs the output of the replacement prohibition attribute adding unit 224 of the inter-gate net protection unit 22, and performs logic on the logic circuit to which the replacement prohibition attribute is added. Perform synthesis.

The logic optimizing unit 24 is realized by a CPU or the like controlled by a program, inputs the output of the logic synthesizing unit 23, and optimizes the logic circuit that has been logically synthesized.

The output format conversion unit 25 is realized by a program-controlled CPU or the like, receives an output of the logic optimization unit 24, and converts the optimized logic circuit into a logic circuit described at a gate level. , A logical synthesis result file 30 in EDIF format.

Next, the operation of this embodiment will be described in detail with reference to the block diagram of FIG. 1 and the flowchart of FIG.

When the hardware description file 10 is input to the logic synthesis device 20, first, the input analysis unit 21 converts the description of the hardware description file 10 into an internal processing format and analyzes the structure of the logic circuit.

Next, the inter-gate net protection unit 22 detects a spare circuit from the output of the input analysis unit 21 and adds a constraint that prohibits connection of the wiring of the spare circuit unit to another gate. Here, the inter-gate net protection unit 22 will be described in detail with reference to FIG.

First, the prohibited gate detection unit 221 checks whether there is a gate to which a replacement prohibition attribute has been added to the gate of the input logic circuit. If there is a gate to which the replacement prohibition attribute is added, the cell name is extracted and registered in the cell name list (step 201). If the cell name has been detected and registered in the cell name list, the process proceeds to the output terminal detection unit 222. On the other hand, if the cell name registered in the cell name list cannot be detected, the processing is terminated (step 202).

When the cell name is detected, the output terminal detecting section 222 detects the output terminal of one cell in the cell name list. In the first detection processing, the cell having the first cell name in the cell name list is a target of output terminal detection. In the second and subsequent detection processing, a cell having a cell name next to the cell that has been subjected to the last detection processing in the cell name list is a target of output terminal detection. If the target cell has an output terminal or an input / output terminal, the terminal name is extracted into a pin name list (step 203). If the pin name is detected and registered in the pin name list, the connection net detecting unit 22
The process moves to the process of No. 3.

On the other hand, if the pin name registered in the pin name list cannot be detected, the cell name list is checked, and if there is a cell name next to the processed cell, the flow returns to step 203, and the next cell An output terminal is detected for a cell having a name (steps 204 and 210). If there is no next cell name in the cell name list, the process ends.

When the pin name is detected, next, the connection net detection unit 223 detects the net of one pin in the pin name list. In the first detection process, the pin having the first pin name in the pin name list is a target of the net detection. In the second and subsequent detection processes, a pin having a pin name next to the pin that has been subjected to the last detection process in the pin name list is subjected to net detection. If a wiring is connected to the target pin, the wiring name is extracted and registered in the net name list (step 205). When the wiring name is detected and registered in the net name list, the processing shifts to the processing of the replacement prohibition attribute adding unit 224.

On the other hand, if the wiring name registered in the net name list cannot be detected, the pin name list is checked, and if there is a pin name next to the processed pin, the process returns to step 205 and the next pin Connection nets are detected for pins having names (steps 206 and 209). If there is no next pin name in the pin name list, it is checked whether or not the cell name list has a cell name next to the cell subjected to the process. If there is a next cell name, the processing after step 203 is repeated ( Steps 209 and 210). If there is no next cell name in the cell name list, the process ends.

When the net name is detected, the replacement prohibition attribute adding section 224 selects one net in the net name list and adds the replacement prohibition attribute (step 20).
7). In the first process, the net having the first net name in the net name list is to be subjected to the replacement prohibition attribute addition. In the second and subsequent processes, the net having the net name next to the net to which the replacement prohibition attribute has been added last in the net name list is to be added with the replacement prohibition attribute. Then, the process of step 207 is repeated until the replacement prohibition attribute is added to all nets in the net name list (step 208).

When the replacement prohibition attribute is added to all nets, it is checked whether or not the pin name list has a pin name next to the pin subjected to the processing.
The processing after step 205 is repeated (step 20
8, 209). If there is no next pin name in the pin name list,
Further, it is checked whether or not the cell name list has a cell name next to the cell on which the processing has been performed.
10). If there is no next cell name in the cell name list, the process ends.

The logic synthesis section 23 performs logic synthesis of the logic circuit based on the output of the inter-gate net protection section 22.
At this time, the cells and nets to which the replacement prohibition attribute is added are not replaced with other cells or connected to other nets during logic synthesis.

The logic optimizing unit 23 optimizes the logic circuit that has undergone logic synthesis based on the output from the logic synthesizing unit 22. At this time, optimization is performed by the inter-gate net protection unit 22 according to the constraints added to the gates and nets of the logic circuit.

The output format conversion unit 24 converts the optimized logic circuit into a logic circuit described at the gate level based on the output from the logic optimization unit 23, and
The logic synthesis result file 30 in the F format is output.

As described above, according to the present embodiment, the detection of a net for which connection to another net is prohibited is performed based on the cell to which the replacement prohibition attribute is added. Even if the replacement prohibition attribute is not described, it is possible to easily set the restriction on the use of the wiring for the spare circuit only by describing the replacement prohibition attribute in the cell in the hardware description file 10.

Next, the operation of this embodiment will be described in detail with reference to a specific description example of a logic circuit.

FIG. 3 is a diagram showing an example in which a logic circuit to be designed is described in a hardware description language. The description shown is
It is a part of the hardware description file 10 and includes a hardware description part of a regular circuit and a description part of a spare circuit. "// synthesi" on the hardware description
"s dont_replace G11" indicates that the replacement prohibition attribute is added to the gate G11 in the present description example. As shown in the drawing, the cells G11, G12, and G13 constituting the spare circuit are each provided with a replacement prohibition attribute. Also, the cell G0 constituting the normal circuit
1. No replacement prohibition attribute is added to G02.

FIG. 5 is a diagram showing an example in which the operation of the gate-to-gate net protection unit 22 in this embodiment is implemented using a command. Hereinafter, the operation of the inter-gate net protection unit 22 will be described with reference to FIG.

First, the replacement prohibited gate detection unit 221 detects the replacement prohibited gate. First, "cells_
list <select ("*", cell, dont
_Replace == true) ”, all the cells G01, G02,.
It is checked whether there is a cell to which G11, G12, G13,. Replacement prohibition attribute dont_place
Is added to the cell name list cells_list (FIG. 2, step 20).
1). Since the replacement prohibition attribute is added to the cells G11, G12, and G13 of the spare circuit, cells_li
In st, G11, G12, and G13 are registered.

Next, "if (cells_list!
= “″)}”, A conditional branch is performed depending on the presence or absence of a cell name in cells_list (FIG. 2, step 2)
02). G11, G1 in cells_list
2 and G13 are registered, the command in the parentheses is executed. If the cells_list is blank, the replacement prohibition gate detection process ends, and the logic synthesis by the logic synthesis unit 23 is subsequently performed.

Second, an output terminal is detected by the output terminal detection section 222. First, "foreach (acel
(1, cells_list)} ”, first, the first cell G11 in the cells_list is selected and assigned to the variable acell.

Next, "pins_list <select"
t (acell, pin, pin_type == out
|| pin_type == inout)], for the cell G11 assigned to acell,
A terminal in the form of out indicating output or in indicating input / output
Check if there is a terminal of the form out. If there is a corresponding terminal, its pin name is registered in a pin name list pins_list (see step 203 in FIG. 2). Where in
The terminal i1 of the verter gate is in type, and o1
Is in the out format. Similarly, the terminals i1, i2 and i3 of the nand gate are in type, and o1 is ou
It is assumed that the format is t. Also, the terminal i1 of the nor gate,
It is assumed that i2 and i3 are in format and o1 is in out format. A terminal o1 of the cell G11 is connected to an output out indicating an output.
Because of the format, o1 is registered in pins_list.

Next, "if (pins_list!
= “″)}”, A conditional branch is performed depending on the presence or absence of a cell name in pins_list (FIG. 2, step 20).
4). Since o1 is registered in the pins_list, the command in parentheses is executed. Suppose, pi
If ns_list is blank, the process proceeds to the search for the next cell name (see step 210 in FIG. 2).

Third, a connection net is detected by the connection net detection unit 223. First, "foreach (ap
(in, pins_list)} ”, first, the first pin o1 in the pins_list is selected and assigned to the variable apin.

Next, “nets_list <select”
In the row of “t (apin, net)”, it is checked whether there is a net connected to the pin o1 with respect to the pin o1 assigned to apin. If there is a connected net, the net name is written in net name list nets_l
is registered (see FIG. 2, step 205). Since the net n11 is connected to the terminal o1,
n11 is registered in s_list.

Next, “if (nets_list!
= “″)}”, A conditional branch is performed depending on the presence or absence of a net name in nets_list (FIG. 2, step 2)
06). Since n11 is registered in nets_list, the commands in the parentheses are executed. what if,
If the nets_list is blank, the process moves to the search for the next pin name (FIG. 2, step 209).

Fourth, the replacement prohibition attribute adding section 224 adds a replacement prohibition attribute to the wiring. First, "forea
ch (anet, nets_list)} ”, the first line n1 in the nets_list
Select 1 and substitute it for the variable anet.

Next, "set_dont_replac"
In e (net, anet), an attribute is added to the net n11 assigned to the anet for prohibiting the change of the wiring at the time of logic synthesis (see step 207 in FIG. 2).

Fifth, the process proceeds to the search for the next net name (see step 208 in FIG. 2). "Foreach (a
net, nets_list)}, n
Since there is only the distribution n11 in the ets_list, the process ends, and the process proceeds to the search for the next pin name (see step 209 in FIG. 2). If there are a plurality of net names in the nets_list, the process returns to the fourth operation, the next net name is selected and assigned to the variable anet, and a replacement prohibition attribute is added to the wiring.

Sixth, the processing shifts to the search for the next pin name.
"Foreach (apin, pins_lis
t) ｛｝ ”, in pins_list,
Since there is only the wiring o1, the process ends, and the process proceeds to the search for the next cell name (see step 210 in FIG. 2). what if,
If there are multiple pin names in the pins_list, the third
Returning to the operation of (1), the next pin name is selected and assigned to the variable apin, and a connection net is detected for the pin.

Seventh, the process proceeds to the search for the next cell name. First, "foreach (acell, cell_lis
In the row “t) ｛｝”, the cell names G11, G12, and G13 are substituted in the cells_list. Therefore, the cell name G12 next to the cell name G11 for which the processing has been completed is selected and substituted into the variable acell. . And cell name G
Perform the above-described second to seventh operations on the net n12 connected to the output terminal o1 of the cell name G12.
, An attribute that prohibits the change of the wiring at the time of logic synthesis is added.

Next, similarly, the above-described second to seventh processes are performed on the cell name G13 to change the wiring of the net n13 connected to the output terminal o1 of the cell name G13 at the time of logic synthesis. Add an attribute that prohibits.

Finally, "foreach (acell,
celllist)} "line, cells_
Since there is no cell name next to the cell name G13 in the list, the process ends (see step 210 in FIG. 2). Then, the process proceeds to logic synthesis by the logic synthesis unit 23.

The logic synthesis section 23 performs logic synthesis of the logic circuit output from the inter-gate net protection section 22. At this time, cells G11 and G1 to which the replacement prohibition attribute is added
2. G13 does not replace with another cell. Also, nets n11, n12, n1 to which the replacement prohibition attribute is added
No. 3 does not connect to a net other than the net describing the connection on the hardware description file 10. The logic optimization unit 23 optimizes the logic circuit according to the constraints included in the output of the logic synthesis unit 22.

As described above, the cells G11, G12, and G13 constituting the spare circuit are not connected to other nets other than those whose connection is described in the hardware description file 10, and the logic circuit is logically synthesized. Is done.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0062]

As described above, according to the logic synthesizing apparatus of the present invention, it is possible to add a restriction for prohibiting a net from being changed during logic synthesis on a desired net before logic synthesis. is there. Therefore, logic synthesis of the logic circuit can be performed without connecting the net of the spare circuit to the logic of the normal circuit other than the net described in the hardware description file. As a result, in a logic circuit including a spare circuit logically synthesized according to the present invention, the spare circuit can be easily used when the circuit after circuit design is corrected, and the number of work steps can be reduced.

In order to detect a cell in which the replacement prohibition attribute is added to the cell name, detect a net connected to the output terminal of the cell, and automatically add the replacement prohibition attribute to the net, Even if the replacement prohibition attribute is not described in all the target nets, it is possible to easily set the restriction on the use of the wiring of the spare circuit portion simply by describing the replacement prohibition attribute in the cell in the hardware description file. This has the effect.

Further, since there is no increase in the number of steps required for adding the replacement prohibition attribute to the net of the spare circuit section, the efficiency of the design work can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic synthesis device according to one embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of an inter-gate net protection unit.

FIG. 3 is a diagram illustrating a description example of a design target logic circuit in a hardware description language.

FIG. 4 is a diagram showing a configuration example of a circuit diagram corresponding to contents described in the hardware description language of FIG. 3;

FIG. 5 is a diagram illustrating an example in which the operation of the inter-gate net protection unit is performed using a command.

FIG. 6 is a block diagram illustrating a configuration of a conventional logic synthesis device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Hardware description file 20 Logic synthesizer 21 Input analysis part 22 Net protection part between gates 23 Logic synthesis part 24 Logic optimization part 25 Output format conversion part 30 Logic synthesis result file 221 Replacement prohibition gate detection part 222 Output terminal detection part 223 Connection net detection unit 224 Replacement prohibition attribute addition unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50 H01L 21/82 JICST file (JOIS) Patent file (PATOLIS)

Claims (5)

(57) [Claims] 1. A logic synthesis device that inputs a file of a logic circuit described in a hardware description language, converts the file into a logic circuit described at a gate level, and outputs a logic synthesis result file. An input analysis unit for inputting a file of the described logic circuit and analyzing the structure of the described logic circuit; and a replacement prohibition attribute is added from the logic circuit based on an analysis result of the input analysis unit. Detecting a cell, detecting a net connected to an output terminal of the cell, and automatically adding a replacement prohibition attribute to the net; an inter-gate net protection unit; Logic synthesis means for performing logic synthesis on the added logic circuit, and logic optimization means for optimizing the logic circuit synthesized by the logic synthesis means , Logic synthesis device characterized by comprising an output format converting means for outputting the converted logic circuit optimized by the logic optimization means to the logic circuit described in the gate-level logic synthesis result file. 2. The replacement gate detection means for detecting a replacement inhibition gate from a logic circuit analyzed by the input analysis means and extracting a cell name, wherein the replacement gate detection means extracts the cell name. Output terminal detecting means for detecting an output terminal of a cell having the selected cell name and extracting a pin name, and detecting a connection net of the pin having the pin name extracted by the output terminal detecting means to extract a net name 2. The logic synthesizing apparatus according to claim 1, further comprising: a connection net detecting unit that performs a replacement prohibition attribute on the net having the net name extracted by the connection net detection unit. . 3. The logic synthesizing unit does not replace a cell to which a replacement prohibition attribute is added with another cell and connects a net to which the replacement prohibition attribute is added on the hardware description file. Perform logic synthesis of the logic circuit output from the inter-gate net protection means without connecting to other nets other than the described net; and the logic optimization means is included in the output of the logic synthesis means. 3. The logic synthesis apparatus according to claim 1, wherein the logic circuit is optimized without violating restrictions. 4. A logic synthesis method for inputting a file of a logic circuit described in a hardware description language, converting the file into a logic circuit described at a gate level, and outputting a logic synthesis result file, comprising the steps of: A first step of inputting a file of the described logic circuit and analyzing the structure of the described logic circuit; and adding a replacement prohibition attribute from the logic circuit based on an analysis result of the input analysis means. A second step of detecting a cell connected, detecting a net connected to an output terminal of the cell, and automatically adding a replacement prohibition attribute to the net; A third step of performing logic synthesis on the added logic circuit; a fourth step of optimizing the logic circuit synthesized by the logic synthesis unit; Serial logic synthesis method characterized in that it comprises a fifth step of outputting the optimized converts a logic circuit to the logic circuit described in the gate-level logic synthesis result file by the logic optimization means. 5. A second step of adding a replacement prohibition attribute to the predetermined inter-gate net, comprising: detecting a replacement prohibition gate from a logic circuit analyzed by the input analysis means and extracting a cell name; Detecting the output terminal of the cell having the cell name extracted by the replacement gate detecting means to extract the pin name; and detecting the connection net of the pin having the pin name extracted by the output terminal detecting means. 5. The logic synthesis method apparatus according to claim 4, further comprising the steps of: extracting a net name; and adding a replacement prohibition attribute to the net having the net name extracted by the connected net detection unit.