JP2891685B2 - Transmitter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitter for use in a railway security device such as an ATC device, and more particularly, to a reduction in size and cost of a transmitter.

[0002]

2. Description of the Related Art AT output from a transmitter such as an ATC device
The C signal and the like are directly involved in the control of the train, and no error is allowed. Therefore, it is necessary to monitor and check whether the created transmission signal is a signal to be output originally. In order to confirm the suitability of the transmission signal, a conventional transmitter includes a signal generation unit 71 for generating the transmission signal and a receiver equivalent function unit 8 for monitoring and checking the generated transmission signal as shown in FIG.
1 is provided. The modulator 72 of the signal generator 71 converts the carrier transmitted from the carrier generator 73 into a modulated wave generator 7.
And modulates the PWM signal with the modulated wave sent from 4 and sends it to the PWM modulating unit 75. Occur. This PWM wave is power-amplified by a switching amplifier 77 and then a low-pass filter 78.
To the track circuit 8 as a transmission signal. The receiver equivalent function unit 81 feeds back the transmission signal output to the orbit circuit 8 and removes noise from the orbit by the noise filter 82, selects a frequency band through the carrier wave filter 83, and demodulates by the demodulation unit 84. Later, the modulation wave was selected through the selection filter 85, and the level detection unit 86 checked the modulation wave.

[0003]

As described above, if a transmitter such as an ATC device is provided with a receiver-equivalent functional unit to check a transmission signal, the transmitter becomes large. Also, since the receiver-equivalent functional unit feeds back the transmission signal output to the orbit, it is necessary to completely remove noise from the orbit with a noise filter, and the transmitter becomes larger and more expensive. I will.

[0004] The present invention has been made to solve such a disadvantage, and has a function of checking whether a transmission signal is appropriate.
It is intended to obtain a small and low-cost transmitter.

[0005]

A transmitter according to the present invention has a processing unit, two signal generation units and a comparison circuit unit, and each of the signal generation units is controlled by a control command from the processing unit.
The WM wave is created and output, and the comparison circuit unit compares the PWM waves output from each signal generation unit to create a comparison signal indicating whether they match or not, and outputs the comparison signal to the processing device. The first D flip-flop has a clock input terminal to which a PWM wave output from one of the signal generators is input, and a D input terminal to have a D input terminal. The output of the second delay circuit is input and Q
An output is input to the first delay circuit, a PWM wave output from the other signal generator is input to a clock input terminal of the second D flip-flop, and an output of the first delay circuit is input to a D input terminal. Is input, and the Q output is input to the second delay circuit and output to the processing device as a comparison signal. The processing device determines whether the input comparison signal is an alternating signal or a DC signal,
It is characterized in that it is determined whether the PWM waves output from the two signal generators match or not.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A transmitter according to the present invention has a processing unit, two systems of signal generation units and comparison circuit units. Each signal generator generates and outputs a PWM wave according to a control command from the processing device. The comparison circuit unit has two D flip-flops and two delay circuits, and a clock input terminal of the first D flip-flop has a P output from one signal generation unit.
The WM wave is input, the output of the second delay circuit is input to the D input terminal, the Q output is input to the first delay circuit, and the other signal is generated at the clock input terminal of the second D flip-flop. The PWM wave output from the section is input, the output of the first delay circuit is input to the D input terminal, and the Q output is input to the second delay circuit and output to the processing device as a comparison signal. In the first delay circuit and the second delay circuit, a delay time is set according to an allowable value of a difference between pulse widths of PWM waves caused by variations in components of the two signal generation units.

One of the PWs input to the comparison circuit is
If the fall timing of the M wave is within the delay time from the fall timing of the other PWM wave, the D inputs of the two D flip-flops are different, and the Q inputs of the two D flip-flops are different at the fall timing of each PWM wave. The output is inverted, and the comparison signal output from the comparison circuit becomes an alternating signal in which a high level and a low level are alternately output. However, the falling timing of one PWM wave is
When the delay time is not within the delay time from the fall timing of the WM wave, that is, when the difference between the pulse widths of the PWM waves generated by the two signal generation units exceeds an allowable value, the D inputs of the two D flip-flops are set to the same value. Thereafter, the Q outputs of the two D flip-flops become the same, and the comparison signal output from the comparison circuit becomes a DC signal. The processing device determines whether the comparison signal is an alternating signal or a DC signal, and determines whether the PWM waves output from the two signal generators match or not.

[0008]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. As shown in FIG.
Has a processing device 2, two-system signal generators 3 and 4, a comparator circuit 5, a switching amplifier 6, and a low-pass filter 7. The processing device 2 has a CPU, a memory, and the like, sends the same control command to each of the signal generators 3 and 4 so as to generate necessary signals, and transmits the same to the track circuit 8 by a comparison signal from the comparison circuit 5. Determine the suitability of the signal. The signal generators 3 and 4 are composed of the same circuit, and generate and output a necessary PWM wave according to a control command from the processing device 2.
The comparison circuit 5 is a PWM output from the signal generators 3 and 4.
The wave is compared to generate a comparison signal indicating whether the waves match or not, and outputs the signal to the processing device 2.
As shown in FIG. 7, the circuit has two D flip-flops 51 and 52 and two delay circuits 53 and 54. At the clock input terminal of the D flip-flop 51, a PWM wave (hereinafter referred to as PWM-A) output from the signal generator 3 is supplied to the inverter 5.
5, the output of the delay circuit 54 is input to the D input terminal, and the Q output is input to the delay circuit 53. The PWM wave (hereinafter referred to as PWM-B) output from the signal generator 4 is input to the clock input terminal of the D flip-flop 52 via the inverter 56, and the output of the delay circuit 53 is input to the D input terminal. The Q output is input to the delay circuit 54 and output as a comparison signal.

In describing the operation of the transmitter 1 configured as described above, the operation principle will be described first. PWM-A created by signal generator 3 and PWM created by signal generator 4
Even if the MBs are generated by the same control command and generate the same signal, the timing is slightly shifted. For example, as shown in FIG.
When a PWM wave is generated by the comparator 36 using the transmission wave generated by the counter 32 and the low-pass filter 33 and the triangular wave generated by the counter 34 and the D / A converter 35, the signal generator 3 , 4 contain an analog circuit such as a low-pass filter 33 and a comparator 36. Due to the variation of individual components, as shown in FIG.
The pulse width of PWM-B is longer than the pulse width of -A, or the pulse width of PWM-A is larger than the pulse width of PWM-A as shown in FIG.
The pulse width of MB becomes shorter, and PWM-A and PWM-
A timing difference ΔT occurs at the fall of B. Comparator 3
As shown in FIG. 5, the pulse width of the PWM wave generated in step 6 depends on the level VL at the time of sampling the transmission wave and the triangular wave, and the difference between the levels VL is the difference in pulse width of the PWM wave. Further, even if the phases of the two transmission waves are shifted or there is a level difference, a difference occurs in the pulse width of the PWM wave. The difference between the pulse widths of PWM-A and PWM-B caused by these factors is fixed if the individual components of the low-pass filter 33 and the comparator 36 are determined at the time of manufacturing. The difference can be suppressed within a certain limit by adjustment.

However, when the circuits constituting the signal generators 3 and 4 fail and the frequency of the transmission wave shifts, the PWM-A
And the pulse width of PWM-B periodically change from “0” to the difference between the positive maximum value and the negative maximum value of the transmission wave. Therefore, PWM-A and PWM-B due to variation of parts at the time of manufacturing
Is allowed, and when the difference between the pulse widths of PWM-A and PWM-B exceeds this allowable value, the signal generator 3,
It can be determined that an abnormality has occurred in the circuit constituting No. 4. Therefore, PWM-A and PWM-B due to variation of parts at the time of manufacturing
Is set as the delay time T of the delay circuits 53 and 54 of the comparison circuit unit 5.

The operation of the transmitter 1 configured as described above when the pulse width of PWM-B is longer than the pulse width of PWM-A will be described with reference to the waveform diagram of FIG. The signal generators 3 and 4 generate necessary PWM waves in accordance with a control command from the processor 2, amplify the PWM-A generated by the signal generator 3 by the switching amplifier 6, and then pass through the low-pass filter 7. The signal is sent to the track circuit 8 as a transmission signal and also sent to the comparison circuit unit 5. The PWM-B generated by the signal generator 4 is sent to the comparator 5.
The D flip-flop 51 of the comparison circuit unit 5 stores the low-level D input input from the delay circuit 54 at the moment of the falling timing of the PWM-A as the Q output.
It is held until the next fall of WM-A. D
The output of the delay circuit 53 falls when the delay time T has elapsed since the fall of the Q output of the flip-flop 51. If PWM-B falls before the delay time T elapses, the Q output of the D flip-flop 52 rises.
When the delay time T elapses after the Q output of the D flip-flop 52 rises, the output of the delay circuit 54 rises. In this way, if the fall timing of PWM-B is within the delay time T from the fall timing of PWM-A, the D inputs of the D flip-flops 51 and 52 are different, and the rise of PWM-A and the rise of PWM-B are different. At the falling timing, the Q outputs of the D flip-flops 51 and 52 are inverted. Therefore, the comparison signal output from the D flip-flop 52 is an alternating signal in which a high level and a low level are alternately output. However, when the fall timing of the PWM-B is not within the delay time T from the fall timing of the PWM-A, that is, when the PWM-A and the PWM-
When the difference between the pulse widths of B exceeds the allowable value, the D inputs of the D flip-flops 51 and 52 become the same, and thereafter the Q outputs of the D flip-flops 51 and 52 become the same and the output from the D flip-flop 52 becomes the same. The comparison signal is a DC signal fixed to either a high level or a low level. In this manner, the comparison signal output from the comparison circuit unit 5 is input to the processing device 2, and the processing device 2 determines whether the input comparison signal is an alternating signal or a DC signal, and thereby the signal generation unit 3 and the signal generation unit 4 can determine whether the same operation is performed, that is, whether a normal transmission signal is transmitted.

Since the comparison circuit unit 5 compares the PWM-A and the PWM-B before the power is amplified by the switching amplifier 6, it is possible to accurately judge the suitability of the transmission signal without being affected by the noise from the track. be able to.

Although the above embodiment has been described with reference to a transmitter of an ATC device, the present invention can be similarly applied to a transmitter of another railway security device or the like.

[0014]

As described above, according to the present invention, the PWM wave output from the two signal generators depends on whether the difference between the pulse widths of the PWM waves generated by the two signal generators exceeds an allowable value. Since the match or mismatch is determined, it is possible to check the suitability of the transmission signal without providing the transmitter with a reception function, and the transmitter can be downsized.
It is possible to reduce the price of a transmitter with a check function.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a comparison circuit unit of the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a signal generation unit.

FIG. 4 is a waveform diagram showing a difference between pulse widths of PWM waves generated by two signal generation units.

FIG. 5 is a waveform diagram showing creation of a PWM wave.

FIG. 6 is a waveform chart showing an operation of the signal generator.

FIG. 7 is a block diagram showing a configuration of a conventional transmitter.

[Description of Signs] 1 Transmitter 2 Processing device 3 Signal generator 4 Signal generator 5 Comparison circuit 6 Switching amplifier 7 Low-pass filter 8 Track circuit 51 D flip-flop 52 D flip-flop 53 Delay circuit 54 Delay circuit

(56) References JP-A-6-87448 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) B61L 1/00-23/32

Claims (1)

(57) [Claims] 1. A signal processing unit comprising a signal generator and a comparator circuit of two systems, each signal generator generates and outputs a PWM wave according to a control command from the processor, and The PWM signal output from the generator is compared to generate a comparison signal indicating whether the signals match or not, and outputs the comparison signal to the processing device. Two D flip-flops and two delay circuits are provided. A delay time is set in each of the two delay circuits in accordance with the allowable value of the difference between the pulse widths of the PWM waves of the two signal generators. One of the delay circuits is connected to the clock input terminal of the first D flip-flop. The PWM wave output from the signal generator is input, the output of the second delay circuit is input to the D input terminal, the Q output is input to the first delay circuit, and the clock input of the second D flip-flop is input. At the end is the PWM output from the other signal generator There is input, D
The output of the first delay circuit is input to the input terminal, the Q output is input to the second delay circuit and output to the processing device as a comparison signal, and the processing device determines whether the input comparison signal is an alternating signal or a DC signal. And determining whether the PWM waves output from the two signal generators match or not.