JP2885168B2 - Data reply method in multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system including a plurality of processors each connected to a cache memory of a write-back system, and a shared memory shared by the processors. The present invention relates to a data reply method in a multiprocessor system that can shorten a read time when reading data from a memory.

[0002]

2. Description of the Related Art In a multiprocessor system having a plurality of processors each connected to a cache memory of a write-back system and a shared memory shared by each processor, a certain processor receives data from a shared memory. When data reading is requested, the following is conventionally performed in order to maintain consistency between cache memories or between a cache memory and a shared memory.

When one processor requests to read data from the shared memory, another processor
It is determined whether or not a block containing data requested by the requesting processor and a rewritten block is stored in the cache memory of the own processor. If it is determined that the block is stored, an owner signal indicating this is output at a predetermined timing, and a bus acquisition request is made to acquire a bus. To the processor. If it is determined that the data is not stored, an owner signal indicating that is stored is output at a predetermined timing. On the other hand, the shared memory refers to the owner signal at the timing when the owner signal is sufficiently determined, and determines whether or not it indicates that there is no rewritten processor. If it is determined that the owner signal indicates that the rewritten processor does not exist, a bus acquisition request is made and the bus is acquired, and the block containing the requested data is used as reply data as the request source. To the processor.

[0004]

As described above, conventionally, it is determined whether or not there is a processor that has rewritten data based on the owner signal after the timing at which the owner signal is sufficiently determined. However, when the result of the determination indicates that there is a processor that has rewritten the data, the data reply operation is started, so that there is a problem that data reading from the shared memory is delayed. In particular, the timing for outputting a bus acquisition request is fixed such that a bus acquisition request for performing data reply can be output only once every several clocks, and the timing for waiting for the owner signal to be sufficiently determined is waited. In a multiprocessor system in which the timing at which a bus acquisition request can be output just passes, the delay becomes noticeable.

Therefore, an object of the present invention is to reduce the read time when reading data from a shared memory.

[0006]

According to the present invention, there is provided a multi-processor comprising a plurality of processors each connected to a write-back cache memory, and a shared memory shared by the processors. In the processor system, each of the processors is a block including data requested by the requesting processor in a cache memory of the own processor when another processor requests reading of data from the shared memory. In addition, it is determined whether or not the rewritten block is stored, and an owner signal indicating the determination result is output at a predetermined timing, and the determination result stores the rewritten block. Indicates that the data requested by the requesting processor at a predetermined timing. The shared memory outputs the block including the data, and the processor that has rewritten the data with the owner signal with reference to the owner signal at a timing one clock before the timing when the owner signal is sufficiently determined is output. When it is determined that it does not exist, the data reply operation is started immediately, and thereafter, at a timing when the owner signal is sufficiently determined, the owner signal refers to the owner signal to rewrite data. If it is determined that the execution of the processor is present, stop the data reply operation,
The requesting processor was instructed to validate the block output from the processor, and the requesting processor was not instructed by the shared memory to validate the block from the processor. In this case, the block from the shared memory is stored in the cache memory of the own processor, and when instructed, the block from another processor is stored in the cache memory of the own processor.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a multiprocessor system to which the present invention is applied. The processors 1 and 2 and the shared memory 3 are connected via a bus 4, and the processors 1 and 2 are connected to cache memories 5 and 6 of a write-back system, respectively.

The bus 4 comprises an address bus 401, a data bus 402, an owner signal line 403, and a data cancel signal line 404. Owner signal line 4
03 is connected to each of the processors 1 and 2 by wired OR connection.

The cache memories 5 and 6 have tag sections 51 and 61, respectively. The tag sections 51 and 61 store information indicating whether or not each block stored in the cache memories 5 and 6 has been rewritten.

FIG. 2 is a block diagram showing components required when the processor 1 operates as a processor that requests data reading from the shared memory 3 among the components of the processor 1. , Bus state determination unit 102 and address request unit 103
, Address output register 104, selector 105
, An interface flip-flop (interface FF) 106, a coupling unit 107, and a bus arbiter 108
And a data input register 109.

FIG. 3 is a block diagram showing components required when the processor 2 operates as a processor other than the requesting processor among the components of the processor 2. Part 202
, An address input register 203, an interface flip-flop 204, a data request unit 205
, An interface flip-flop 206, a combining unit 207, a bus arbiter 208, a data output register 209, and a combining unit 210.

FIG. 4 is a block diagram showing an example of the configuration of the shared memory 3. The memory unit 301, the control unit 302, the flip-flop 303, and the cancel signal generation unit 304
A bus state determination unit 305, a data request unit 306, an interface flip-flop 307,
The coupling unit 308 and the interface flip-flop 30
9, the address input register 310, and the bus arbiter 3
11, a data output register 312, and a coupling unit 313. 2 to 4, the same reference numerals as those in FIG. 1 indicate the same parts.

FIG. 5 is a timing chart showing the operation of this embodiment. The operation of this embodiment will be described below with reference to the drawings. As shown in the figure, in the multiprocessor system of this embodiment, four clocks from state I to state IV are repeated as one cycle, and an address bus acquisition request ARQ for acquiring an address bus and a data bus Data bus acquisition request DRQ of state I
Output is possible only with. The address output after acquiring the address bus can be performed only in state III.

In FIG. 2, data required by the processor 1 is not stored in the cache memory 5,
It is assumed that a mishit occurs in the processor 1. When a mishit occurs, the control unit 101 in the processor 1
Sets the address ADR of the data in the address output register 104 and the address request unit 1
03 is instructed to output an address bus acquisition request. In response to this instruction, the address request unit 103 outputs an address bus acquisition request ARQ.

Thereafter, the control unit 101 controls the selector 105 to select the address request unit 103 at the timing when the bus state determination unit 102 determines that the state IV (the first cycle) has been reached. The state I (2)
At the timing at which it is determined that the cycle 1) has been reached, the bit assigned to the processor 1 in the address bus 401 to output the address bus acquisition request ARQ by controlling the coupling unit 107 and the interface flip-flop 106 And the corresponding bits are combined. For example, if upper bits of the address bus 401 are allocated to the processor 1, the upper bits of the address bus 401 and the upper bits of the interface flip-flop 106 are combined. Thus, the address bus acquisition request ARQ output from the selector 105 in the state IV in the first cycle is delayed by one clock in the interface flip-flop 106 and output to the address bus 401 in the state I in the second cycle.

The bus arbiter 108 in the processor 1
At the timing when the bus state determination unit 102 determines that the state I (second cycle) has been reached, the contents of the address bus 401 are read, and it is determined whether or not the processor 1 can acquire the address bus 401. Is notified to the control unit 101.

When notified that the address bus 401 can be acquired, the control unit 101 controls the selector 105 to select the address output register 104 in state II (second cycle), and further shifts to state III. In this case, the control unit 107 controls the connection unit 107 to connect the interface flip-flop 106 to the address bus 401. As a result, the address ADR output from the selector 105 in the state II in the second cycle is delayed by one clock in the interface flip-flop 106 and output to the address bus 401 in the state III in the second cycle.

The address ADR output to the address bus 401 in state III of the second cycle is the next state.
The data is captured by the interface flip-flops 204 and 309 in the processor 2 and the shared memory 3 shown in FIGS. 3 and 4 in IV, and is set in the address input registers 203 and 310 in state I in the third cycle.

When the address ADR is set in the address input register 203, the control unit 201 in the processor 2 immediately executes a block including the data indicated by the address ADR based on the contents of the tag unit 61 in the cache memory 6. It is determined whether or not the rewritten block exists in the cache memory 6. If it is determined that the block does not exist, an owner signal having a logical value “0” is output to the owner signal line 403. If it is determined that the owner signal exists, the owner signal of the logical value "1" is output to the owner signal line 4.
03 is output.

Further, when it is determined that the above-mentioned block exists in the cache memory 6, the control unit 201
The above-described block is read from the cache memory 6, set in the data output register 209, and in the state IV of the fourth cycle, the data request unit 205 is instructed to output a data bus acquisition request. The interface flip-flop 206 is coupled to the address bus 401 by controlling the coupling unit 207 in the step (a). As a result, the data bus acquisition request DRQ is output to the address bus 401 in the state I of the fifth cycle. The bus arbiter 208 in the processor 2 captures the contents of the address bus 401 in state I of the fifth cycle, determines whether the processor 2 can acquire the data bus 402, and notifies the control unit 201 of the determination result. Upon receiving the notification that the data bus 402 can be acquired, the control unit 201 controls the coupling unit 210 to couple the data output register 209 and the data bus 402 in the sixth cycle. As a result, in the sixth cycle, a block containing data requested by the requesting processor 1 is output from the processor 2 to the data bus 402.

Here, even if the timing at which the owner signal output from the processor 2 is sufficiently determined is after the state IV in the third cycle, in most cases, the correct value is obtained in the state III one clock before. Is displayed. In other words, the timing at which the owner signal is sufficiently determined is the timing at which the maximum values of the read time of the cache memory and other circuit delay times are accumulated, so that unless a bad environment such as an extremely high temperature or an electromagnetic field overlaps, In many cases, a correct value is displayed one clock before.

Therefore, in the shared memory 3 shown in FIG. 4, the logic value of the owner signal is fetched into the flip-flop 303 in state III of the third cycle one clock before the timing at which the owner signal is sufficiently determined, and the flip-flop 303 If the logical value of the owner signal fetched in step (1) is "0", the data reply operation is started immediately.

Now, for example, the logical value of the owner signal fetched into the flip-flop 303 in state III of the third cycle one clock before the timing at which the owner signal is sufficiently determined is also determined by the three cycles at which the owner signal is sufficiently determined. Assuming that the logical value of the owner signal in the eye state IV is also "0", the following operation is performed.

The control unit 302 in the shared memory 3 outputs the data bus acquisition request to the data request unit 306 in the state IV of the third cycle if the owner signal taken into the flip-flop 303 is “0”. Instruct
In state I of the next fourth cycle, the bits assigned to control the coupling unit 308 to output the data bus acquisition request DRQ by the processor 2 on the address bus 401 correspond to the above bits of the interface flip-flop 307. Combine with the bit to be done. As a result, the data bus acquisition request DRQ output from the data request unit 306 in the third cycle state IV is delayed by one clock in the interface flip-flop 307 and output to the address bus 401 in the fourth cycle state I. .

The cancel signal generator 304 compares the logical value of the owner signal at that time with the logical value of the owner signal one clock before, which is taken into the flip-flop 303, in state IV of the third cycle. If they do not match, the data cancel signal is set to logic "1".
In the case of this example, since they match, the data cancel signal does not become logic "1".

The bus arbiter 311 outputs the address bus 401 at the timing when the bus state determination unit 305 determines that the state has entered the state I (fourth cycle).
And determines whether or not the shared memory 3 can acquire the data bus 402, and notifies the control unit 302 of the determination result.

Upon receiving the notification that the data bus 402 can be acquired, the control unit 302
The block including the data indicated by the address stored in the address 0 is read from the memory unit 301 and set in the data output register 312. Further, in the state I of the fifth cycle, the coupling unit 313 is controlled and the data output register 312 The data bus 402 is connected. As a result, a block containing the data requested to be read by the requesting processor 1 is output to the data bus 402 in the fifth cycle.

The control unit 101 in the requesting processor 1
When the data bus acquisition request is output in state I of the fourth cycle, the data input register 109 is controlled in the fifth cycle, and the data (block) on the data bus 402 is transferred to the data input register 109. Let it be captured. Thereafter, the control unit 101 sets the data input register 10
9 is stored in the cache memory 5.

As described above, the logical value of the owner signal fetched into the flip-flop 303 of the shared memory 3 in the state III of the third cycle one clock before the timing at which the owner signal is sufficiently determined is sufficient for the owner signal. If the logical value of the owner signal in state IV of the third cycle is also "0", the data bus acquisition request DRQ is output after waiting for the timing when the owner signal is sufficiently determined. Then, the timing at which the data bus acquisition request DRQ is output to the data bus 402 is
The state I becomes the fifth cycle, and the data reading is delayed by four clocks as compared with the above case.

Next, state III in the third cycle one clock before the timing when the owner signal is sufficiently determined.
The logical value of the owner signal taken into the flip-flop 303 is "0", and the logical value of the owner signal is "1" in the third cycle of state IV where the owner signal is sufficiently determined.
The operation in the case of "" will be described.

In this case, a data acquisition request DRQ is output to the address bus 401 in the state I of the fourth cycle in the same manner as described above. However, in this case, the logical value of the owner signal in state III in the third cycle taken into the flip-flop 303 is “0”, and the logical value of the owner signal in state IV in the third cycle is “0”. Since it is “1”, the cancel signal generation unit 304
Sets the data cancel signal to "1" in state II of the fourth cycle.

When the data cancel signal becomes "1", the control section 302 in the shared memory 3 stops the data reply operation.

The control unit 1 in the requesting processor 1
In the case of 01, when the data cancel signal becomes "1", the operation of taking data into the data input register 109 is stopped. Then, when the data bus acquisition request DRQ is output in state I of the fifth cycle, the block output from the processor 2 in the sixth cycle is fetched into the data input register 109, and the fetched block is cached. It is stored in the memory 5.

Next, state III in the third cycle one clock before the timing when the owner signal is sufficiently determined.
As for the logical value of the owner signal taken into the flip-flop 303 of the shared memory 3, the owner signal is also sufficiently determined.
The operation in the case where the logical values of the owner signal are both "1" in the state IV in the cycle will be described.

In this case, the control unit 302 in the shared memory 3
In this case, the data reply operation is not performed, the data reply operation is performed in the processor 2, and the requesting processor 1 stores the block sent from the processor 2 in the cache memory 5.

Next, the third cycle of state III, one clock before the timing at which the owner signal is sufficiently determined.
The logical value of the owner signal taken into the flip-flop 303 is "1", and the logical value of the owner signal is "0" in the third cycle of state IV in which the owner signal is sufficiently determined.
The operation in the case of "" will be described.

The cancel signal generator 3 in the shared memory 3
04 is 3 which is taken in the flip-flop 303
Since the logical value of the owner signal in state III in the third cycle is "1" and the logical value of the owner signal in state IV in the third cycle is "0", the data cancel signal is output in the fourth cycle. Set to "1" in state II.

The control unit 302 controls the state of the fourth cycle.
When the data cancel signal becomes "1" in II, the value set in the flip-flop 303 is "1". DRQ output is instructed, and in state I of the next fifth cycle,
08 to connect the address bus 401 with the interface flip-flop 307. This gives 5
In state I of the cycle, a data bus acquisition request DRQ is output to data bus 402. After that, the control unit 302
Outputs a block containing the data requested by the requesting processor 1 to the data bus 402 in the same manner as described above.

[0040]

As described above, the present invention recognizes that there is no processor that rewrites data with reference to the owner signal at a timing one clock before the timing at which the owner signal is sufficiently determined. In this case, since the data reply operation is started immediately, the read time for reading data from the shared memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a multiprocessor system to which the present invention is applied.

FIG. 2 is a block diagram showing components required when operating as a requesting processor.

FIG. 3 is a block diagram showing components required when operating as a processor other than the requesting processor.

FIG. 4 is a block diagram illustrating a configuration example of a shared memory 3;

FIG. 5 is a timing chart showing the operation of the embodiment.

[Explanation of symbols]

 1, 2, processor 3, shared memory 4, bus 5, 6, cache memory

Claims (3)

(57) [Claims] 1. In a multiprocessor system including a plurality of processors each connected to a write-back cache memory and a shared memory shared by each processor, each of the processors is connected to another processor. Requests the reading of data from the shared memory, determines whether the cache memory of its own processor contains a block containing data requested by the requesting processor and a rewritten block. And outputs an owner signal indicating the determination result at a predetermined timing. If the determination result indicates that the rewritten block is stored, the owner signal is output at a predetermined timing. The shared memory outputs a block including data requested by the requesting processor, If it is determined at a timing one clock before the timing at which the owner signal is sufficiently determined that the owner signal indicates that there is no processor that has rewritten data by referring to the owner signal, Immediately starts a data reply operation, and then determines at a timing when the owner signal is sufficiently determined that the owner signal indicates that there is a processor that has rewritten data by referring to the owner signal. In this case, the data reply operation is stopped, and the requesting processor is instructed to validate the block output from the processor. If not instructed to enable the block of Storing the lock in the cache memory of its own processor, it indicated in the data reply method in a multi-processor system, characterized by storing the blocks from the other processor in the cache memory of its own processor if. 2. The shared memory according to claim 1, wherein a processor in which the owner signal rewrites data with reference to the owner signal at a timing one clock before a timing at which the owner signal is sufficiently determined exists. At the timing when the owner signal is sufficiently determined, and then determines that the owner signal indicates that there is no processor that has rewritten data by referring to the owner signal. 2. The data reply method in a multiprocessor system according to claim 1, wherein a data reply operation is performed when the data reply is performed. 3. The shared memory includes a processor in which the owner signal rewrites data with reference to the owner signal at a timing one clock before a timing at which the owner signal is sufficiently determined. At the timing when the owner signal is sufficiently determined, and then determines that the owner signal indicates that there is a processor that has rewritten data by referring to the owner signal. 3. The data reply method in a multiprocessor system according to claim 2, wherein the data reply operation is not performed when the data reply is performed.