JP2883785B2 - Optical scanning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical scanning device used as an exposure device in a copying machine, a laser printer, or the like.

[0002]

2. Description of the Related Art For example, an optical scanning device used for a laser printer deflects and scans a laser beam to irradiate a photosensitive surface. In general, correction of each optical aberration such as scanning line curvature, fθ correction, and surface tilt is performed purely optically, and a structure in which a plurality of fθ lenses and a surface tilt correction cylindrical lens are combined is known. Also, to simplify the optical system,
There is also known a device that performs optical aberration correction by using a combination of an elliptic cylindrical polygon mirror and a double-sided aspherical correction lens without using an fθ lens.

Among the optical aberrations, fθ error (error that the interval between pixels is not constant because the scanning speed of the laser beam on the scanning surface changes depending on the scanning position when the laser beam is scanned at a constant angular velocity) There is also known a device that performs electrical correction and optically corrects other aberrations.

For example, in Japanese Unexamined Patent Publication No. 2-131212, as shown in FIG. 10, a divergent laser beam from a semiconductor laser 1 is corrected into a convergent or parallel light beam by a collimator lens 2, and the corrected laser beam is cylindrically reflected. Lens 3
Irradiates the polygon mirror 4 via the torsion mirror 5 and deflects and scans the light. The deflected light is reflected by the return mirrors 6 and 7 via the toroidal lens 5 and condensed on the photosensitive drum 8 to scan the main scanning line 9 In this case, since the scanning speed is different from the center to the end in the main scanning line 9, that is, the scanning speed at the end is higher than that at the center, the exposure may be performed at an isochronous timing. The dot pitch varies.

Therefore, the entire area of the main scanning line 9 is bisected at the center, and half of each area is divided into a to a as shown in FIG.
g is divided into 7 blocks, and in each of the blocks a to g, 10 pulses of the reference clock, which is 10 times the print clock, correspond to 1 pulse.
By changing the ratio of the portion forming a dot and the portion forming one dot with 9 pulses, the dot printing timing is advanced as it approaches the end, so that the printing interval is macroscopically uniform from the center to the end. So that the fθ error is electrically corrected.

[0006] The fθ error correction pulse width data for determining the dot printing timing is stored in the ROM, the fθ error correction pulse width data is read from the ROM for each scan, and a character control clock is generated at a timing based on the data. (Pixel clock) to turn on the laser light,
It is turned off.

[0007]

However, this publication does not take any measures against the resolution.
It cannot be applied to an apparatus that can use a plurality of resolutions. Furthermore, it could not cope with a continuous change in resolution required for a copying machine.

Accordingly, the present invention provides an optical scanning device which electrically corrects an fθ error, in which the generation timing of a pixel clock for the fθ error correction can be controlled according to any resolution, and the versatility can be improved. I do.

[0009]

The invention corresponding to claim 1 is:
In an optical scanning device that controls on / off of a laser beam based on recording information at a timing of a pixel clock generated from a pixel clock generating unit and scans a photosensitive surface with the laser beam to dot-record information, the pixel clock generating unit A reference clock generating means for generating a reference clock serving as a source of a pixel clock; a storage means for storing at least a numerical value T0 corresponding to a pixel clock cycle and a numerical value T1 corresponding to a time derivative of the numerical value T0; T1 = T1 + 2A- using a constant A corresponding to the pixel clock cycle at the center of the scanning width of the above and the numerical values T0 and T1 stored in the storage means.
4T0 and T0 = T0 + T1, calculating means for updating the numerical values T0, T1 of the storing means based on the calculation result, and using the numerical value T0 of the storing means as a dividing ratio, and using the dividing ratio as a reference clock generating means. And a variable frequency dividing means for generating a pixel clock by dividing the frequency of the reference clock.

According to a second aspect of the present invention, in the first aspect, the reciprocal of the beam deflection angle per pixel is represented by s.
h, the numerical values T0 and T1 are converted to an integer t representing an integer part.
Using 0, t1 and integers s0, s1 indicating the fractional part, T
0 = t0 + s0 / sh and T1 = t1 + s1 / sh, and the storage means is an integer t instead of the numerical values T0 and T1.
0, t1, s0, s1 are stored, and the calculating means is a numerical value T0,
Integers t0, t1, s0, and s1 are updated in place of T1, and accumulating means for accumulating the integer s0 every time the frequency division ratio (t0 + s0 / sh) is updated is provided.
If it becomes larger than 2, t0 is incremented by 1 and sh is subtracted from the accumulated value. If the accumulated value becomes smaller than sh / 2, t0 is subtracted from -2.
Then, 1 is added to the accumulated value.

[0011]

According to the first aspect of the present invention, T1 = T1 using the constant A corresponding to the pixel clock cycle at the center of the scanning width of the laser beam and the numerical values T0 and T1 stored in the storage means.
+ 2A-4T0 and T0 = T0 + T1 are calculated, and a pixel clock is generated by dividing the reference clock from the reference clock generating means using the calculated numerical value T0 as a division ratio. Further, the numerical values T0 and T1 of the storage means are expressed as T1 = T1 + 2A-4.
Update based on the result of T0 and T0 = T0 + T1.
This is performed for each pixel to be scanned to correct the fθ error.

In the invention corresponding to claim 2, when the reciprocal of the beam deflection angle per pixel is sh, the numerical values T0 and T1 are represented by integers t0 and t1 representing integer parts and an integer s0 representing decimal parts. , S1, T0 = t0 + s0 /
sh and the relational expression of T1 = t1 + s1 / sh, where (t
(0 + s0 / sh) is used as the dividing ratio to divide the reference clock from the reference clock generating means to generate a pixel clock. Further, the integers t0, t1, s0, and s1 of the storage means are represented by T
Update based on the results of 1 = T1 + 2A-4T0 and T0 = T0 + T1. Further, integers t0, t1, s0, s1
The integer s0 is accumulated every time the frequency division ratio (t0 + s0 / sh) is updated by the update of .t0. When the accumulated value becomes larger than sh / 2, t0 is incremented by 1, and sh is subtracted from the accumulated value. Is smaller than sh / 2, t0 is decremented by 1, and sh is added to the accumulated value. This corrects the error caused by the fractional part being truncated in each calculation.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 show the structure of an optical scanning device main body. This device main body converts a laser beam from a semiconductor laser oscillator 11 into a divergent light beam with a converging lens 12 and then forms a circular beam with a slit 13. After shaping into a beam, reflecting the beam on the reflecting mirror 14 and changing the optical path at right angles,
The two 45 ° reflecting surfaces of the right-angle prism 16 arranged on the rotation axis 15b of the rotor 15a of the scanner motor 15 are irradiated. That is, the right angle prism 16 is
Two surfaces orthogonal to each other are defined as reflection surfaces. Then, the center of the rectangular surface sandwiched between the two reflecting surfaces is arranged so as to match the rotation axis 15b of the scanner motor 15, and the light reflected from the reflection mirror 14 is reflected by the rotation axis 15 of the scanner motor 15.
The light is incident on the position about several mm away from b in parallel with the rotation axis 15b.

The scanner motor 15 has a magnet 15c integrally attached to a rotor 15a. The rotating shaft 1
5b is rotatably mounted on the stator member 15d via a ball bearing 15e. The stator member 15
A circuit board 15g is fixed to d via a spacer 15f, and a coil 15h is mounted on the back surface of a portion of the circuit board 15g facing the magnet 15c.

The reflected light from the reflecting mirror 14 is reflected by the reflecting surface of a right-angle prism 16 that is driven to rotate by the scanner motor 15 and is converted into deflected light that is deflected and scanned in a plane direction perpendicular to the rotation axis 15b of the scanner motor 15. After that, the light enters the meniscus lens 17 having a smaller radius of curvature of the exit surface than the entrance surface and convex outward, and is located at a distance L from the deflection point, that is, the reflection point of the right-angle prism 16 as shown in FIG. The image is formed on the photosensitive surface 21 of the photosensitive drum located at the position shown in FIG.

The semiconductor laser oscillator 11, the converging lens 12, and the slit 13 are integrated as a light emitting unit 18. The meniscus lens 17 is incorporated in a case 19. Then, the light emitting unit 18 is fitted into the upper rear of a housing 20 surrounding the entire device made of, for example, a synthetic resin, and the reflection mirror 14 is embedded in an upper front inclined portion of the housing 20. 20 in the front opening.

The stator member 1 of the scanner motor 15
The flange portion of the housing 20 is screwed to the periphery of 5d.

If the deflection angle of the light beam from the scanning center, that is, the deflection angle of the light beam, is θ, and the distance from the scanning center to the image point of the light beam at this time is h (θ), h (θ ) = Ltan θ (1) By differentiating this equation (1), the scanning speed v (θ)
Can be requested. That is,

(Equation 1) Becomes Where dθ / dt is the deflection angular velocity of the light beam,
When the scanner motor 15 rotates at a constant speed, it becomes a constant. As is apparent from the above equation (2), the scanning speed v (θ)
Is small near θ = 0, that is, near the scanning center of the light beam, and increases as the distance from the scanning center increases.

If the period of the pixel clock used to control the on / off timing of the laser light emitted from the semiconductor laser oscillator 11 is T (θ), the width P of one pixel is P = T ( θ) · v (θ) (3) Here, when T (θ) is fixed, the scanning speed v (θ) changes as in the above equation (2), so that P changes with θ. This is the fθ error.

In order to keep the width P of one pixel constant, ω = dθ
/ Dt,

(Equation 2) As described above, the period T (θ) of the pixel clock may be changed according to the deflection angle θ of the light beam.

The graph of FIG. 4 shows the scanning speed v (θ) with respect to the deflection angle θ of the light beam, and the graph of FIG. 5 shows the change of the pixel clock cycle T (θ) with respect to the deflection angle θ of the light beam. .

Since the above equation (4) includes a trigonometric function,
You cannot do calculations easily. Therefore, a calculation equivalent to the above equation (4) was realized using only addition and subtraction of integers. That is, if the calculation can be realized only by addition and subtraction of integers, the calculation can be easily performed by the arithmetic means, and real-time control can be performed.

For simplicity, it is assumed that a = P / Lω. Above (4)
Differentiating the equation twice with θ gives

(Equation 3) Becomes Here, since acos ² θ = T (θ), the following equation holds.

[0025]

(Equation 4) The deflection angle of the light beam with respect to one pixel at the center of scanning is Δ
Assuming that the deflection angle of the light beam with respect to θ and the n-th pixel is represented by θ _n , T (θ) and dT (θ) / dt are tailored, and if the second and subsequent terms are omitted, then

(Equation 5) Becomes Also, from the above equation (7),

(Equation 6) Approximation.

As described above, T (θ _n ) and dT (θ _n )
Given / dt, T (θ _n ) for any θ _n can be calculated using the above recurrence formulas (7) to (9).

Next, a method of performing an integer operation on the above equations (7) to (9) will be described.

Now, assuming three integers sh, t0 and s0, T (θ) is expressed as T (θ) = tT (11) using the period t of the reference clock having a higher frequency than the pixel clock. That is, T (θ) is T times the period t. Further, T = t0 + s0 / sh (12) However, | s0 | <sh / 2. here,
t0 corresponds to the integer part of T, and s0 / sh corresponds to the decimal part. s0
Changes, so that s0 always represents a decimal part,
If s0 becomes larger than sh / 2, t0 is incremented by 1, and s0 is reduced by sh. If s0 is smaller than -sh / 2, t0 is decremented by 1, and s0 is increased by sh.

Similarly, dT (θ _n ) / dt = t 1 + s 1 / sh (13) using two integers t 1, s 1 and sh. However, | s1 | <sh / 2, and if s1 changes and becomes larger than sh / 2, t1 is incremented by one, and -s
If it is smaller than h / 2, t1 is decremented by one.

By setting sh = 1 / Δθ, the above recurrence formulas (8) to (10) can be easily calculated by the following procedure.

That is, a new integer t2 is prepared, and the recurrence equation (10) can be realized by calculating 2A−4 × t0 to be t2, and the recurrence equation (9) can be calculated by s1 + t2. And a new s1 can be realized. Further, the recurrence equation (8) is expressed as s0 +
This can be realized by calculating t1 to obtain a new s0. Note that A is T corresponding to θ = 0.

In this calculation, the range where s0 and s1 are determined, that is, | s0 | <sh / 2, | s1 | <sh /
In the case of 2, t0 and t1 are changed. Also, 2A-4x
Multiplication at t0 can be easily realized by addition or shift operation.

The period T (θ) of the pixel clock to be obtained is determined by the period t (θ) of the reference clock by the time t0 obtained by the above operation.
You can see how many times.

When T (θ) is approximated to be t0 (integer) times t by this method, the fractional part s0 / sh is rounded down, and the error is accumulated by repeating the calculation.

To prevent this, a new integer sg is prepared, and the fractional part s0 to be discarded is added and accumulated. In other words, this can be realized by adding a calculation process of calculating sg + s0 to a new sg in addition to the above-described integer calculation. Then, if sg becomes larger than sh / 2, t0 is set to T (θ) times (t0 + 1) times t, and sg is set to s.
Reduce by h. If sg becomes smaller than -sh / 2, T (.theta.) Is set to (t0 -1) times t, and sg is increased by sh.

By doing so, accumulation of errors due to truncation of the decimal part can be prevented. In order to realize the above integer arithmetic processing by a program, a pixel clock generation processing based on a flowchart shown in FIG. 6 may be performed.

That is, first, at step S1, an integer t0
, S0, t1, s1, 2A, sh
Subsequently, in step S2, 2A-4.times.t0 is calculated to obtain t2.
And t2 is added to s1.

Then, it is checked in step S3 whether s1> sh / 2 or not. If s1> sh / 2 is not satisfied, then in step S4 it is checked whether s1 <-sh / 2.
Unless s1 <-sh / 2, t1 is added to s0 in step S5.
Is added.

If s1> sh / 2, step S6
Then, 1 is added to t1 and sh is subtracted from s1 and then the process of step S5 is performed. If s1 <-sh / 2, 1 is subtracted from t1 in step S7, and sh is added to s1, and then the process of step S5 is performed.

Subsequently, it is checked in step S8 whether or not s0> sh / 2. If s0> sh / 2 is not satisfied, then in step S9 it is checked whether or not s0 <-sh / 2.
Unless s0 <-sh / 2, s0 is added to sg in step S10.

If s0> sh / 2, step S1
At step 1, 1 is added to t0, and sh is subtracted from s0, and then the process of step S10 is performed. If s0 <-sh / 2, 1 is subtracted from t0 in step S12, and sh is added to s0, and then the process of step S10 is performed.

Subsequently, in step S13, sg> sh / 2
It is checked whether or not sg> sh / 2 if sg <-sh / 2. If sg <-sh / 2, then if not sg <-sh / 2, t is determined in step S15.
0 is the division ratio.

If sg> sh / 2, step S1
In step 6, 1 is added to t0 to obtain a division ratio, and sg to s
h is subtracted. If sg <-sh / 2, 1 is subtracted from t0 in step S17 to obtain a frequency division ratio, and sg
And sh.

FIG. 7 is a circuit block diagram of an optical scanning device that performs a pixel clock generation process by such an integer operation. Image recording information from a host computer (not shown) is transmitted to an I / O device.
/ F (interface) 31 and receives the image
Stored in 2. The image recording information stored in the image memory 32 is read out to a parallel / serial conversion circuit 33, and the conversion circuit 33 converts parallel data into serial data in synchronization with a pixel clock generated from a pixel clock generation circuit 34, and performs optical scanning. The signal is output to the semiconductor laser oscillator 11 of the device main body 35.

FIG. 8 shows a specific configuration of the pixel clock generation circuit 34, which has a circuit configuration for realizing the pixel clock generation processing shown in FIG.

That is, the pixel clock generation circuit 34
Are the integers t0, s0, t1, s1, sg, 2A, sh,
A register group 41 as storage means for storing 1, 0 and a frequency division ratio, first and second multiplexers 42 and 43, demultiplexer 44, first and second comparators 45 and 46, adder 47, code Converter 48, each of the multiplexers 4
2, 43, a decoder 49 for outputting a selection signal to the demultiplexer 44 and the code converter 48,
The control circuit 50 which takes in the output of the decoder 46 and controls the decoder 49, the reference clock generation circuit 51 which generates the reference clock, and the frequency division ratio stored in the register group 41 are set for each generation of the pixel clock. A variable frequency divider 52 divides the reference clock from the clock generation circuit 51 based on the set division ratio and outputs a desired pixel clock.

The register group 41 is composed of, for example, a 12-bit D-type flip-flop, and is externally provided with integers t0, s0, t1, s1, 2A, s by an initialization circuit (not shown).
The initial value of h is set.

The first comparator 45 compares the result of the addition by the adder 47 with a constant sh / 2. The second comparator 46 calculates an addition result of the adder 47 and a constant −sh /
Compare the size of the two.

Next, the operation of this embodiment will be described with reference to Table 1.

First, in the state "0", the register group 41
Are set to the initial values of the integers t0, s0, t1, s1, 2A, and sh. (Step S1) This state “0” is executed only once at the beginning when the light beam scans the photosensitive surface 21 once. Then, the state shifts to state “1”.

In the next state "1", a process of calculating 2A-4.times.t0 and setting it to t2 is performed. (Step 2) That is, in the state “1”, 2A is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and
Further, t0 is converted to the value of the second multiplexer 43 and the code converter 4.
8 to the adder 47. Where 4 × t0
Is realized by shifting the connection between t0 of the register group 41 and the second multiplexer 43 by 2 bits. The minus sign is inverted by the sign converter 48 and added.

In this way, the adder 47 executes the operation of 2A-4 × t0, and substitutes the result into t2 of the register group 41 via the demultiplexer 44. And each comparator 4
The state transits to the state "2" irrespective of the results of the steps 5 and 46.

In state "2", a process is performed to calculate s1 + t2 to make it a new s1. (Step 2) That is, in the state “2”, s1 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and
Further, t2 is calculated by the second multiplexer 43 and the code converter 4.
8 to the adder 47. The adder 47 is s
The operation of 1 + t2 is executed, and the result is substituted into s1 of the register group 41 via the demultiplexer 44.

The operation result s1 at this time is sh / 2
If it is larger, the state shifts to state "3". If it is smaller than -sh / 2, the state shifts to state "5".

In state "7", a process is performed to calculate s0 + t1 to obtain a new s0. (Step 5) That is, in the state "7", s0 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and
Further, t1 is converted to the value of the second multiplexer 43 and the code converter 4.
8 to the adder 47. The adder 47 is s
The operation of 0 + t1 is executed, and the result is substituted into s0 of the register group 41 via the demultiplexer 44.

The operation result s0 at this time is sh / 2
If it is larger, the state is changed to "8", if it is smaller than -sh / 2, the state is changed to "10", and if neither is set, the state is changed to "12".

In the state "3", a process is performed to calculate t1 + 1 to make a new t1. (Step S6) That is, in the state "3", t1 is taken out from the register group 41 to the adder 47 via the first multiplexer 42.
Further, “1” is taken out to the adder 47 via the second multiplexer 43 and the code converter 48 to perform the operation. The adder 47 executes the operation of t1 +1 and substitutes the result into t1 of the register group 41 via the demultiplexer 44. Then, the state shifts to the state “4” irrespective of the results of the comparators 45 and 46.

In this state "4", a process is performed to calculate s1 -sh to make it a new s1. (Step S6) That is, in state "4", s1 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and
Also, sh is converted to the second multiplexer 43 and the code converter 4.
8 to the adder 47. The adder 47 is s
The operation of 1-sh is executed, and the result is substituted into s1 of the register group 41 via the demultiplexer 44. Then, the state transits to the state “7”.

In the state "5", a process for calculating t1 -1 and setting it as a new t1 is performed. (Step S7) That is, in the state “5”, the same arithmetic processing as in the state “3” is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state shifts to state “6” regardless of the results of the comparators 45 and 46.

In this state "6", a process of calculating s1 + sh to obtain a new s1 is performed. (Step S7) In the state "6", the same arithmetic processing as that in the state "4" is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state transits to the state “7”.

In the state "12", a process of calculating sg + s0 to make a new sg is performed. (Step 10) In other words, in the state "12", sg is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and s0 is taken out from the register group 41 via the second multiplexer 43 and the sign converter 48. And take it out. Adder 47
Executes the operation of sg + s0, and substitutes the result into sg of the register group 41 via the demultiplexer 44.

The operation result sg at this time is sh / 2
If it is larger, the state goes to state "13". If it is smaller than -sh / 2, the state goes to state "16". If neither is found, the state goes to state "15".

In state "8", a process is performed to calculate t0 + 1 to obtain a new t0. (Step S11) That is, in state “8”, t0 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and
Further, “1” is taken out to the adder 47 via the second multiplexer 43 and the code converter 48 to perform the operation. The adder 47 executes the operation of t0 + 1, and substitutes the result into t0 of the register group 41 via the demultiplexer 44. Then, the state transits to the state “9” irrespective of the results of the comparators 45 and 46.

In this state "9", a process is performed to calculate s0-sh to obtain a new s0. (Step S11) That is, in the state "9", s0 is taken out from the register group 41 to the adder 47 via the first multiplexer 42.
Also, sh is converted to the second multiplexer 43 and the code converter 4.
8 to the adder 47. The adder 47 is s
The operation of 0-sh is executed, and the result is substituted into s0 of the register group 41 via the demultiplexer 44. Then, the state shifts to the state “12”.

In the state "10", a process of calculating t0 -1 and setting it as a new t0 is performed. (Step S12) In this state "10", the same arithmetic processing as in state "8" is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state transits to the state "11" irrespective of the results of the comparators 45 and 46.

In this state "11", a process of calculating s0 + sh to obtain a new s0 is performed. (Step S12) That is, in the state “11”, the same arithmetic processing as in the state “9” is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state shifts to the state “12”.

In the state "15", processing for setting t0 as the frequency division ratio is performed. (Step 15) That is, in the state "15", t0 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and "0" is added via the second multiplexer 43 and the sign converter 48. It is taken out to the container 47 and performed. Adder 4
7 executes the operation of t0 + 0, and substitutes the result into the frequency division ratio of the register group 41 via the demultiplexer 44.
Then, the processing shifts to the state "1" (step S2) described above.

In the state "13", a process is performed in which 1 is added to t0 to obtain a frequency division ratio. (Step 16) That is, in the state "13", t0 is taken out from the register group 41 to the adder 47 via the first multiplexer 42, and "1" is added via the second multiplexer 43 and the sign converter 48. It is taken out to the container 47 and performed. Adder 4
7 executes the operation of t0 +1 and substitutes the result into the frequency division ratio of the register group 41 via the demultiplexer 44.
The state “1” is independent of the results of the comparators 45 and 46.
4 ”.

In this state "14", a process of calculating sg-sh to make a new sg is performed. (Step S16) That is, in the state “14”, sg is extracted from the register group 41 to the adder 47 via the first multiplexer 42, and sh is added to the adder 47 via the second multiplexer 43 and the sign converter 48. And take it out. Adder 47
Executes the operation of sg-sh, and substitutes the result into sg of the register group 41 via the demultiplexer 44. Then, the processing shifts to the state "1" (step S2) described above.

In the state "16", a process is performed in which 1 is subtracted from t0 to obtain a frequency division ratio. (Step S17) That is, in the state “16”, the same arithmetic processing as in the state “13” is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state transits to the state "17" irrespective of the results of the comparators 45 and 46.

In this state "17", a process of calculating sg + sh to obtain a new sg is performed. (Step S17) That is, in the state “17”, the same arithmetic processing as in the state “14” is performed. The difference between the codes at this time is processed by the code converter 48. Then, the state “1” described above (step S
Go to 2).

[0072]

[Table 1] In the above processing, the change from the state “14” “15” “17” to the state “1” is performed in synchronization with the pixel clock.
At the same time, the division ratio of the register group 41 is set in the variable frequency divider 52.

The variable frequency divider 52 divides the reference clock from the reference clock generation circuit 51 based on the frequency division ratio thus set, and generates a pixel clock once.

Since the frequency division ratio of the register group 41, that is, t0, changes so as to perform fθ error correction according to the scanning position, the timing of the pixel clock from the variable frequency divider 52 is the same as the timing at which the fθ error is corrected. Become.

In this apparatus, when the number of pixels in one scan, that is, the resolution changes, only the deflection angle Δθ of the light beam for one pixel changes.
With 1 / Δθ, it is possible to cope only by changing the value of sh set in the register group 41, and it is possible to easily cope with a change in resolution. Therefore, it is possible to easily cope with not only a number of stepwise resolution switching but also a continuous resolution switching.

When the scanning line length changes, that is, when the scanning start position changes, the above equation (8) is used.
In equations (9) and (10), T (θ _n ) and dT (θ _n ) /
Since dθ changes, it can be easily dealt with only by changing the initial values of the integers t0, s0, t1, and s1 set in the register group 41.

Next, another embodiment of the present invention will be described with reference to the drawings. The same parts as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

This is because the pixel clock generation circuit 34 is
As shown in the figure, a CPU (central processing unit) 61, a program memory 62, a correction information RAM (random access memory) 63, an address counter 64, an address bus switching circuit 65, a data bus switching circuit 66, and a reference clock generating circuit. 51, a variable frequency divider 52.

The address bus switching circuit 65 includes a CPU
61, from the program memory 62 to the correction information RAM 6
3 and the address counter 64
To the address bus connected to the RAM 63 for correction information.

The data bus switching circuit 66 includes a CPU 6
1. From the program memory 62 to the correction information RAM 63
And the data bus connected from the variable frequency divider 52 to the correction information RAM 63.

The correction information RAM 63 stores the frequency division ratio set in the variable frequency divider 52. The address counter 64 counts the pixel clock from the variable frequency divider 52 and designates the address of the correction information RAM 63.

The pixel clock generating circuit 34 is connected to the CPU 61 and the program memory 62 by the address bus switching circuit 65 and the data bus switching circuit 66 before the start of light beam scanning, for example, before printing when applied to a printer. The address bus and the data bus to the correction information RAM 63 are connected.

In this state, the CPU 61 calculates a frequency division ratio for generating a pixel clock for each pixel in one scan based on the program data in the program memory 62 according to the algorithm shown in FIG. Then, the calculated dividing ratio for each pixel is stored in the correction information RAM 63.

Subsequently, the address bus switching circuit 65 and the data bus switching circuit 66 are switched, and the address counter 64 and the variable frequency divider 52 are connected to the correction information RAM 63.

In this state, scanning of the light beam is started, that is, printing is started. Address counter 6 at the start of scanning
4 is reset, and the address from which the frequency division ratio corresponding to the first pixel stored in the correction information RAM 63 is read by the address counter 64 is designated. Thus, the correction information R
The frequency division ratio corresponding to the first pixel is read out from AM 63 and set in variable frequency divider 52.

The variable frequency divider 52 counts the reference clock from the reference clock generation circuit 51 and generates one pixel clock when the frequency becomes equal to the set frequency division ratio. The address counter 64 counts up by this pixel clock. As a result, the frequency division ratio corresponding to the next pixel is read out from the correction information RAM 63 and the variable frequency divider 52 is read.
Set to.

Thereafter, the same operation is repeated until one scan is completed, and a pixel clock is generated while setting the frequency dividing ratio sequentially calculated by the variable frequency divider 52.

Therefore, also in this embodiment, the variable frequency divider 5
The pixel clock generated from 2 is generated at the timing of correcting the fθ error.

Therefore, in this embodiment, the same effects as in the above embodiment can be obtained.

[0090]

As described above, according to the present invention, in the apparatus for electrically correcting the fθ error, the generation timing of the pixel clock for the fθ error correction can be controlled according to any resolution, and the versatility can be improved. .

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention with a housing omitted.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is a view showing a scanning range on a photosensitive surface in the embodiment.

FIG. 4 is a graph showing a relationship between a light beam deflection angle and a scanning speed.

FIG. 5 is a graph showing a relationship between a light beam deflection angle and a pixel clock cycle.

FIG. 6 is a flowchart showing a pixel clock generation process in the embodiment.

FIG. 7 is a block diagram showing a control circuit configuration of the embodiment.

FIG. 8 is a block diagram showing a specific configuration of the pixel clock generation circuit of FIG. 7;

FIG. 9 is a block diagram of a pixel clock generation circuit showing another embodiment of the present invention.

FIG. 10 is a perspective view showing a conventional example.

FIG. 11 is a diagram showing a cycle of a laser control signal with respect to a scanning position in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor laser oscillator 15 ... Scanner motor 16 ... Right angle prism 34 ... Pixel clock generation circuit 41 ... Register group 42, 43 ... Multiplexer 44 ... Demultiplexer 47 ... Adder 48 ... Code converter 50 ... Control circuit 51 ... Reference clock generation Circuit 52: Variable frequency divider

Claims (2)

(57) [Claims] 1. An optical scanning apparatus for controlling on / off of a laser beam based on recording information at a timing of a pixel clock generated from a pixel clock generating means, and scanning a photosensitive surface with the laser beam to dot-record information. The pixel clock generating means stores a reference clock generating means for generating a reference clock serving as a source of the pixel clock, and at least a numerical value T0 corresponding to a pixel clock cycle and a numerical value T1 corresponding to a time derivative of the numerical value T0. Storage means, a constant A corresponding to a pixel clock cycle at the center of the scanning width of the laser beam, and numerical values T0, T stored in the storage means;
T1 = T1 + 2A-4T0 and T0 = T0
+ T1, calculating means for updating the numerical values T0, T1 in the storage means based on the calculation result; and using the numerical value T0 in the storage means as a frequency division ratio, and using the frequency division ratio as a reference to the reference clock generation means. An optical scanning device, comprising: variable frequency dividing means for dividing a reference clock to generate a pixel clock. 2. Assuming that the reciprocal of the beam deflection angle per pixel is sh, numerical values T0 and T1 are expressed by using integers t0 and t1 indicating an integer part and integers s0 and s1 indicating a decimal part.
The relational expressions of T0 = t0 + s0 / sh and T1 = t1 + s1 / sh are used. The storage means stores integers t0, t1, s0, s1 in place of the numerical values T0, T1, and the arithmetic means stores the numerical values T0.
, T1, and the integers t0, t1, s0, and s1 are updated, and the integer s is updated every time the division ratio (t0 + s0 / sh) is updated.
An accumulating means for accumulating 0 is provided. When the accumulated value of the accumulating means is larger than sh / 2, t0 is incremented by 1, and sh is subtracted from the accumulated value. When the accumulated value is smaller than sh / 2, t
2. The optical scanning device according to claim 1, wherein sh is added to the accumulated value by decrementing 0.