JP2877527B2 - Pulse voltage generation circuit and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a pulse voltage and a driving method thereof, and more particularly to a circuit suitable for generating a pulse voltage to be applied to a charge transfer section of a CCD image sensor.

[0002]

2. Description of the Related Art In recent years, CCD image sensors have been widely used for facsimile machines, video cameras and the like. Although there are several types of CCD image sensors, those generally driven by applying a two-phase clock pulse to a register electrode are generally used. A power supply voltage and a pulse amplitude of 12 V are generally used. However, recently, a CCD image sensor driven at a low voltage of 5 V, for example, has been put to practical use based on demands for low power consumption and low cost.

FIG. 8 shows a circuit configuration in which a conventional pulse voltage generating circuit is used for an output section of a CCD image sensor.
The transfer electrodes 21 are arranged, and are alternately connected to the drive pulse φ2 input terminal 19 or the drive pulse φ1 input terminal 20.

A pulse generating circuit 24a is connected to the last-stage transfer electrode 21a. The pulse generating circuit 24a includes a capacitor 18, a diode 22, resistors R1 and R2, a voltage VDD input terminal 25, and a ground terminal.

A capacitor 18 is connected between the transfer electrode 21a and the drive pulse φ2 input terminal 20, and an anode of a diode 22 is connected to the transfer electrode 21a. A resistor R is connected between the ground terminal and the voltage VDD input terminal 25.
1 and R2 are connected in series.
The cathode of the diode 22 is connected to a node N1 that connects the node N2 to the node N2.

An output gate electrode 17 is provided adjacent to the final-stage transfer electrode 21a.
The output gate terminal 16 is connected to 7. A floating junction 15 and a reset electrode 14 are sequentially provided adjacent to the output gate electrode 17. The floating junction 15 is connected to an input terminal of the amplifier 11, and the reset electrode 14 is connected to a reset terminal 13. The output terminal of the amplifier 11 is connected to an output terminal 12 for outputting a signal to the outside.

Two-phase drive pulses φ1 and φ2 are alternately applied to the transfer electrode 21, and signal charges are sequentially transferred from the right side to the left side in the figure through the potential well under the transfer electrode 21. Then, the signal charge transferred from under the transfer electrode 21a at the final stage to under the output gate electrode 17 is detected by the floating junction 15 made of an n-type impurity layer, amplified by the amplifier 11, and then output from the output terminal 12 to the outside. Is output. Further, when a reset voltage is applied to the reset electrode 14, the reset electrode 14 enters a reset state.

FIG. 9A shows a cross-sectional structure in which the output portion of the CCD image sensor shown in FIG. 8 is formed on a semiconductor wafer. A buried channel portion 27 is formed on the surface of the p-type semiconductor substrate 28. As described above, the transfer electrodes 21 are sequentially arranged on the surface of the p-type semiconductor substrate 28 via an insulating film (not shown). Here, the transfer electrodes 21 are electrodes 21aa and 21aa.
bb, and a p-type impurity layer 26 is formed under one electrode 21aa to function as a barrier.

Next, the potentials of the transfer electrodes 21 and 21a, the output gate electrode 17, and the reset electrode 14 are shown in FIG. A drive pulse φ1 or φ2 is applied to each of the transfer electrodes 21 and 21a.
Is applied, the depth of the potential well changes by the amplitude of the voltage V. Here, even with the same transfer electrode 21, the depth of the potential well below the electrode 21 aa is reduced by the presence of the p-type impurity layer 26.

The depth of the potential well of only the final stage transfer electrode 21a is reduced by the action of the pulse generation circuit 24a. This is because, in a low-voltage driven CCD image sensor, in order to ensure a sufficient saturation output voltage of the floating junction 15, the output gate electrode 1
This is because it is necessary to reduce the depth of the potential below the gate electrode 7. Therefore, in order to transfer the signal charges sequentially through the deep potential wells below the transfer electrodes 21 and then transfer the signal charges to the lower portion of the output gate electrode 17 having the shallow potential, the transfer electrodes 2 in the final stage are required.
The well at potential 1a must be shallow as shown in FIG. 2 (b).

The above-described clamp function for shifting the pulse voltage to be applied to the final-stage transfer electrode 21a to a low level while keeping the amplitude V unchanged is provided by the pulse generation circuit 2
4a has it. That is, when the power supply voltage VDD is equal to the resistances R1
To the potential VN1 of the node N1 divided by
The pulse voltage to be applied to a is clamped. Therefore, the high level of the drive pulse φ1 input from the drive pulse φ1 input terminal 20 is clamped by the diode 22, and the drive pulse φ1 is applied to the capacitor 18 to generate an amplitude V, and then input to the transfer electrode 21a. Is done.

[0012]

However, when a CCD image sensor is driven using such a conventional pulse generating circuit, there are the following problems. In the circuit shown in FIG. 8, the power supply voltage VDD and the driving pulse φ1
FIG. 10 shows changes in the potentials of the node N2 on the anode side and the node N1 on the cathode side of the diode 22 when φ2 and φ2 are applied.

In the conventional pulse generation circuit, the power supply voltage VDD is input to the voltage VDD input terminal 25, and the driving pulses φ1 and φ2 are input to the driving pulse φ1 input terminal 20 and the driving pulse φ2 input terminal 19, respectively. There were no restrictions on the order. Therefore, the drive pulses φ1 and φ2 may be input first, and then the power supply voltage VDD may be input.

When drive pulses φ1 and φ2 are input and power supply voltage VDD is not input yet, nodes N1 and N2
The potential of No. 2 is as shown in FIG. Since the power supply voltage VDD is not input to the voltage VDD input terminal 25, the potential of the node N1 is at the same level as the ground potential 0. The level of the potential of the node N2 changes with the amplitude of the voltage V when the driving pulse φ1 is input to the driving pulse φ1 input terminal 20. Next, when the power supply voltage VDD is input to the voltage VDD input terminal 25, a value V1 obtained by dividing the voltage VDD by the resistors R1 and R2 is applied to the node N1. Thereby, the depth of the potential of the node N1 is increased by the voltage V1 as shown in FIG. Therefore, the node N1
Is higher than the potential VN2 of the node N2, and a reverse bias voltage is applied to the diode 22.

For this reason, a leakage current flows through the diode 22 from the node N1 having a high potential to the node N2,
It takes time to reach a steady state as shown in FIG. From the state shown in FIG. 10B to the steady state shown in FIG. 10C, the pulse generation circuit 24a does not operate, and the driving pulse φ1 is applied to the transfer electrode 21.
Since the voltage is not applied to a, the timing at which the CCD image sensor starts operating is delayed.

In view of the above circumstances, the present invention provides a pulse voltage generating circuit capable of generating a pulse voltage so that a CCD image sensor can start operating immediately without delay when it should start operating. And a driving method thereof.

[0017]

A pulse voltage generating circuit according to the present invention comprises a pulse input terminal to which a pulse is input, and a capacitor connected in series between an electrode to which the pulse is to be applied and the pulse input terminal. , Connected between the electrode and the power supply terminal,
An element that allows current to flow from the electrode to the power supply terminal and a capacitor are connected in series between the capacitor and the pulse input terminal or between the power supply terminal and the element, and a pulse input to the pulse input terminal is input to the power supply terminal. And a control unit that controls the timing of input so that the input is not performed earlier.

Further, a method of driving a pulse voltage generating circuit according to the present invention includes a pulse input terminal to which a pulse is input, a capacitor connected in series between an electrode to which the pulse is to be applied, and the pulse input terminal, A method for driving a pulse voltage generation circuit comprising: an element connected between an electrode and a power supply terminal; and an element for flowing a current from the electrode to the power supply terminal, wherein the input of a pulse to the pulse input terminal is performed by a power supply terminal. This is characterized in that it is not performed before input of the power supply voltage to the power supply.

[0019]

When a pulse is input to the pulse input terminal, the pulse is applied to the electrode via a capacitor, and the potential on the electrode side of the element that flows current from the electrode to the power supply terminal changes with the amplitude of the pulse. The potential on the terminal side is at a low level such as a ground potential. Thereafter, when the potential of the power supply terminal becomes the power supply voltage, the potential on the power supply terminal side of the element that flows current from the electrode to the power supply terminal increases, and the voltage is applied to this element in a direction opposite to the direction in which the current flows. Applied. To reach the steady state from this state, a leak current must flow in the element in the reverse direction, and it takes time.
There is a time delay before the pulse is applied to the electrodes. On the other hand, by providing the control unit, the input timing is controlled so that the input of the pulse to the pulse input terminal is not performed earlier than when the potential of the power supply terminal becomes the power supply voltage, A voltage that causes a current to flow in the opposite direction is not applied to the element that causes a current to flow from the electrode to the power supply terminal, and the element quickly reaches a steady state and applies a pulse to the electrode without a time delay. be able to.

Further, according to the driving method of the pulse voltage generating circuit of the present invention, the input of the pulse to the pulse input terminal is prevented from being performed earlier even when the potential of the power supply terminal becomes the power supply voltage. Similarly, a voltage that causes a current to flow in the opposite direction is not applied to the element that causes a current to flow from the electrode to the power supply terminal, and the application of a pulse to the electrode can be performed without a time delay. .

[0021]

An embodiment of the present invention will be described below with reference to the drawings. First, a circuit configuration of a pulse voltage generating circuit according to the first embodiment is shown in FIG. Compared with FIG. 8 showing a conventional circuit, the pulse voltage generation circuit 24b has an N-channel M
The difference is that an OS transistor 61 is newly provided. The transistor 61 has a source connected to the capacitor 18, a drain connected to the drive pulse φ1 input terminal 20, and a gate connected to the voltage VDD input terminal 25. Thus, unless the power supply voltage VDD is input to the voltage VDD input terminal 25 and the transistor 61 is turned on, even if the drive pulse φ1 is input to the drive pulse It will not be applied. Here, the same components as those of the conventional circuit of FIG. 8 are denoted by the same reference numerals, and description thereof is omitted. Further, the connection relationship between the components is the same except that a transistor 61 is added.

As described above, in the pulse generation circuit 24b, the timing for applying the power supply voltage VDD is determined by the drive pulse φ.
By making the timing earlier than the timing of applying 2, the potential VN1 of the node N1 and the potential VN2 of the node N2 change as shown in FIG. First, when the power supply voltage VDD is applied to the voltage VDD input terminal 25, this voltage VDD is applied to the resistors R1 and R1.
2 is applied to the node N1. Thus, the depth of the potential VN1 at the node N1 is increased by the voltage V1 as shown in FIG. The potential VN2 of one node N2 maintains the level of the ground potential 0 because the drive pulse φ2 has not been applied yet.

When the power supply voltage VDD is applied to the voltage VDD input terminal 25 and the transistor 61 is turned on, the drive pulse φ1 input to the drive pulse φ1 input terminal 20 becomes
This is applied to the node N2 via the capacitor 18.
At this time, the potential VN1 of the node N1 and the potential V of the node N2
N2 is as shown in FIG. 2 (b). The potential VN1 of the node N1 originally has the amplitude of the voltage V of the drive pulse φ2. However, as shown in FIG.
Is higher than the node N2 by the voltage V1.
Therefore, the diode 22 is forward biased. As a result, as shown by the dotted line, the high-level potential is clamped to the level of the voltage V1 and the node N
The potential VN2 of No. 2 has an amplitude by the voltage V-V1.

When a bias voltage is applied to the diode 22 in the forward direction and a current flows in the forward direction, a steady state as shown in FIG. The potential VN1 of the node N1 is the voltage V1, and the potential VN2 of the node VN2 changes with the amplitude of the voltage V. When the stationary state is reached, the pulse generation circuit 24b operates to apply the pulse φ2 to the transfer electrode 21a, and the CCD image sensor starts operating.

Here, unlike the conventional case shown in FIG. 10, since a bias voltage is applied to the diode 22 in the forward direction, the state shown in FIG. 2B reaches the steady state shown in FIG. 2C. The time until is much shorter. Therefore, CC
It is possible to start the operation of the D image sensor with almost no delay.

Next, a second embodiment of the present invention will be described. As described above, the voltage to be applied to the transfer electrode 21 needs to be lowered as approaching the output gate electrode 17 to make the potential well shallow. In the circuit according to the first embodiment, only the voltage to be applied to the final-stage transfer electrode 21a is shifted to a low level. On the other hand, in the second embodiment, as shown in FIG.
From the transfer electrode 21d which is three places before 1a, the transfer electrode 21
The applied pulse voltage is shifted to a lower level so that the potential well becomes shallower in order toward d, 21c, 21b, and 21a.

The structure of the pulse voltage generating circuit according to the second embodiment is as shown in FIG. The following elements are provided as the pulse voltage generation circuit 24c. The resistors R21 to R21 are connected between the voltage VDD input terminal 42 and the ground terminal.
R25 is connected in series. A diode 41a is connected between a node N11 between the resistors R21 and R22 and a node N12 to which the transfer electrode 21a is connected. Similarly, node N between resistors R22 and R23
13 and a node N14 to which the transfer electrode 21b is connected, a diode 41b is connected, and resistors R23 and R24
A diode 41c is connected between a node N15 between the node N15 and the node N16 to which the transfer electrode 21c is connected, a node N17 between the resistors R24 and R25, and a node N18 to which the transfer electrode 21d is connected. The diode 41d is connected between them. Each diode 41a-41
The direction of d is, for example, the diode 41a, the node N
The cathode is connected to 11 and the anode is connected to the node N2.

Further, the pulse voltage generating circuit 24c
The control unit 43 includes N-channel MOS transistors 44a and 44b. Drive pulse φ2 input terminal 4
5 and the node N19, the source / drain of the transistor 44a is connected, and the drive pulse φ1 input terminal 46
The source / drain of the transistor 44b is connected between the node and the node N20. The gates of the transistors 44a and 44b are both connected to the voltage VDD input terminal 42.

Further, a capacitor 45a is connected between the node N12 and the node N20, and the node N14 and the node N1 are connected.
9, a capacitor 45b is connected. Further, a capacitor 45c is connected between the node N16 and the node N20,
The capacitor 45d is connected between the node N18 and the node N19.

Nodes N11, N13, N15 and N17
To the power supply voltage VDD by resistors R21 to R25, respectively.
Is applied. And the node N11
In a state where the high level is clamped to the potential applied to the transfer electrode 21, the drive pulse φ 1 is applied to the transfer electrode 21 via the capacitor 45 a.
a, the driving pulse φ2 is applied to the capacitor 4 while the high level is clamped to the potential applied to the node N13.
5b is applied to the transfer electrode 21b. Similarly, in a state where the high level is clamped to the potential applied to the node N15, the driving pulse φ1 is applied to the transfer electrode 21c via the capacitor 45c, and the high level is clamped to the potential applied to the node N17. Drive pulse φ2
Is applied to the transfer electrode 21d via the capacitor 45d. As a result, the level of the pulse voltage applied to each of the transfer electrodes 21 a to 21 d gradually decreases toward the output gate electrode 17.

Here, the transistor 44a of the control unit 43
And 44b conduct when the power supply voltage VDD is input to the voltage VDD input terminal 42. These transistors 44a and 4
Until 4b becomes conductive, the drive pulses φ2 and φ1 are cut off and are not applied to the transfer electrodes 21a to 21d. Therefore, by the operation of the control unit 43, the drive pulses φ1 and φ2 are not input until the power supply voltage VDD is input. Accordingly, a bias voltage is applied to each of the diodes 41a to 41d in the forward direction in the same manner as in the first embodiment, the steady state is quickly reached, and the operation of the CCD image sensor is started at a desired timing without delay. Can be done.

FIG. 5 shows a configuration of a pulse voltage generating circuit 24f according to a third embodiment of the present invention. This circuit is the third
It differs from the pulse generation circuit 24c in the figure in the following point. Instead of the control unit 43, control units 46 and 47 operating as inverters are provided to control the drive pulses φ1 and φ2 not to be input before the power supply voltage VDD. The control unit 46 includes a resistor R31 and an N-channel MOS transistor 49.
Is connected between the voltage VDD input terminal 48 and the node N19. The transistor 49 has a drain connected to the node N19, a gate connected to the inverted pulse φ2 input terminal 50, and a source grounded. The control unit 46 includes a resistor R32 and an N-channel MOS transistor 51. The resistor R32 is connected to the voltage VDD input terminal 48 and the node N.
The transistor 51 has a drain connected to the node N20 and a gate connected to the inversion pulse φ1 input terminal 52.
And the source is grounded. The inversion pulse φ1 input terminal 52 and the inversion pulse φ2 input terminal 50
Are supplied with inverted pulses φ1 and φ2 obtained by inverting the drive pulses φ1 and φ2, respectively.

Until the power supply voltage VDD is input to the voltage VDD input terminal 48, the transistors 49 and 51 are off, and the inversion pulses φ2 and φ1 are cut off and are not applied to the transfer electrodes 21a to 21d. When the power supply voltage VDD is input, the transistors 49 and 51 repeat ON / OFF in accordance with the levels of the inversion pulses φ2 and φ1, respectively. For example, a high-level inverted pulse φ2 is applied to the gate of the transistor 49 via the inverted pulse φ2 input terminal 50.
Is input, the level of the node N19 becomes low level. Conversely, when the low level inversion pulse φ2 is input, the node N19 turns off and the level of the node N19 becomes high level. Therefore, similarly to the pulse voltage generation circuit 24c of FIG. 3, when the drive pulse φ2 is at a low level, the node N19
Is at a low level, and when the drive pulse φ2 is at a high level, the node N19 is at a high level.

The voltage VDD is equal to the inverted input pulse φ.
By inputting signals before the signals φ1 and φ2, a bias voltage is applied to each of the diodes 41a to 41d in the forward direction. Therefore, it is possible to quickly reach a steady state and quickly start the operation of the CCD image sensor.
The same effects as those of the first and second embodiments can be obtained.

Here, in the circuits according to the first to third embodiments, all are controlled so that the power supply voltage VDD is input first, but the driving pulses φ1 and φ2 (inversion pulses φ1 and φ2) are used.
Even when 2) is performed at the same time, the same effect can be obtained because no reverse bias voltage is applied to the diode.

Further, in the pulse voltage generating circuits according to the first to third embodiments, the driving pulses φ1 and φ2 (inversion pulses φ1 and φ2) are automatically input so as not to be input earlier than the power supply voltage VDD. Controlled. The driving method of the pulse voltage generating circuit according to one embodiment of the present invention is such that the input of the power supply voltage VDD to the pulse voltage generating circuit is
It is characterized by being performed earlier than or simultaneously with the drive pulses φ1, φ2 (inversion pulses φ1, φ2). Therefore, this driving method is applied to the voltage VDD input terminal 25 in the circuit of FIG.
The timing at which the power supply voltage VDD is input to the drive pulse φ1 input terminal 20 is earlier or at the same time as the timing at which the drive pulse φ1 is input to the input terminal 20.
The effects described above can be obtained.

The pulse voltage generating circuit shown in FIG. 6 corresponds to a circuit obtained by removing the control unit 43 from the circuit shown in FIG. Since other components and connection relations are the same, the same components are denoted by the same reference numerals and description thereof is omitted. In the circuit of FIG. 6 as well, the power supply voltage VDD is
The timing of inputting the drive pulse φ1 to the drive pulse φ1 input terminal 46 and the timing of inputting the drive pulse φ1 to the drive pulse φ2 input terminal 45
A similar effect can be obtained by setting the timing earlier than or simultaneously with the timing of inputting the number 2.

The pulse voltage generating circuit 24e of the present invention shown in FIG. 7 is different from the pulse generating circuit 24d shown in FIG.
This is equivalent to one provided with transistors 34a to 34d.

Here, the drains of the transistors 34a to 34d are all grounded. The source of the transistor 34a is connected to the transfer electrode 21a, and the gate is connected to the resistor R2.
1 and a resistor N22. The source of the transistor 34b is the transfer electrode 21b.
The gate is connected to a node N32 that connects the resistors R22 and R23. The transistor 34c has a source connected to the transfer electrode 21c and a gate connected to the resistor R23 and the resistor R23.
24 to the node N33. Further, the transistor 34d has a source connected to the transfer electrode 21d,
Node N whose gate connects resistor R24 and resistor R25
34.

The driving method according to the present embodiment can be applied to the pulse voltage generating circuit 24e.
That is, the timing at which the power supply voltage VDD is input to the voltage VDD input terminal 42 is the timing at which the drive pulse φ2 is input to the drive pulse φ2 input terminal 45, and the timing at which the drive pulse φ1
When the driving pulse φ1 is input to the input terminal 45 earlier or at the same time, the operation of the CCD image sensor can be started quickly as in the case of applying to the circuit shown in FIG. Can be

The above embodiments are merely examples, and do not limit the present invention. For example, as the pulse voltage generation circuit of the present invention, the configuration of the control unit includes the transistor 61 of FIG. 1, the control unit 43 of FIG. 3, and the control units 46 and 47 of FIG.
The present invention is not limited to this, and any device may be used as long as it can be controlled so that the power supply voltage is input before or simultaneously with the drive pulse.

[0042]

According to the pulse voltage generation circuit of the present invention, the input timing of the pulse is controlled by the control unit so that the input of the pulse to the pulse input terminal is not performed before the potential of the power supply terminal becomes the power supply voltage. Is controlled, a voltage that causes current to flow in the reverse direction is not applied to the element that flows current from the electrode to the divided voltage output terminal, and a steady state is reached quickly, and the application of a pulse to the electrode takes time. It can be performed without any significant delay.

According to the driving method of the pulse voltage generating circuit of the present invention, the input of the pulse to the pulse input terminal is not performed before the potential of the power supply terminal becomes the power supply voltage. The application of the pulse to the electrode is performed without a time delay.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention connected to an output section of a CCD image sensor.
FIG. 4 is a circuit diagram showing a configuration in a case where a pulse voltage generation circuit according to the embodiment is provided.

FIG. 2 is an explanatory diagram showing changes in potentials of a node N1 and a node N2 in the same circuit.

FIG. 3 shows a second embodiment of the present invention connected to an output section of a CCD image sensor.
FIG. 4 is a circuit diagram showing a configuration in a case where a pulse voltage generation circuit according to the embodiment is provided.

FIG. 4 is an explanatory diagram showing a cross-sectional structure of an output unit of the CCD image sensor shown in FIG. 3 and a potential under each electrode.

FIG. 5 shows a third embodiment of the present invention connected to the output section of the CCD image sensor.
FIG. 4 is a circuit diagram showing a configuration in a case where a pulse voltage generation circuit according to the embodiment is provided.

FIG. 6 is a circuit diagram showing a configuration in which a pulse voltage generation circuit to which a driving method of the pulse voltage generation circuit according to one embodiment of the present invention can be applied is provided in an output unit of a CCD image sensor.

FIG. 7 shows another pulse voltage generation circuit to which the driving method of the pulse voltage generation circuit according to one embodiment of the present invention can be applied.
FIG. 4 is a circuit diagram showing a configuration in a case where the output unit of the D image sensor is provided.

FIG. 8 is a circuit diagram showing a configuration in a case where a conventional pulse voltage generation circuit is provided in an output section of a CCD image sensor.

9 is an explanatory diagram showing a cross-sectional structure of an output unit of the CCD image sensor shown in FIG. 8 and a potential under each electrode.

FIG. 10 is an explanatory diagram showing changes in potentials of nodes N1 and N2 in the same circuit.

[Explanation of symbols]

 Reference Signs List 11 amplifier 12 output terminal 13 reset terminal 14 reset electrode 15 floating junction 16 output gate terminal 17 output gate electrode 18 capacitance 19 drive pulse φ2 input terminal 20 drive pulse φ1 input terminal 21 transfer electrode 22 diode 24a pulse voltage generation circuit 25 voltage VDD input Terminal 34a P-channel MOS transistor 43 Control unit 44a N-channel MOS transistor 53 Inversion pulse φ2 input terminal 54 Inversion pulse φ1 input terminal

Continuation of the front page (56) References JP-A-63-199581 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (2)

(57) [Claims] 1. A pulse input terminal for inputting a pulse, a capacitor connected in series between an electrode to which the pulse is to be applied and the pulse input terminal, and a connection between the electrode and a power supply terminal An element that flows a current from the electrode to the power supply terminal, and is connected in series between the capacitor and the pulse input terminal or between the power supply terminal and the element, and is connected to the pulse input terminal. A pulse voltage generating circuit, comprising: a control unit that controls input timing so that the input of the pulse is not performed before the input of the power supply voltage to the power supply terminal. 2. A pulse input terminal for inputting a pulse, a capacitor connected in series between an electrode to which the pulse is to be applied and the pulse input terminal, and a capacitor connected between the electrode and a power supply terminal. Wherein the input of the pulse to the pulse input terminal includes the input of a power supply voltage to the power supply terminal. A driving method of the pulse voltage generation circuit, wherein the driving is not performed before the driving.