JP2877033B2 - Operational amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit having a complementary output circuit for performing a push-pull operation by a p-channel output stage MOS transistor and an n-channel output stage MOS transistor.

[0002]

2. Description of the Related Art In many cases, an operational amplifier circuit based on a CMOS process has a CMO at an input stage as shown in FIG.
An S differential circuit is used, and the output stage is a single-ended type having a constant current load. This kind of operational amplifier circuit, when the load connected to the output terminal is a low impedance load,
There is a problem with drive capacity. This is because the supply current is limited by the constant current load. In order to have a sufficient driving capability for a low impedance load, it is necessary to make the impedance of the constant current load sufficiently small to supply a large current, and accordingly, the output stage MOS transistor has a sufficiently large current capacity. It is necessary to do things.

On the other hand, as an operational amplifier circuit advantageous for driving a low impedance load, a circuit in which the p-channel and the n-channel are reversed from the operational amplifier circuit configuration of FIG. 3 is prepared, and as shown in FIG. It is conceivable to provide a complementary circuit by arranging the power supply VDD and the ground VSS side. With such a circuit, it is possible to drive the load by the push-pull operation of the p-channel MOS transistor and the n-channel MOS transistor in the output stage.

[0004]

However, as shown in FIG. 4, in a complementary circuit in which only two single-ended operational amplifier circuits are combined, a p-channel MO of an output stage is used.
It does not have the function of stabilizing the current of the S transistor and the n-channel MOS transistor. Because p-channel M
This is because, under a bias condition in which the OS transistor and the n-channel MOS transistor are simultaneously turned on and a through current flows, the output potential does not change even if the through current increases, and there is no feedback function for suppressing the increase in the through current. Therefore, there arises a problem that a through current increases to cause breakdown. Conversely, if the current of the output stage MOS transistor decreases simultaneously, the output stage is cut off.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an operational amplifier circuit having a push-pull operation for an output stage and a function of stabilizing an output stage current.

[0006]

An operational amplifier circuit according to the present invention includes a first input stage differential amplifier circuit having an active load by an n-channel differential MOS transistor pair and a p-channel first current mirror circuit. , P-channel differential M
A second input stage differential amplifier connected in parallel to the first input stage differential amplifier, the second input stage differential amplifier having an active load of an OS transistor pair and an n-channel second current mirror circuit; The gate is controlled by the output of the amplifier circuit, the gate is controlled by the output of the p-channel output stage MOS transistor having the drain connected to the signal output terminal and the output of the second input stage differential amplifier circuit, and the drain is connected to the signal output terminal. -Channel output stage MO connected to
A complementary output circuit having an S transistor, and a p-channel current detection MOS to which the same gate-source bias as the p-channel output stage MOS transistor is applied
A first current detection circuit that obtains a detection current proportional to the current of the p-channel output stage MOS transistor using a transistor; and an n-channel output circuit that receives the same gate-source bias as the n-channel output stage MOS transistor. A second current detection circuit that obtains a detection current proportional to the current of the n-channel output stage MOS transistor using a current detection MOS transistor, and is controlled by outputs of the first and second current detection circuits, respectively. Current source M
A reference current source circuit having an OS transistor and obtaining a reference current proportional to the sum of detection currents of the first and second current detection circuits as a common reference current of the first and second current mirror circuits; It is characterized by:

In the present invention, preferably, the first current detection circuit is configured such that a ratio between a channel width and a channel length of the p-channel current detection MOS transistor is equal to a channel width and a channel length of the p-channel output stage MOS transistor. Is set to 1 / N (where N> 1), and a detection current of 1 / N of the collector current of the p-channel output stage MOS transistor is obtained. The ratio of the channel width to the channel length of the n-channel current detecting MOS transistor is set to 1 / N of the ratio of the channel width to the channel length of the n-channel output stage MOS transistor, M
It is characterized in that a detection current of 1 / N of the collector current of the OS transistor is obtained.

[0008]

In the operational amplifier circuit according to the present invention, the signal input stage is made a complementary circuit by the first and second input stage differential amplifier circuits, and the output stage is also a p-channel output stage MOS transistor and an n-channel output stage MOS transistor. And a complementary circuit. The first and second input stage differential amplifier circuits are provided with an active load by the first and second current mirror circuits, respectively. In order to stabilize the current in the output stage, the p-channel MOS transistor in the output stage and n
First and second current detection circuits for detecting the current of the channel MOS transistor are provided, and a reference current source circuit for obtaining a reference current proportional to the sum of the detection currents is provided by a first and a second current mirror. The circuit is configured as a common reference current source circuit.

Thus, in the operational amplifier circuit according to the present invention, when the through current in the output stage tends to fluctuate, the common reference current of the first and second current mirror circuits is controlled, for example, in a direction in which the through current increases. If so, in the first and second input stage differential amplifier circuits, the reference current acts in a direction in which each active load is turned on more deeply, whereby both the output stage p-channel MOS transistor and the n-channel MOS transistor are turned off. The gate is biased. That is, feedback for suppressing an increase in the output stage through current is involved, the output current is stabilized, and destruction due to runaway or the like is reliably prevented. Since the negative feedback due to the above-described current detection and reference current control is not applied to the difference between the output currents, there is no effect on the amplification factor of the operational amplifier circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an operational amplifier circuit according to one embodiment of the present invention. In the input stage, a constant current source I2 is provided as a common source, and a first difference using a pair of n-channel differential MOS transistors Q1 and Q3 whose gates serve as an inverting input terminal IN2 and a non-inverting input terminal IN1. Dynamic amplification circuit 1
Similarly, a constant current source I1 is provided in the common source, and each gate has an inverting input terminal IN2 and a non-inverting input terminal I1.
N-channel p-channel differential MOS transistor pair Q
2 and a second differential amplifier circuit 2 using Q4 are arranged in parallel.

The MOS transistor Q5 of the first current mirror circuit 3 composed of p-channel MOS transistors Q7 and Q5 is active on the drain side of the MOS transistor Q3 serving as the output terminal N1 of the first differential amplifier circuit 1. Inserted as a load. Similarly, n-channel MOS transistors Q8 and Q6 are connected to the drain side of a MOS transistor Q4 serving as the output terminal N2 of the second differential amplifier circuit 2.
MOS of the second current mirror circuit 4 configured by
Transistor Q6 is inserted as an active load.

A p-channel output stage MOS transistor Q15 whose gate is controlled by the output terminal N1 of the first differential amplifier circuit 1, and an n whose gate is controlled by the output terminal N2 of the second differential amplifier circuit 2. The output stage MOS transistor Q16 of the channel is arranged on the power supply VDD side and the ground VSS side, respectively, and the drain is commonly connected to the signal output terminal OUT to form the complementary output circuit 5.

The first and second current mirror circuits 3 and 4 are provided with a common reference current source circuit 8. The reference current source circuit 8 includes an n-channel MOS transistor Q9 on the first current mirror circuit 3 side whose conductivity is controlled in accordance with the amount of current of the p-channel output stage MOS transistor Q15, and an n-channel output stage. MOS transistor Q1
6, the p-channel MOS transistor Q1 of the second current mirror circuit 4 whose conduction degree is controlled in accordance with the amount of current
0 and resistors R1 and R2 inserted in series with these.

First and second current detection circuits 6 and 7 are provided for detecting currents of the output stage MOS transistors Q15 and Q16 of the complementary output circuit 5, respectively. In the first current detection circuit 6, the gate is driven in common with the output stage MOS transistor Q15, and the source is the power supply VDD.
And a p-channel current detecting MOS transistor Q11 to which the same gate-source bias as the MOS transistor Q15 is applied. Similarly, the second current detection circuit 7 has an n-channel current detection MOS transistor Q12 to which the same gate-source bias as the output stage MOS transistor Q16 is applied.

The ratio of the channel width W11 to the channel length L11 of the current detecting MOS transistor Q11 is such that the following equation 1 is satisfied with respect to the ratio of the channel width W15 to the channel length L15 of the output stage MOS transistor Q15. Is set. Here, N is a number larger than 1.

[0016]

## EQU1 ## W11 / L11 = (W15 / L15) / N

Similarly, current detecting MOS transistor Q
The element size is set so that the ratio of the channel width W12 to the channel length L12 of the output stage MOS transistor Q16 satisfies the following expression 2 with respect to the ratio of the channel width W16 to the channel length L16 of the output-stage MOS transistor Q16.

[0018]

## EQU2 ## W12 / L12 = (W16 / L16) / N

One current detecting MOS transistor Q1
The drain of 1 is connected to ground VSS through a p-channel MOS transistor Q13 via a resistor R3 serving as a load. Similarly, the drain of the other current detecting MOS transistor Q12 is connected to the power supply VDD via the resistor R4 and the n-channel MOS transistor Q14. The gates of these MOS transistors Q13 and Q14 are controlled by the potential of an intermediate potential point N3 by resistors R5 and R6 which divide the voltage between the power supply VDD and the ground VSS.

The above resistor R3 and MOS transistor Q1
3 and the part of the resistor R4 and the MOS transistor Q14 are respectively connected to the current detecting MOS transistor Q1.
1 and Q12 are converted to voltage values by a current-voltage conversion circuit.
5 is a common reference current source circuit for the current mirror circuits 3 and 4
Are connected to the gates of the MOS transistors Q9 and Q10.

The operation of stabilizing the output current of the operational amplifier circuit having such a configuration will be described below. P of the complementary output circuit 5
Channel MOS transistor Q15 and n-channel MOS
The collector current of the transistor Q16 is
The current is detected by the second current detection circuits 6 and 7. The ratio between the channel width and the channel length of the current detecting MOS transistors Q11 and Q12 is different from the output stage MOS transistor Q1.
5 and Q16, the output stage MOS transistors Q15 and Q15 are set to 1 / N as described above.
Current detection is performed with a detection current of 1 / N of the collector current of Q16.

The reference current from the reference current source circuit 8 is variably controlled so as to be proportional to the sum of the currents detected by the first and second current detection circuits 6 and 7, and this is controlled by the first and second current mirrors. By the circuits 3 and 4, the first and second
As an active load current of the differential amplifier circuits 1 and 2 of FIG. Therefore, for example, when the through current in the complementary output circuit 4 increases, the currents of the active load MOS transistors Q5, Q6 in the first and second differential amplifier circuits 1, 2 increase accordingly. That is, the potential of one output terminal N1 increases and the other output terminal N2 operates in the direction of decreasing the potential. As a result, the gates of both the output stage MOS transistors Q15 and Q16 are biased in the direction of turning off, and negative feedback is applied in the direction of reducing the through current.

The above negative feedback operation will be described more specifically. For ease of explanation, the following assumptions are made. First R5
= R6, and VDD / 2 is obtained at the node N3. Also, R1 = R2 = R3 = R4, p-channel MOS transistors Q10 and Q13 have the same size, and n-channel MOS transistors Q9 and Q14 have the same size. The constant current sources I2 and I2 of the first and second differential amplifier circuits 1 and 2
I1 is set to I1 = I2.

FIG. 2 shows the relationship between the voltage and current of the main parts of the first and second current detection circuits 6 and 7 and the reference current source circuit 8. Assuming that the detection currents of the first and second current detection circuits 6 and 7 are I11 and I12 as shown in the figure, these currents cause a voltage VR3 across the resistor R3 and a voltage between the gate and source of the MOS transistor Q13. The voltage VT13, similarly, the voltage VR4 across the resistor R4, the MOS transistor Q14
A voltage VT14 is generated between the gate and the source.

Therefore, a voltage expressed by the following equation 3 is applied between the gates of the MOS transistors Q9 and Q10 of the reference current source circuit 8.

[0026]

## EQU3 ## VR3 + VT13 + VT14 + VR4

The gate-source voltage of the MOS transistor Q9 of the reference current source circuit 8 is VT9, the gate-source voltage of the MOS transistor Q10 is VT10, and the resistance R
If the voltages at both ends of R1 and R2 are VR1 and VR2, respectively,
The following Equation 4 is obtained in relation to Equation 3.

[0028]

VT9 + VR1 + VR2 + VT10 = VR3 + VT13 + V
T14 + VR4

From the relationship between the element dimensions described above, VT13
= VT10 and VT14 = VT9.
Is rewritten as

[0030]

## EQU5 ## VR1 + VR2 = VR3 + VR4

Assuming that the currents of the MOS transistors Q9 and Q10 of the reference current source circuit 8 are I9 and I10, the following equation (6) is obtained from the equation (5).

[0032]

## EQU6 ## R1 ・ I9 + R2 ・ I10 = R3 ・ I11 + R4 ・ I12

By the way, since the currents I9 and I10 have no other branch path, I9 = I10 and R1 = I10 as described above.
Assuming that R2 = R3 = R4, the following equation 7 is obtained from equation 6.

[0034]

I9 = I10 = (I10 + I12) / 2

As described above, the common reference current I9 = I10 of the first and second current mirror circuits 3 and 4 is equal to the first and second current mirror circuits 3 and 4.
Is a value proportional to the sum of the detection currents I11 and I12 by the current detection circuits 6 and 7. The detection currents I11 and I12 are respectively proportional to the collector currents of the output stage MOS transistors Q15 and Q16. In other words, the common reference current I9 = I10 is proportional to the through current of the output stage.

In this way, the reference current controlled according to the through current of the complementary output circuit 5 is provided as the active load current of the first and second differential amplifier circuits 1 and 2, so that the through current increases. In this case, the first and second differential amplifier circuits 1 and 2
The two MOS transistors Q5 and Q6 both act to turn on deeply, and a negative feedback is applied so as to suppress the through current of the complementary output circuit 5. The first and second differential amplifier circuits 1 and 2 are set so that a constant current flows by the constant current sources I2 and I1, respectively. The through current of the circuit 5 is controlled.

For example, assuming that the output potential of this operational amplifier circuit is substantially at the intermediate potential of the power supply VDD, the detected current is I11
= I12. Also, the first and second differential amplifier circuits 1 and 2
The currents IQ5 and IQ6 of the active load transistors Q5 and Q6 of the
9, IQ6 = I10 and I9 = I10, so that one transistor Q3 of each differential transistor pair
The currents IQ3 and IQ4 of Q4 are given by the following equation (8).

[0038]

[Equation 8] IQ3 = I11 = I12 = IQ4

That is, the detection currents I11 and I12 are equal to the currents IQ3 and IQ4 of the first-stage differential amplifier circuits 1 and 2, ie, the currents of the output-stage MOS transistors Q15 and Q16 are stable at N times these values. It has become.

As is readily apparent from the above description, the first and second current detection circuits 6 and 7 and the reference voltage source circuit 8
Are the MOS transistors Q15 and Q15 of the complementary output circuit 5.
Since the 16 current difference components do not have a non-feedback effect, they do not affect the amplification factor for the differential input signal. For example, when the potential of one input terminal IN1 rises with respect to the other input terminal IN2, the output terminal N
1 acts to turn on the output stage MOS transistor Q15 when the potential drops, and in the second differential amplifier circuit 2, the output end N2 acts to turn off the output MOS transistor Q16. Then, the differential amplification of the output stage push-pull operation, in which the potential of the signal output terminal OUT rises, is performed.

[0041]

As described above, according to the present invention, the output stage is a complementary circuit, the current of the output stage is detected, and the variation of the through current of the output stage is suppressed in the first-stage differential amplifier circuit. By performing such feedback, the operational amplifier circuit of the push-pull operation can have a function of stabilizing the output stage current.

[Brief description of the drawings]

FIG. 1 shows an operational amplifier circuit according to one embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of current control according to the embodiment.

FIG. 3 shows a conventional operational amplifier circuit.

FIG. 4 shows an operational amplifier circuit provided with the circuit of FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st input stage differential amplifier circuit, 2 ... 1st input stage differential amplifier circuit, 3 ... 1st current mirror circuit, 4 ... 2nd current mirror circuit, 5 ... Complementary output circuit, 6 ... Reference numeral 1 denotes a current detection circuit, 7 denotes a second current detection circuit, and 8 denotes a reference current source circuit.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁶ identification code FI H03K 17/687 H03K 17/687 F 19/0948 19/094 B (58) Investigated field (Int.Cl. ⁶ , DB name) H03K 17/16 H03F 3/45

Claims (2)

(57) [Claims] A first input stage differential amplifier circuit having an active load by an n-channel differential MOS transistor pair and a p-channel first current mirror circuit; a p-channel differential MOS transistor pair and an n-channel differential MOS transistor A second input stage differential amplifier circuit having an active load by a second current mirror circuit and connected in parallel with the first input stage differential amplifier circuit; and a gate formed by an output of the first input stage differential amplifier circuit. The gate of the transistor is controlled by a p-channel output stage MOS transistor having a drain connected to the signal output terminal and an output of the second input stage differential amplifier circuit, and an n-channel drain having a drain connected to the signal output terminal. A complementary output circuit having an output stage MOS transistor; and a gate-source bias same as that of the p-channel output stage MOS transistor. A first current detection circuit for obtaining a detection current proportional to the current of the p-channel output stage MOS transistor using a given p-channel current detection MOS transistor; A second current detection circuit for obtaining a detection current proportional to the current of the n-channel output stage MOS transistor using an n-channel current detection MOS transistor to which a source-to-source bias is applied; and the first and second currents A current source MOS transistor controlled by an output of the detection circuit;
And a reference current source circuit for obtaining a reference current proportional to the sum of the detection currents of the first and second current detection circuits as a common reference current of the second current mirror circuit. 2. The circuit according to claim 1, wherein the ratio of the channel width to the channel length of the p-channel current detection MOS transistor is one of the ratio of the channel width to the channel length of the p-channel output stage MOS transistor. / N (however, N
> 1) to obtain a detection current of 1 / N of the collector current of the p-channel output stage MOS transistor, wherein the second current detection circuit is configured to output the n-channel current detection MOS transistor. Is set to 1 / N of the ratio of the channel width to the channel length of the n-channel output stage MOS transistor, and 1 / N of the collector current of the n-channel output stage MOS transistor.
2. The operational amplifier circuit according to claim 1, wherein an N detection current is obtained.