JP2875296B2 - Processor system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a peripheral circuit control method suitable for shortening a machine cycle or a bus cycle.

[Conventional technology]

Conventionally, in a computer system, a peripheral control circuit or a bus controller operating in synchronization with the CPU by a basic clock applied to the CPU sends control signals necessary for the peripheral system to control peripheral circuits of the CPU. The system uses the signals to perform necessary operations (for example, generate access signals to memory and I / O), and to exchange data between the CPU and memory and I / O. . A bus controller or the like may have a plurality of functions by classifying the functions, but usually has a structure in which one is used to control many parts in the system.

As a conventional technology example, Intel Micro Processor
AND PARIS FALLAL HANDBOOK BOREAM I-
Microprocessor (intel Microprocessor and Perip
heral Handbook Volume I-Microprocessor) (Document No.I
SBN1-55512-062-8) There is a system shown in FIGS. 31 and 32 of 3-34 and 3-35. FIG. 31 shows a basic system having a local bus centered on one bus controller (Bus Controller) and one CPU, and a clock (CLK) serving as a reference for the operation of the system is a clock generator (CLK). Clock Generator) and input directly to both the bus controller and the CPU. FIG. 32 shows a system configuration for a special case of controlling a multi-bus, which is a system bus, except that a bus arbiter (Bus Arbiter) for generating a signal necessary for controlling the multi-bus is added. It has a structure basically equivalent to FIG. 31 of the above-mentioned document. The CLK signal from the clock generator is also directly input to the bus arbiter. Further, a bus arbiter (Bus Arbiter) is a signal for controlling a bus controller (Bus Controller) (for example, a bus arbiter).
AEN signal), which is serially input to the bus controller (Bus Controller). In each of these basic systems, various sub-control systems in the system and subsystems on the bus are controlled using the control signals of the control system described above.

The system configuration is shown in Fig. 31 and Fig.
A basic system having both a local bus and a system bus in combination with FIG. 32 and distributing functions to the control of the local bus and the system bus and providing a bus control system is also possible. However, each bus is controlled by one bus control system.

[Problem to be Solved by the Invention] In the above-mentioned conventional technology, the same (or equivalent) clock as that generally applied to the CPU is used as a synchronization signal to the peripheral control circuit and the bus controller, and the further progress is made. No clock of phase (signal transition occurs earlier in time) is used. For this reason, the delay time of the control signal output from the peripheral control circuit or the bus controller is delayed by the amount of passing through the peripheral control circuit or the bus controller with respect to the reference clock given to the CPU. Therefore, in a peripheral system using the same, a further delay time (a gate delay or a delay caused by a machine cycle) is generated in the process of generating a specific access signal to a memory or the like, and a high-speed operation is performed. There is a problem that a machine cycle or a bus cycle cannot be realized. Also, 1
In a system in which one peripheral control circuit or a bus controller controls a peripheral system, there are problems such as a heavy signal load, which delays a signal, and a problem that a signal line becomes too long to be electrically stable. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor system capable of shortening a machine cycle or a bus cycle of a computer system and further increasing the speed of the system.

[Means for solving the problem]

In order to achieve the above object, a processor system of the present invention includes a CPU, a subsystem accessed by the CPU, a signal controller controlling access to the subsystem, and a signal controller corresponding to the state of the CPU. And a machine state controller for providing a reference control signal obtained by providing a system clock to the machine state controller,
The machine state controller generates a reference clock serving as a reference of the operation of the CPU delayed with respect to the system clock, and a reference of an access timing from the CPU to the subsystem based on operation information from the CPU. And the generation of a reference control signal
The CPU receives the reference clock generated by the machine state controller, and operates based on the reference clock.The signal controller receives the reference control signal generated by the machine state controller and receives the reference control signal. Generating an access timing from the CPU to the subsystem in synchronization with a clock signal;
The CPU controls access to the subsystem.

Further, the processor system of the present invention is configured to control a CPU operating based on a reference clock, a data input / output device accessed by the CPU, and a data input / output operation between the data input / output device and the CPU. A processor system comprising: an input / output controller for generating an access control signal of the same; and a machine state controller for providing the input / output controller with a reference control signal serving as a reference for data input / output control. The machine state controller generates a reference clock which is a reference of the operation of the CPU delayed with respect to the system clock, and an access timing from the CPU to the subsystem based on operation information from the CPU. And the generation of the reference control signal, which is the reference for The CPU receives the reference clock generated by the machine state controller, operates based on the reference clock, and the input / output controller receives the reference control signal generated by the machine state controller, and An access timing from the CPU to the subsystem synchronized with a reference clock signal is generated to generate an access control signal of the CPU to the data input / output device.

Further, the processor system of the present invention includes a CPU operating based on a reference clock, a memory system accessed by the CPU, and a memory control signal for controlling a data input / output operation between the memory system and the CPU. And a machine state controller that provides the memory access controller with a reference control signal serving as a reference for data input / output control, a system clock provided to the machine state controller, The machine state controller generates a reference clock serving as a reference of the operation of the CPU delayed with respect to the system clock, and serves as a reference of an access timing from the CPU to the subsystem based on operation information from the CPU. Parallel generation of reference control signal The CPU receives the reference clock generated by the machine state controller, operates based on the reference clock, and the memory access controller receives the reference control signal generated by the machine state controller. hand,
Generating an access timing from the CPU to the subsystem synchronized with the reference clock signal,
The access control signal to the data input / output device is generated.

In the above processor system, the machine state controller may be separately provided in the CPU and the signal controller, the input / output controller, or the memory access controller.

[Action]

According to the above means, the reference clock supplied to the CPU and the reference control signal supplied to the signal controller, the input / output controller or the memory access controller are both based on the system clock input to the machine state controller by the machine state controller. Are generated in parallel. For this reason, a large delay based on the gate delay is unlikely to occur between the reference clock and the reference control signal, and the delay can be easily adjusted in the machine state controller.

Therefore, it is not necessary to design an access time longer or insert an extra CPU wait time due to the delay time of the reference control signal with respect to the reference clock, and it is possible to reduce a machine cycle or a bus cycle.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a block diagram of the present invention. Here, it consists of two local control blocks (LCBs) 17 and 18. Local control block (LCB0)
17 includes a machine state controller (MSC0) 3, a central processing unit (CPU) 4, and a sub system (SUBS
Signal (LCTL0) 21 for controlling access to YS0)
Has a local controller (LC0) 5 for generating the same. On the other hand, another local control block (LCB1) 18 has another machine state controller (MSC).
1) and a local controller (LC1) 14 for generating a signal (LCTL1) 22 for controlling access from the CPU to the subsystem (SUBSYS1). Data bus for exchanging information between CPU and subsystems,
Although the address bus and control bus are not shown in the figure, they are actually connected to the subsystems 19 and 20 directly or via a bus buffer or the like. The machine state controllers 3 and 13 are supplied with a control signal line 11 from the CPU. The clock (SCLK) 2 which is a reference of the operation of the machine state controller is not in phase with the clock input to the CPU but has a phase advanced from the clock input to the CPU. It is driven and input to two machine state controllers 3 and 13. The reference clock (CLK) 6 input to the CPU or used for control is generated by the machine state controller (MSC0) 3 and is accurately managed with respect to the delay of the clock (SCLK) 2. Since the reference of the AC timing in the system depends on the operation timing of the CPU, the clock (CLK) 6 is important as a reference clock for system control. The AC timing, such as the timing of generating a signal from the CPU and the timing of inputting information to the CPU, are all defined by a clock (CLK) 6.
The other machine state controller (MSC0) 3 includes a local controller (LC0) 5 and a necessary control signal (CTL0) 1
2 and exchange necessary reference signals 7, 8, 9, 10 (7-PCLK,
8- ▲ ▼, 9-PCLKC, 10- ▲ ▼), etc. to the local controller (LC0) 5. On the other hand, in the local controller block (LCB1) 18, similarly, the machine state controller (MSC1) 13 is independently connected to the local controller (LC1) 14 and necessary control signals (CTL).
1) Exchange 16 and provide the required reference signal 15 to the local controller (LC1) 16. If the signal reference must be strictly controlled, the machine state controller (MSC) in one of the local control blocks will be the reference and some reference signals (CLK, PCL
K) or a control signal (CTL) to another local control block (LCB), which may be used by the local controller (LC) in the local control block (LCB).

Next, the features and advantages of the present invention will be clarified by comparison with the conventional example.

FIG. 2 shows a conventional configuration example of a peripheral controller centering on a CPU 4 having the same system functions as the functions shown in FIG. The clock (CLK) 6 is directly driven by the clock driver 1 and input to the CPU 4 and the machine state controller (MSC) 3. The machine state controller (MSC) 3 exchanges necessary control signals 11 with the CPU 4 and uses these signals and the reference clock (CLK) 6 to control signals (CTL) necessary for peripheral control.
And a reference signal 15 are generated. Each of the local controllers (LC) 13, 14 has a corresponding subsystem (SUB
In order to generate signals (LCTL) 21 and 22 necessary for controlling the SYS) 19 and 20, a basic control signal (CTL) 12 required is exchanged with the machine state controller (MSC) 3. The machine state controller (MSC) 3 is generally one, and all the local controllers (L
Supply the control signal (CTL) required for C).

FIG. 3 shows the generation timing of the reference signal and the control signal in the conventional example shown in FIG. The system clock (SCLK) is delayed by a transit delay time (including a delay on the line, and a delay time on the line in the future, including a delay time on the line) td7 of the driver 1 and becomes a reference clock (CLK). ) 6. The machine state controller (MSC) 3 generates a PCLK signal, which is one of the reference signals, at the rise of the state 0 (S0), and also outputs the PCLK signal before being output to the outside inside the machine state controller (MSC) 3. Used, State 1 (S1)
The control signal (CTL) falls with reference to the rise of the internal PCLK signal. The delay time of the control signal (CTL) for the PCLK signal is td2. State 0
The total time from the rise of (S0) to the output of the control signal (CTL) from the machine state controller (MSC) 3 is td6 + td2. Local controller (LC)
Td6 needs to be synchronized using a clock (CLK) to generate the local control signal (LCTL) needed to control the subsystem (SUBSYS).
+ Td2 is a value close to or longer than the cycle of each state, and a sufficient set amplifier time for latching may not be obtained. FIG. 3 shows an example. Local controller (LC) is in state 1 (S1)
Since the control signal (CTL) cannot be latched at the falling edge of the signal, the signal is latched at the rising edge of the state 2 (S2) to generate the local control signal (LCTL) (active L0). At this time, the local control signal (LCTL) falls with a delay of td4 from the rising of the state 2 (S2). Using this, the subsystem (SUBSYS) is accessed and data is transferred to the CP
Suppose you type in U4. Assuming that the timing at which the CPU 4 loads data into the CPU 4 is the rising edge of the state 4 (S4), the access time from when the local control signal (LCTL) changes to the active L0 is the local control signal (LCTL).
When the control signal (CTL) output from the machine state controller (MSC) 3 rises (inactive), it immediately rises to Hi level (becomes inactive). The timing when the control signal (CTL) rises is
The reference signal PCLK rises in state 5 (S5) and is delayed by td3. In response to this, since the timing at which the local control signal (LCTL) rises is delayed by td5, it has a total delay time of ht1 (td6 + td3 + td5) measured from the reference clock (CLK) 6. If this is too large, the time at which the next access cycle can be started will be delayed, and in the example of FIG. 3, the state will be after state 7 (S7).

The above is the conventional example. If the access time dt1 is too small, the access to the subsystem (SUBSYS) cannot be made in time, and an extra Wait State must be inserted into the CPU 4. Also, if the hold time ht1 is too long,
The number of accesses within a unit time cannot be increased. In any case, the data transfer throughput between the CPU 4 and the subsystems (SUBSYS) 19, 20 and the like is reduced.

On the other hand, FIG. 4 shows a case where a function equivalent to the control signal generation function shown in FIG. 3 is realized in the embodiment shown in FIG. The difference from the conventional one is that the machine state controllers (MSCs) 3 and 13 do not operate based on the clock (CLK) 6 input to the CPU 4, but the system clock (SCL) whose phase is further advanced.
K) It operates on the basis of 2. Here, for simplicity, the operation timing of the machine state controller (MSC) 3 will be described as shown in FIG.

The system clock (SCLK) 2 is input to a machine state controller (MSC) 3 and then delayed in the machine state controller (MSC) 3 to generate a reference clock (CLK) 6 delayed by td7. When relative delay control between output signals is required as in this method, generally, the machine state controller (MSC) 3 itself is integrated into an IC, and the gates constituting the circuit of the machine state controller (MSC) 3 are integrated. It is necessary to make sure that the delay does not vary so much.

In the present invention as well, the machine state controllers (MSCs) that are arranged in a distributed manner are each integrated into an IC, and if the current IC manufacturing process is used, the relative number of signals output from the same IC in units of the number of gate passage stages is reduced. It is possible to manage the delay difference. Thus, the machine state controller (MSC) 3 operates based on the system clock (SCLK) and the CPU 4 operates based on the clock (CLK).
For example, the relative delay time of the reference signal PCLK with respect to the clock (CLK) is td1 = td6-td7 (td6 is the PCLK with respect to SCLK.
Signal delay time). In the conventional system, td6 itself is the delay time from the clock (CLK),
This means that the signal can be output earlier by td7 compared to the conventional method. Due to the relative relationship between the signals, the PCLK signal is delayed by td1 from the clock (CLK) (td1
> 0) If it is necessary, the control is performed for a long time in an IC having a built-in machine state controller (MSC) 3 so as to satisfy the relative delay relationship. Similarly, the control signal CTL is delayed by td1 + td2 with respect to the rising edge of the clock (CLK) in the state 0 (S0). This is because the delay time td6 + td2 was conventionally provided, and the delay time td7 (td1 = td1 = td6-td7) is also canceled according to the present invention, and the control signal (CTL) is earlier by that time. Can be turned off (active L0). From the result of these delay time reductions, the control signal CTL is activated during the period of the state 1 (S1).
And the control signal CTL can be latched at the fall of the state 1 (S1). After that, the delay time until the local control signal LCTL is output from the local controller (LC) 5 is set to td4 as in the related art, and the CPU 4
Assuming that the timing for reading data from the subsystem is also the rising timing of state 4 (S4) as in the prior art, the effective access time to the subsystem (SUBSYS) 5 is at2 = 3 states-td4. This value indicates that an access time longer by one state than in the conventional method can be secured. Hold time ht
Also in 2, the control signal (CTL) is reduced by an amount corresponding to the rise (inactive) by the time td7 earlier. That is, ht2 = ht1-ht7, and the next access cycle can be started after state 6 (S6). Therefore, the access cycle for one state can be shortened compared to the conventional example of FIG.

As in the above-described conventional example, the case where the total delay time does not fall within one machine state and two machine states are required for signal processing is a problem that frequently occurs as the machine cycle frequency is increased. This problem becomes a net, and in many cases, the machine cycle frequency cannot be increased.
According to the present invention, since the delay time with respect to the reference clock can be reduced, the system can be operated at a higher machine cycle frequency.

In the embodiment shown in FIG. 1, the local controller (LC) is provided independently of the machine state controller (MSC). Therefore, in this configuration, each local controller block (LCB) has multiple local controllers (LBs).
C) can be arranged in combination and controlled by one machine state controller (MSC). Therefore, when designing an electronic board, a flexible circuit configuration can be newly constructed, so that it is versatile. However, the local control block (LC
If the function of B) is clarified and it is not necessary to change it in the future, the machine state controller (MSC) and some or all of the peripheral local controllers controlled by them (parts that do not need to change the circuit) are integrated into one. It may be integrated in an IC chip. The effect in this case will be described with reference to FIG.

FIG. 5 realizes the same function as the conventional example shown in FIG. 3, as in FIG. The difference from the example of FIG. 4 is that the local controller (LC) 5 and the machine state controller (MSC) 3 are built in the same chip. Others are the same as the configuration of the embodiment of FIG. 1 and the conditions set in FIG. Local controller (LC) 5
Is included in the IC of the machine state controller (MSC) 3, and therefore, regarding the control signal (CTL), the internal control signal (INCTL) of the same function in the IC is transmitted to the local controller (L).
C) Available in 5. The internal control signal (INCTL) obviously changes at a time earlier than the externally output control signal (CTL) (information is obtained earlier than the CTL by the output buffer delay time td13), and is thus input to the CPU4. Change at a time earlier than the clock (CLK) (the phase is advanced)
It can be controlled inside the IC by C internal clock (MSCINCLK). Internal clock (MSCINCLK)
Is changed from the rise of the internal clock (MSCINCLK) in state 1 (S1) to the local control signal (LCTL), assuming that it changes earlier than the clock (CLK) by the time td10.
Even if the time td4 until becomes active is the same delay time as the example shown in FIG. 4 (actually, the gate delay can be reduced by configuring the circuit only inside the IC, so td4 is 4 is generally smaller than the example in FIG. 4),
The relative delay time of the local control signal (LCTL) with respect to the clock (CLK) is td4 '= td4-td10. Therefore,
By incorporating a local controller (LC) inside, it is possible to change the local control signal (LCTL) at an earlier time than by externally configuring logic. with this,
The access time at3 (at2 + td10) is also the fourth for the time of td10.
It is possible to secure a longer time than in the example shown in the figure, to obtain more margin for accessing the subsystem (SUBSYS), and to operate the system at a higher machine cycle frequency. Hold time
The same applies to ht3. The internal control signal (INCTL)
Local control signal (LCTL) generated using internal control signal (INCTL) because it rises (turns inactive) earlier by td13 time than external control signal (CTL)
Is relative delay td5 ′ (td5 ′) with respect to the external control signal CTL.
= Td5-td13) with a delay time. Therefore, the hold time ht3 = ht2-td13,
It can be made smaller by the time td13 than the embodiment shown in the figure. If the hold time ht3 is within one state, the next access cycle can be started from the falling time of state 5 (S5).

The above operations and effects are at least based on the reference clock (SC
LK) is input to the machine state controller (MSC) first, and the CPU is driven by the reference clock (CLK) adjusted inside the machine state controller (MSC). However, as shown in FIG. 6 (b), when a method of controlling all the local controllers (LC) of one machine state controller (MSC) is employed, the following problem occurs.

1) The load of the reference clock (CLK, PCLK, etc.) and control signal (CTL) becomes heavy (in FIG. 6 (b), each signal line (CLK
And CTL) are connected to three local controllers (LCs), respectively, so that the signal delay time increases.

2) Since the signal lines for the reference clock (CLK, PCLK, etc.) and control signals (CTL) are long, delay management and waveform management of many signal lines (effects of signal reflection, ringing due to line inductance components, etc. Suppress)
Is required.

The above problems lower the operating frequency of the system and lower the reliability of the system. Therefore, the present invention employs a distributed machine state control system having the system structure shown in FIG. According to this, one or a plurality of machine state controllers (MSCs) exist for each local controller (LC) or a local controller (LC) existing in a local control block (LCB) to distribute load. Can be planned. In this method, the only signal that needs to be subjected to delay management and waveform management is the reference clock, SCLK, and the load of the reference clock (CLK, PCLK, etc.) and control signal (CTL) generated from the machine state controller (MSC). Are also dispersed, and the problem of signal delay due to the load is reduced. Also, as the size of the system increases, the area to be physically controlled increases, and the distribution range of the local controllers (LC) also increases. Therefore, a single machine state controller (MSC) can control a plurality of local controllers (LCs). Control, the machine state controller (M
Since it is practically impossible to integrate the SC) and the local controllers (LC), it is difficult to obtain the effects shown in FIGS. 4 and 5. However, if the distributed machine state control method of the present invention is used, it is only necessary to integrate each local control block (LCB) in one IC chip, and the effects shown in FIGS. 4 and 5 can be easily obtained. .

Each local control block (LCB)
Subsystems or signal controllers (LCs and MSCs) that are strongly related on signals are put together, or components that are close to each other on the circuit layout are put together. It is best to configure the exchange of signals between the local blocks as small as possible.

FIG. 7 shows an embodiment using the distributed machine state control method of the present invention in a large-scale system. This example shows two large processor blocks, MCPBLOCK
26 and MSPBLOCK25. Each processor block is
It consists of several local control blocks, each containing one or more machine state controllers (MSCs). In FIG. 7, M
Only the internal structure of SPBLOCK25 is described in detail.

The clock generator 23 generates an original clock signal serving as a reference of the system. The clock signal is transmitted by signal line 28 to clock distributor 24, which generates various system clocks which are the reference clocks of the system. There are roughly two types of system clocks, FSCLK (Fast SCLK) that changes at the earliest time.
And SCLK which is a clock slightly delayed from FSCLK. In FIG. 7, 2-6 (EFSCLK
1) and 2-7 (EFSCLK2).
-2,2-3,2-4,2-5. Of these, SCLK2-1 is MSPB
Reference system clock dedicated to LOCK, SCLK2-1 is MCP
This is a reference system clock dedicated to BLOCK. SCLK2-1 (ES
CLK1), SCLK2-4 (ESCLK2) and SCLK2-5 (ESCLK3) are reference system clocks supplied externally. Also, FSCLK
There are 2-6 and 2-7 (EFSCLK2).
2-7 is supplied to the outside, and FSCLK2-6 are output to the outside as EFSCLK1 after being used by MSPBLOCK25. 27-1,27
-2,27-3 is a terminating resistor that adjusts the impedance of the signal line and stabilizes signal transmission. Clock distributor
Reference numeral 24 denotes a clock driver 1-1 (outputs SCLK2-1), 1-2 (outputs SCLK2-2), 1-3 (outputs SCLK2-3) corresponding to each system clock, 1-4 (output SCLK2-4), 1-5 (output SCLK2-5), 1-6 (output SCLK2-6)
) And 1-7 (output SCLK2-7). Clock drivers 1-1 to 1-5 are drivers 1-8
, 1-6, 1-7 and the driver 1-8 are directly driven by the clock signal line 28 from the clock generator 23. Therefore, SCLK1-1 to 1-5
Is delayed by the time required to pass through the driver 1-8 as compared with FSCLK1-6 and FSCLK1-7. By adjusting the delay in the clock distributor, it is possible to generate a system clock having a phase that is different from the reference clock (CLK) applied to the CPU in two stages with a certain degree of delay relationship. Of course, in principle, a system clock having many stages of phase differences can be generated in a similar manner. By appropriately using these various system clocks and supplying them to each machine state controller (MSC) of each local control block (LCB), finer relative delay control can be realized.
In the embodiment of FIG. 7, LSCLK2-6 are connected to LCC3 MSC3-1 and LCB4.
Supplied to MSC4. As a result, MSC3-1 and MSC4
Supplies the required control signal slightly earlier than other machine state controllers (MSCs).

MSPBLOCK has 6 local control blocks LC
It consists of B0 to LCB5. LCB0 is a block including a CPU, and includes one machine state controller MSC0 and MSC0.
Two local controllers LC00 (5-2) that cannot be incorporated in C0 or have no particular advantage even if incorporated
LC01 (5-2). In MSC0, supply to CPU and MSP
An auxiliary reference signal such as a clock CLK6-1 serving as a reference for the entire BLOCK, a clock CLK6-2 serving as an inverted clock thereof, and PCLK7 and PCLK9 is generated. In other local control blocks LCB1 to LCB5, the local control function that can be absorbed in the machine state controller (MSC) is M
The effect in the AC timing described with reference to FIGS. 4 and 5 is effectively used by incorporating it in the SC. Since LCB0 has a CPU at the center of the system, it can be said that it is a block that serves as a reference for the operation timing of the system. For the local control blocks LCB1-5, only the machine state controller (MSC) is described for simplicity. Each local control block (LCB) has one or more machine state controllers (MSCs) including a local controller (LC) having necessary control functions. The local controller (LC) described with reference to FIG. The system operation in a high-speed machine cycle is enabled by obtaining the effect on AC timing by integrating it into a machine state controller (MSC) and integrating it into an IC. Each local control block (LCB) has a system clock 2 distributed by a clock distributor 24.
-1 and 2-6 are provided. These system clocks are managed by signal skew, and the time of arrival at each machine state controller (MSC) is clearly defined to a certain extent (usually, it is preferable to reach the synchronization clock as much as possible, In some cases, it is sufficient if the relative relationship is clear). As explained earlier, system clock 2
The system clock 2-6 changes at a slightly earlier time than the -1. System clock 2-1 is LC
B0, LCB1, LCB2 and LCB5 are supplied to the system clock 2
-6 is supplied to LCB3 and LCB4. Therefore LCB3 and
The control signal in the LCB4 can be generated slightly earlier than the control signal in the other local control block (LCB), thus achieving fine AC timing control in the local control block (LCB) or the entire system. ing. In addition, each machine state controller (MSC) in LCB1 to LCB5 has a CPU of LCB0.
Signal line 11 for exchanging minimum necessary control signals with
Are connected, and necessary control signals are generated in each local control block (LCB) based on the information on the signal line 11 with reference to the system clock.
The control signals generated in each local control block (LCB) are used in principle in that local control block (LCB), but signals that do not matter so much even if the signal line is long are used for other local control blocks. It is naturally possible to exchange some signals between the local control blocks (LCB) by obtaining them from the block (LCB) or sending them to other local control blocks (LCB).

By using the present invention, in a large-scale system as shown in FIG. 7, not only the operating frequency can be improved, but also the effect of shortening the length of the critical signal line and the load on the critical signal line can be reduced. Can be obtained at the same time. This leads to higher reliability by electrical stabilization, delay due to a time constant circuit on wiring, and absolute delay of a signal line (delay physically determined by the speed of light). And the operating frequency is further increased (the machine cycle time is further reduced).

Next, several embodiments of the most popular processor system using this method will be described.

FIG. 8 shows a memory system 103, a machine state controller 102 having a function for controlling the memory system 103, a CPU 10
The figure shows a distributed machine state control type system having two machine state controllers with a machine state controller 101 controlling 0. In this example, the machine state controller 101 sends the CPU 100 a reference clock CLK1 generated from the system clock SCLK1.
2 and the task of creating an enable signal ▼ 14 for permitting access to the memory using the signal on the address bus 105. If ▲ ▼
If l4 and CLKl2 are configured by flow-through logic, they have no relation to the machine state operation.
The function of the portion (a) can be constituted by the clock driver 106 and the decoder circuit 105 having the delay control function as shown in (b). That is, in that case, there is no need to perform machine state control. The machine state controller NSC102
3. Supply the necessary control signals to 3. From CPU100, CPU100
Control signal ▲ ▼ l3 which is the reference to determine the state of
And R / 15 are input to the machine state controller MSC102. From these and SCLK1, the memory system 103
Control signals ▲ ▼ l8 and ▲ ▼ l9 for performing the control of. Also, the machine state controller 102
An address latch signal ALEl7 is supplied to a latch circuit 104 for latching necessary address information to the memory system 103 from an address bus 105. In this example, the latch circuit 104
Is also performing ▲ ▼ l4 at the same time. Since the generation of ALEl7 is possible in the MSC101, the latch circuit
The process may be performed in the MSC 101 including the process 104. Further, it is also possible to supply the address 105 to the MSC 102 and to incorporate a function of generating an address 14 and latching the address to be given to the memory system. In that case, set the local control section to MSC102
Since these are all built-in, the necessary control signals and address signals can be supplied to the memory system 103 at an earlier timing for the above-mentioned reason, and the access time to the memory can be shortened.

FIG. 9 shows a conventional processor system. CLKl2 is supplied as a reference clock to both the CPU 100 and the machine state controller MSC108. Also, l ▼ 14 is generated by the decoder circuit 105 and supplied to the memory system 103 latched by the latch circuit 104 together with a necessary address. Functionally, it is completely the same as the processor system shown in FIG. 8, but it is inferior to this method in securing access time to the memory as described above. The detailed examination and comparison of the timing will be described later.

FIG. 10 shows a case where the two machine state controllers MSC102 and MSC101 shown in FIG. 8 are integrated into one machine state controller MSC109.
If the MSC 109 is composed of one IC chip, CLK12, which is a reference clock to the CPU 100, and ALE11, ▲ 18, ▲, which are reference control signals to the memory system 103 and the latch circuit 104.
▼ It is possible to more accurately adjust the phase relationship and output timing with l9 and the like. That is, since the variation in switching speed of each transistor in one IC chip is very small, it is possible to finely adjust the delay between each signal, and to perform more critical timing design. As in the case of FIG. 8, the latch circuit
By incorporating 104 into MSC109, the reference clock CLK
It is also possible to output the reference control signal and the address signal to the memory system 103 at an earlier timing with respect to l2.

FIG. 11 shows that the memory system 110 is added to the processor system of FIG.
Machine state controller MSC112
And machine state control is distributed. In this example, an enable signal ▲ ▼ 14 for permitting access to the memory system 103 and an enable signal ▲ for permitting access to the memory system 110
Both ▼ and 13 are generated by MSC112. Therefore,
The necessary address information is input to the MSC 112 from the address bus 105 and used for decoding. When the memory system becomes huge, the load of control signals and address signals applied to it becomes large (because the number of memory ICs increases). Therefore, by using the distributed machine state control of the present method to distribute the load, it is possible to reduce the timing delay due to the load. This was elaborated earlier. In this example, the memory system 10
3 and assign MSC111, control signal ALEl7, ▲ ▼ l8,
▲ ▼ l9 and supply MSC11 to memory system 110
Assign 2 and control signals ALE12, ▲ ▼ 10, ▲ ▼
11 are supplied. If both memory systems 103 and 110 have the same size, the reference clock CLK
The delay of each control signal is almost the same as that of FIG. 10, and it is considered that there is almost no increase in the timing delay due to the load.

Next, considering the delay of the control signal output from each MSC in the case of using the distributed machine state control with respect to the reference clock CLK, the effect will be clarified concretely in comparison with the conventional method.

Figures 12 to 16 show MSs integrated into a CMOS process.
When distributed machine state control is performed using multiple C, what is the best (min), standard (typ), and standard (typ) depending on conditions such as ambient temperature, power supply voltage, load, and process variation?
The worst case (max) signal delay is shown. Fig. 12 25
40% process variation in standard environment of ℃, 5V, 30pF
6 is a table showing the case of FIG. In a standard model in which the delay (a) of CLK with respect to SCLK is set to 3 ns and the delay of control signal with respect to SCLK is (b) 6 ns, the best value of control signal delay (c) with respect to CLK is 0.08 ns. The standard value is
3 ns, the worst value is 6.26 ns. In the conventional method, the worst value is 8.4 ns, and at least 2.14 ns indicates that the timing is improved by the present method. Similarly, at 55 ° C,
In the worst case environment of 4.8V, 30pF and process variation 40, the timing improvement by this method can be guaranteed at least 2.4ns.

The above example is for the worst case process variation,
Extremely fast IC chips and extremely slow IC chips
MSCs excluded by 10% or used in the same lot
If all are manufactured, it is possible to reduce the process variation to within 15% using current process management.
The result in that case is shown in FIG. The delay (c) of the control signal with respect to CLK is 4.81 ns at the worst value, and can be controlled within 5 ns. Also, the degree of timing improvement
A minimum of 2.92 ns can be guaranteed compared to the conventional method. Further, if the reference clock CLK is supplied to the CPU by the MSC having a standard delay (typ), the result shown in FIG. 15 is obtained. In other words, the delay (c) of the control signal with respect to CLK is 4.37 ns at the worst value, and the timing improvement over the conventional method is about 3.36 ns.

FIG. 16 illustrates the phase between the reference clock CLK to the CPU and the control signal by controlling the delay of the CLK with respect to the SCLK so that the delay of the control signal with respect to the CLK is about 0 ns at the best (min). It shows the case where it is done. The conditions are the same as those in FIG. 15, but the timing improvement is further improved to about 5.04 ns, and the delay (c) of the control signal with respect to CLK is the worst (max) at 3.35 ns, which is the best value. In an actual system, design is performed under the conditions shown in FIG.

17 and 18 show the delay (c) of the control signal with respect to CLK in the conventional system. FIG.
V, 30pF load, process variation 40%, Fig. 18 shows 55 ℃,
4.8V, 30pF load, process variation 15%.

FIG. 19 shows the timing of each reference clock and each control signal in the embodiment shown in FIG. ▲ ▼
l3 is, CPU 100 is a signal indicating whether to perform a bus cycle (BS) in the next black poke period (L ₀ Akuteibu)
And is generated by the CPU 100. It is assumed that the bus cycle is completed in one clock (for one CLK cycle). Further, it is assumed that SCLK1 and CLK12 have the same frequency, and the relative delay control is performed under the conditions shown in FIG. The condition defines the worst value (max). C
The PU 100 controls the address 105 used in the bus cycle and the control signal R / 15 indicating the read cycle or the write cycle in the CLK period immediately before the bus cycle BC is started.
(L ₀ during writing) and ▲ ▼ l3 are output. As described above, the bus cycle control for generating data required for access one cycle before is called a pipeline bus cycle, and is likely to be widely used in microprocessors and the like that require a high-speed bus cycle in the future.

In FIG. 19, the bus cycle BCO is a write cycle. Machine state controller MSC102
l3 and write enable signal from the R / l5 and SCLK1 Metropolitan to the memory system 103 ▲ ▼ l9 the (L ₀ Akuteibu) ▲ output in ▼. In BC1, the enable signal ▲ ▼ l4 to the memory system is inactive (Hi level), and the memory system 103 is not accessed. B
C3 is a read cycle. Data is read from the memory system 103 to the data bus 107, and is read into the CPU 100 at the time of rising of the state S9. Since this read cycle is the most critical in terms of access timing, this example will be compared with the conventional method.

In this method, the address latch enable signal ALEl7
Is performed in parallel with the generation of CLK1 based on SCLK1, so that the relative delay (td2) from CLK1 is max3.35n
s. The worst delay time (td3) by the latch circuit 104 is 5
If it is set to about ns, the chip select signal ▲ ▼ which activates the memory system 103 (accessible state)
And the total delay time (td2 + td3) for CLKl2 until the address signal for the memory system 103 is determined is 8.3.
5 ns. Also, since the data set-up time (sut) required for the CPU 100 to latch the data read from the memory system 103 therein is about 4 ns, CL
Assuming that the cycle of Kl2 is 37 ns, the time available as the access time of the memory system 103 itself is 24.65 ns. On the other hand, in the conventional example, ▲ ▼ l7
Is generated, the ▲ ▼ signal and the memory system 103
The total delay before the address to address is determined is 12.73ns (7.7
3ns + 5ns), and the available memory access time is
20.27 ns, which is 4.5 ns less. Where ▲ ▼
l8 is a signal that indicates whether to output data from the memory system 103 to the data bus 104 (output data at L _0), assuming shall not affect the access time have been determined fast enough I have.

The 4.5ns improvement is equivalent to 12.2% of the 37ns machine cycle, which is a very large value for a high-speed CPU. In other words, when a memory system having an access time of about 25 ns is used, this method can realize a machine cycle of 37 ns, but the conventional method can realize only a machine cycle of about 41.5 ns. This can improve system performance by 12.2%.

〔The invention's effect〕

According to the present invention, a machine clock or a bus cycle can be shortened by generating a reference clock supplied to a CPU and a reference control signal supplied to another controller in parallel by a machine state controller. Thus, the speed of the system can be increased.

[Brief description of the drawings]

1 is a block diagram showing a processor system of the present invention, FIG. 2 is a block diagram of a conventional controller, FIG. 3 is a diagram for explaining a conventional controller signal generation function, and FIG. 4 is a control of the present invention. Diagram illustrating a signal generation function,
FIG. 5 is a diagram for explaining a control signal generation function using another embodiment of the present invention, FIG. 6 is a diagram showing a system structure of a distributed machine controller of the present invention, and FIG. FIG. 8 shows an embodiment used in a large-scale system,
The figure shows another distributed machine state control type system of the present invention, FIG. 9 shows a conventional processor system, and FIG. 10 integrates the two machine state controllers shown in FIG. FIG.
FIG. 12 shows an embodiment in which a memory system is further added to the processor system of FIG. 10, and FIG. 12, FIG. 13, and FIG.
FIGS. 15, 15 and 16 are diagrams showing the performance of the present invention when the conditions are changed, FIGS. 17 and 18 are diagrams showing the performance of the present invention when the conditions are changed, and FIG. 19 is a diagram showing the present invention. FIG. 13 is a diagram illustrating signal timings according to another embodiment.

Claims (6)

(57) [Claims] 1. A CPU, a subsystem accessed by the CPU, a signal controller controlling access to the subsystem, and a machine state controller for providing the signal controller with a reference control signal corresponding to a state of the CPU. A system clock provided to a machine state controller, wherein the machine state controller generates a reference clock that is a reference of the operation of the CPU delayed with respect to the system clock, and outputs the reference clock from the CPU. Performing in parallel with the generation of a reference control signal from the CPU based on the operation information as a reference for the access timing to the subsystem, the CPU receives the reference clock generated by the machine state controller, Operate based on a reference clock, and The roller receives the reference control signal generated by the machine state controller, generates an access timing from the CPU to the subsystem in synchronization with the reference clock signal, and controls the CPU to access the subsystem. A processor system, characterized by controlling: 2. A CPU that operates based on a reference clock;
A data input / output device to be accessed by the CPU, an input / output controller that generates an access control signal for controlling a data input / output operation between the data input / output device and the CPU, and data input / output to the input / output controller. A machine state controller for providing a reference control signal serving as a reference for input / output control, wherein a system clock is provided to the machine state controller, and the machine state controller is configured to delay the CPU with respect to the system clock. Generation of a reference clock as a reference for the operation of the CPU and generation of a reference control signal as a reference for access timing to the subsystem from the CPU based on the operation information from the CPU, in parallel, the CPU includes: Receiving the reference clock generated by the machine state controller; Operating on the basis of the reference clock, wherein the input / output controller receives the reference control signal generated by the machine state controller, and receives access timing from the CPU to the subsystem in synchronization with the reference clock signal. And generating an access control signal for the CPU to access the data input / output device. 3. A CPU that operates based on a reference clock;
A memory system to be accessed by the CPU, a memory access controller that generates a memory control signal for controlling a data input / output operation between the memory system and the CPU, and a data input / output control to the memory access controller. A machine state controller for providing a reference control signal as a reference, wherein the processor is provided with a system clock and provided to the machine state controller, wherein the machine state controller is a reference for operation of the CPU delayed with respect to the system clock. And a reference control signal serving as a reference of access timing from the CPU to the subsystem based on the operation information from the CPU. The reference mark generated in The memory access controller receives the reference control signal generated by the machine state controller, and operates from the CPU synchronized with the reference clock signal. Generate access timing to the
A processor system for generating an access control signal for accessing a data input / output device of a CPU. 4. The processor system according to claim 1, wherein said machine state controller is provided separately for said CPU and said signal controller. 5. The processor system according to claim 2, wherein said machine state controller is provided separately for said CPU and said input / output controller. 6. The processor system according to claim 3, wherein said machine state controller is provided separately for said CPU and said memory access controller.