JP2870398B2 - Waveform memory address generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform memory address generator for reading desired waveform data by inputting phase data to a waveform memory.

[0002]

2. Description of the Related Art Conventionally, an electronic musical instrument is supplied with waveform data which stores tone waveform sample value data, and supplies phase data which varies in accordance with the pitch of a musical tone to be generated. Some have a built-in sound source that reads out data.

[0003] Some waveform memories store compressed waveform data (compressed waveform data) and others store uncompressed waveform data as they are. The sound source of the electronic musical instrument incorporates a memory system including a plurality of such waveform memories. Therefore, even if the phase data is supplied to the memory system, if the waveform memory corresponding to the address stores compressed waveform data, it takes time to decompress the compressed data, so that the memory system outputs the waveform data. Until the predetermined delay time. On the other hand, if the waveform memory stores uncompressed waveform data, the memory system does not need to decompress, so that the waveform data can be output with almost no delay to the input of the phase data.

That is, the time from outputting an address to a waveform memory and accessing it until an uncompressed linear waveform is obtained differs depending on whether the stored waveform is compressed waveform data or non-compressed waveform data. Normally, compressed waveform data requires a longer time than uncompressed waveform data. Also, the time of the compressed waveform data depends on whether it is based on differential PCM or any compression method such as adaptive differential PCM, delta modulation, linear prediction, other prediction, Percoll filter, subband coating, etc. The delay is not constant. In other words, it is assumed that the memory system in this case includes a waveform memory that stores a plurality of waveforms that require various processes such as compression and modulation, and a processing circuit that performs the processes.

In an electronic musical instrument equipped with such a memory system, when the timing of processing circuits from the time when uncompressed waveform data, which is the material of a musical sound, is obtained until the musical sound is obtained, a certain level is required. It is necessary to obtain waveform data at the timing. Therefore, conventionally, as shown in FIGS. 3 and 4, a delay circuit (delay) is provided on a phase data line or a waveform data line to adjust the output timing of the waveform data, so that the waveform data can always be obtained at a constant timing. Was like that. FIG. 3 is a diagram showing a memory reading device in which a delay circuit is provided on the phase data line side and the output timing of waveform data is adjusted by adjusting the supply timing of phase data.

In FIG. 3, a memory system 1 comprises a compressed waveform memory storing compressed waveform data and an uncompressed waveform memory storing uncompressed waveform data. Here, it is assumed that a decoder for decompressing the compression is provided in the output section in the compression waveform memory. The address counter logic circuit 2 includes a full adder (FA) 21
And a register 22. Full adder 21
Is the frequency number FN corresponding to the pitch of the musical tone to be generated
And phase data PD (Phase D) from the register 22.
data), and adds the two values to the new phase data P
D is output to the register 22. Accordingly, the address counter logic circuit 2 sequentially outputs the phase data PD which sequentially increases in accordance with the frequency number FN. The initial value and the like of the phase data are set in the full adder 21, but the description is omitted.

[0007] The delay circuit 4A receives the waveform data DAT after the phase data integer part INT is input to the compressed waveform memory.
Register 22 is stored for the same time as the time until A is output.
Is to delay the integer part INT of the phase data. The selection circuit (SEL) 5A receives the phase data integer part INT from the register 22 and the delay address DINT delayed by the delay circuit 4, and supplies one of them to the memory system 1 as a read address ADR.

The latch circuit 6 temporarily holds the waveform data DATA from the memory system 1 and
Output to The data processing unit 7 performs interpolation, imparts various effects, and imparts an envelope to the waveform data DATA read from the memory system 1.

FIG. 4 is a diagram showing a memory reading device in which a delay circuit is provided on the waveform data line side to adjust the output timing of the waveform data itself. In FIG. 4, the same components as those in FIG.
The description is omitted. Address counter logic circuit 2
Is composed of a full adder (FA) 21 and a register 21. The full adder 21 receives the frequency number FN corresponding to the pitch of the musical tone to be generated and the phase data PD from the register 22, and outputs the integer part of the sum of the two as the read address ADR to the memory system 1.

The latch circuit 6 temporarily holds the waveform data DATA from the memory system 1 and
Output to The delay circuit 4B delays the waveform data DATA from the latch circuit 6 by the same time difference as the time until the phase data PD is input to the compressed waveform memory or the waveform data DATA is output. The selection circuit (SEL) 5B receives the waveform data DA from the latch circuit 6.
The TA and the delayed waveform data DDATA delayed by the delay circuit 4B are input, and one of them is supplied to the data processing section 7 as waveform data.

[0011]

As described above, conventionally,
A delay circuit is provided in the address signal line or the waveform data signal line to adjust the output timing of the waveform data. However, since the delay circuit must be configured with the number of bits capable of storing the address or the waveform data and the length of the number of stages corresponding to the delay time, the delay circuit occupies a large proportion of the read device in the circuit configuration. was there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in consideration of a problem that a delay time from input of phase data to output of waveform data is reduced from a memory system including a plurality of waveform memories each having a different delay time. It is an object of the present invention to provide a waveform memory address generator capable of appropriately adjusting the output timing of waveform data without increasing the circuit scale when reading out data.

[0013]

SUMMARY OF THE INVENTION A waveform memory address generator according to the present invention is a waveform memory address generator for performing a plurality of time division channel operations, and each storage position corresponds to the plurality of time division channels. The read / write memory is read and written, and the read / write memory accessed by each time slot obtained by dividing each time division channel into a plurality of time slots, and the predetermined time slot in each time division channel, Using phase data updating means for changing the value of the phase data of each time division channel at a rate corresponding to the pitch of the waveform to be generated, and another time slot different from the predetermined time slot in each time division channel The phase data of each time-division channel is sequentially read from the read / write memory, and the read phase data is read. And address generating means for generating an address for accessing the waveform memory on the basis of the data,
Timing adjusting means for changing the storage position of the phase data read by the address generating means in each time-division channel in accordance with the timing at which the address is to be generated.

[0014]

In the read / write memory, phase data for accessing the waveform memory is stored for a plurality of time-division channels, and the data is stored in a tone pitch of a tone generated in each time-division channel by an update operation of the phase data updating means. At a rate corresponding to On the other hand, the address generating means accesses the read / write memory at a time-division timing different from the access to the read / write memory by the update operation, and generates an address of the waveform memory based on the read phase data. The reading of the phase data by the address generating means is completely arbitrary, and since the current phases of all the time-division channels are readable at any time in the read / write memory, the address adjusting means is read by the timing adjusting means. , The timing at which the phase data of each time-division channel is read for generating an address can be adjusted with a simple configuration without adding a delay or the like.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of a memory reading device according to one embodiment of the present invention. In FIG. 1, FIG.
Components having the same configuration as those described above are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the register 22 of the address counter logic circuit 2 in FIG. 3 is replaced with a RAM 32, and several bits of write and read addresses supplied to the RAM 32 are controlled by a full adder 37. That is, the address supplied to the RAM 32 is offset or not according to the offset value.

In this embodiment, the address counter logic circuit 3 comprises a full adder 31, a RAM 32, latch circuits 33 and 34, a counter 35, an AND circuit 36, and a full adder 37. The full adder 31 receives the frequency number FN corresponding to the pitch of the musical tone to be generated and the phase data PD from the latch circuit 33, and outputs a value obtained by adding both to the data input terminal DI of the RAM 32 as new phase data PD. I do.

The RAM 32 inputs the phase data PD from the full adder 31 to a data input terminal, and the full adder 37
Is input to the address terminal,
Latch circuit 3 latches phase data PD from data output terminal DO.
3 and 34. That is, the RAM 32 writes the phase data PD of the full adder 31 at the position of the ram address RADR from the full adder 37, and
From the position of the ram address RADR from
And outputs it to the latch circuits 33 and 34.

The counter 35 counts the operation clock and outputs the count value to the full adder 37. The AND circuit 36 receives the offset value OFS and the output timing signal OT, and outputs logical product data of both to the full adder 37. That is, the AND circuit 36 outputs the offset value OFS to the full adder 37 in synchronization with the input timing of the output timing signal OT. Here, the offset value OFS is stored in the compressed waveform memory as the phase data PD.
Corresponds to the time from input to output of the waveform data DATA. The larger the value, the larger the delay time, and the smaller the value, the smaller the delay time. In addition, the output timing signal OT repeats a high level “1” and a low level “0” within one operation clock.

The full adder 37 outputs the sum of the count value from the counter 35 and the logical product data from the AND circuit 36 to the address terminal of the RAM 32 as a ram address RADR. That is, the full adder 37 changes the count value CNT1 from the counter 35 to the offset value OFS in synchronization with the input timing of the output timing signal OT.
The output is offset by the amount corresponding to.

That is, the counter 35 and the AND circuit 36
The full adder 37 adds the offset value OFS corresponding to the delay time to the count value from the counter 35 at a predetermined timing within one operation clock and outputs the result. When the output timing OT is 1 and the offset value is a negative value, the full adder 37 outputs the offset value OFS
Is output to the address terminal of the RAM 32,
Conversely, when the offset value OFS is a positive value, a value larger by the offset value OFS from the full adder 37 is stored in the RAM.
It is output to 32 address terminals.

When the offset value OFS is a negative value,
In the RAM 32, among the outputs from the full adder 37, a value that has not been offset is input as a phase update address, and the offset value is input as a read address. The phase data PD of the address is updated, and the phase data for reading the waveform memory is read from the offset read address. by this,
The output timing of the phase data PD from the RAM 32 is delayed by a time corresponding to the delay time.

Conversely, when the offset value OFS is a positive value, the non-offset value of the output from the full adder 37 is input to the RAM 32 as a phase update address, and the offset value is Since it is input as a read address, the phase data PD of the phase update address that is not offset by the full adder 31 is updated, and the phase data for reading the waveform memory is read from the read address that is not offset. As a result, the output timing of the phase data PD advances from the RAM 32 by a time corresponding to the delay time, that is, the phase data PD is output earlier.

The latch circuits 33 and 34 latch the integer part INT of the phase data from the RAM 32 in synchronization with the output timing signal OT. That is, the latch circuit 33
Latches the integer part INT of the phase data from the RAM 32 when the output timing signal OT is at a low level "0", and the latch circuit 34 latches the integer part INT of the phase data when the output timing signal OT is at a high level "1". Works. The latch circuit 6 receives the waveform data DAT from the memory system 1.
A is temporarily stored and output to the data processing unit 7. The data processing unit 7 gives various effects to the waveform data DATA read from the memory system 1 and adds an envelope.

The memory reading device of the present invention having the above-described configuration is one of a plurality of circuit blocks constituting a plurality of time division channel waveform memory sound sources in an electronic musical instrument. After this block, an interpolation circuit for performing interpolation, a digital filter for controlling the timbre of the input waveform data, an envelope control circuit for controlling the volume envelope, a plurality of time division circuits An accumulator that mixes the waveform data of the channels, a D / A converter that converts the accumulated waveform data into an analog waveform, a sound system that converts the analog waveform into a sound, and the like are sequentially connected. That is, the circuit of the present invention is a part that generates the first waveform data that is the source of sound in the waveform memory sound source.

Generally, an electronic musical instrument is provided with a sound source, performance operators such as a keyboard, setting operators such as a tone switch, and a control circuit for detecting the operation of these operators and controlling the sound source. I have. When the performance operator is operated, the control circuit assigns a pitch corresponding to the operated performance operator to a sound channel of a sound source, and instructs the sound source to generate a musical tone of the pitch. In response to the instruction, the memory reading device of the present invention generates a waveform on the time division channel to which the pitch is assigned, and sends it to the subsequent circuit block. that time,
In a storage area of the RAM 32 corresponding to the time division channel, an address corresponding to the tone selected by the tone switch is set as an initial address, and the full adder 31 is supplied with a frequency number FN corresponding to the pitch. . The subsequent circuit blocks also perform predetermined processing on the time-division channels assigned according to the instruction, and as a result, a sound of a musical tone corresponding to the operation of the performance operator is output from the sound system.

Next, the operation of the memory reading device of FIG. 1 will be described with reference to FIG. In FIG. 2, the count value CNT1 from the counter 35 is “5”, “6”, “7”,
It counts up one by one like "8".
The offset value is “+2”, and this value corresponds to the delay time. That is, a delay of “2” occurs before the output of the waveform as compared with the standard case. Output timing signal OT
Is a repetition of “0” and “1”. In such a case, the RAM address RADR1 is supplied to the address terminal of the RAM 32. That is, when the count value CNT1 is "5" and the output timing signal is "0", the count value CNT1 "5" is used as it is in the RAM address RAM.
ADR1 is supplied to the address terminal and the count value C
When NT1 is “5” and the output timing signal is “1”, “5” of the count value CNT1 is set to the OFF-foot value.
It is offset by “+2” of SET, and the ram address R
As AMADR1, "7" is supplied to the address terminal. Similarly, when the output timing signal is "0", the count value CNT1 is supplied to the address terminal as it is, and when the output timing signal is "1", the count value CNT1 is offset by the offset value OFFSET. Supplied to the address terminal. Therefore, RA
From the data output terminal DO of M32, the phase data PD for the compressed waveform memory is output earlier by the time corresponding to "+2" in the count value CNT1 of the counter 35.

In FIG. 2, the RAM address RADR2
Is RA when the offset value OFFSET is “+4”.
It is supplied to the address terminal of M32. Therefore, the phase data PD for the compressed waveform memory is output from the data output terminal DO of the RAM 32 earlier by the time corresponding to “+4” in the count value CNT1 of the counter 35.

Although the present embodiment is a waveform memory sound source for reading a waveform memory and generating a musical tone, the address generator of the present invention writes an input waveform sample in the waveform memory, that is, a so-called sampler or digital recorder. Applicable. Although the present invention does not show a specific method of supplying the offset value OFS corresponding to the delay time of the memory system to the full adder 37, it may be set manually or set in advance for each memory system. A value may be used, or the delay of the memory system may be automatically detected and set.

[0029]

According to the present invention, the output time of the address generated by the waveform memory address generator can be adjusted without causing a large increase in the number of circuits such as addition of an address delay.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a waveform memory address generator according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the waveform memory address generator of FIG. 1;

FIG. 3 is a diagram showing a conventional waveform memory address generator in which a delay circuit is provided on an address signal line side to adjust an address supply timing to adjust output timing of waveform data.

FIG. 4 is a diagram showing a waveform memory address generator in which a delay circuit is provided on the waveform data signal line side to adjust the output timing of the waveform data itself.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory system, 2, 3 ... Address counter logic circuit, 4A, 4B ... Delay circuit, 5A, 5B ... Selection circuit, 6 ... Latch circuit, 7 ... Data processing part, 21 ... Full adder, 22 ... Register, 31, 37 … Full adder, 32
... RAM, 33, 34 ... Latch circuit, 35 ... Counter,
36 ... And circuit

Claims (1)

(57) [Claims] 1. A waveform memory address generator for performing a plurality of time-division channel operations, wherein phase data respectively corresponding to the plurality of time-division channels are read and written at respective storage positions, and each time-division channel is stored in a plurality of time periods. Using a read / write memory accessed for each time slot divided into slots, and a predetermined time slot in each time-division channel, the phase data value of each time-division channel in the read / write memory is converted to a waveform to be generated. Phase data updating means for changing at a rate corresponding to a pitch, and using another time slot different from the predetermined time slot in each time division channel, sequentially reading the phase data of each time division channel from the read / write memory. reading,
Address generation means for generating an address for accessing the waveform memory based on the read phase data; and a storage position of the phase data read by the address generation means in each time division channel at a timing at which the address is to be generated. A waveform memory address generator including timing adjustment means for changing the timing according to the timing.