JP2870014B2 - ECL circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECL circuit, and more particularly to a circuit configuration of an emitter follower output circuit section.

[Conventional technology]

Conventionally, an ECL circuit combining a differential amplifier circuit and an emitter follower output circuit has been widely used as a high-speed logic circuit. This emitter-follower output circuit is for level-shifting the output of the differential amplifier circuit, and performs the following operation as a high-speed operation.

The output of the differential amplifier circuit is at a low potential level (hereinafter referred to as low)
From high to high potential level (hereinafter referred to as high)
The load capacitance connected to the output rises at a high speed because it is charged by the emitter follower output transistor. Also, when the output of the differential amplifier circuit changes from high to low,
The load capacitance is discharged by a relatively low-impedance resistor or constant current source connected between the output and the lower power supply, falls at a high speed, and achieves high-speed operation by the function of the emitter follower output circuit. .

FIG. 3 is a circuit diagram showing an example of a conventional ECL circuit having a terminating resistor configuration. In the figure, the bases of input transistors 8 and 9 are connected to input terminals 1 and 2, respectively, the emitters are connected in common and connected to a lower power supply 5 via a constant current source 7, and the collectors are connected in common. Connected to the higher power supply 4 via the supply 12. Also compare transistor
The reference voltage 6 is applied to the base of the transistor 10, the emitter is connected to the emitters of the input transistors 8 and 9, the collector is connected to the higher power supply 4 via the resistor 13, and an output signal is taken out from the collector to obtain a differential amplifier. A circuit is configured.

On the other hand, the base of the emitter follower transistor 11 is
The output of the differential amplifier circuit is connected to the collector of a comparison transistor 10, the collector is connected to the higher power supply 4, the emitter is connected to the lower power supply 5 via a resistor 14, and the emitter follower output circuit is connected to the emitter follower transistor.
The output of the ECL circuit is connected to the output terminal 3.

In this circuit, the signal of the output terminal 3 becomes OR logic with respect to the signal of the input terminals 1 and 2. The load capacitance 15 is the load capacitance of the output terminal 3 and includes the capacitance of the wiring connected to the input terminal of the next stage ECL circuit.

This high-speed operation of the ECL circuit is realized by charging the load capacitance 15 by the emitter follower transistor 11 and discharging the load capacitance 15 by the resistor 14.

[Problems to be solved by the invention]

When an integrated circuit is configured using such an ECL circuit, the logic operates normally even if there is no resistor or constant current source to be connected between the emitter of the emitter-follower type output transistor and the lower power supply. , The falling operation speed becomes extremely slow.

In FIG. 3, even when the resistor 14 is not provided on the circuit, the output terminal 3 becomes high when the collector electric range of the comparison transistor 10 is high. Here, when the collector potential of the comparison transistor 10 changes to low, the output terminal 3 cannot drive the next-stage ECL circuit and becomes low. In this case, the charge stored in the load capacitance 15 is discharged by the base input current of the next stage ECL circuit, and the response becomes extremely slow because there is no low-impedance discharge path by the resistor 14.

When an integrated circuit is manufactured, disconnection of signal wiring, defective contact opening, and the like always occur with a certain probability. Usually, such a defect should be removed by a circuit operation test, but a defect in which only the resistor 14 in FIG. 3 is not connected to the circuit has a normal logic.
It cannot be removed by a circuit operation test. Therefore, even if it is possible to omit the extended time test of the circuit by performing the operation test and the current consumption test on other logic circuits,
The ECL circuit has a problem that this type of failure cannot be removed unless a delay time test is separately performed.

However, as the scale of integrated circuits has increased in recent years, the number of emitter-follower output units in integrated circuits composed of ECL circuits has also become enormous, and it is extremely difficult to perform delay time tests on all of them. It's getting harder.

An object of the present invention is to solve such a problem, and when the low-impedance current path connecting the emitter of the emitter follower output unit and the lower power supply is eliminated, the level of the output terminal is logically fixed to high. It is an object of the present invention to provide an ECL circuit capable of detecting a defect on a circuit by a circuit operation test.

[Means for solving the problem]

According to the configuration of the present invention, an emitter-follower type output transistor is connected to the output side of the ECL circuit unit, and a terminating resistor or a constant current source is connected between the emitter of the emitter-follower type output transistor and the low potential side power supply. In the ECL circuit, a resistor having a resistance value for flowing a current that does not affect the operation level of the circuit is connected between the emitter and the base of the emitter-follower type output transistor.

〔Example〕

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the present embodiment, the same elements and terminals as those in FIG. 3 of the conventional example are described with common numbers, and the output logic of OR is obtained at the output terminal 3 with respect to the signals at the input terminals 1 and 2. It is.
This embodiment differs from FIG. 3 in that a resistor 16 is inserted between the emitter and base of the emitter follower transistor. A sufficiently high resistance value for the resistor 14 is selected for the resistance value of the resistor 16 so that there is no logical problem.

 Hereinafter, the operation of this circuit will be described.

Now, the current value of the constant current source 7 is 0.5 mA, the resistance values of the resistors 12 and 13 are 1.2 KΩ, the logic amplitude applied to the base of the emitter follower transistor 11 is 600 mV, the potential of the higher power supply 4 is 0 V, The potential of the lower power supply 5 is -5.2V. Also,
Resistance values of the resistors 14 and 16, respectively 4k, and 10 k.OMEGA, the forward voltage V _F of the emitter follower transistor 11 when it is normally manufactured to 800 mV.

Here, when the resistor 16 is not provided, the collector potential of the comparison transistor 10 is 0 mV at the high level and −600 mV at the low level since the amplitude is 600 mV at the base of the emitter follower transistor 11.
However, if the resistor 16 is present, the potential at both ends of the resistor 16 is 800 mV, so a current of 0.08 mA flows, and since this current is applied to the resistor 13, 96 mV is added to the high and low levels. The high applied to the base of the emitter follower transistor 11 is -96 mV, and the low applied is -696 mV. Since the forward voltage V _F is 800 mV, high output terminal 3 -896MV, wax becomes -1496MV, the current flowing through the resistor 14 at this time when the high is 1.076MA, when wax is 0.926MA.

As described above, although the high and low level shift values are changed by the resistor 16, the basic operation of the circuit is the same as that of the conventional example, so that high-speed circuit operation can be maintained.

Here, it is assumed that the resistor 14 is not connected due to a manufacturing defect.

In this case, as the load of the output terminal 3, which corresponds to the input terminal 1 of the same circuit as FIG. 1 are 6 circuit connection, the h _FE of all the transistors is 100. At this time, since the constant current source is 0.5 mA, the base current of the input terminal 1 is 0.005 mA.
The total load drive current flowing from the output terminal is 0.03 mA, which is extremely smaller than the original emitter follower current (about 1 mA). This current flows through the resistor 16 and the voltage across the resistor 16 becomes 300 mV.

At this voltage, the emitter follower transistor 11 does not turn on and the resistor 16 is not provided.If the collector potential of the comparison transistor 10 is high, 0 mV is applied, and if the resistor is low, −600 mV is applied. Is resistance 13 and resistance 16
Therefore, the collector potential of the comparison transistor 10 becomes -36 mV when high and -636 mV when low. At this time, since the voltage between both ends of the resistor 16 is 300 mV, the eight levels of the output terminal 3 become -336 mV when high, and -936 mV when low, which is a potential that is not logically treated as low, that is, fixed at high. Therefore, the fact that the resistor 14 is not connected can be detected by the logic operation test.

In this embodiment, the terminating potential of the emitter follower resistor 14 is set to the lower potential 5 of −5.2 V. However, due to the circuit configuration, the terminating potential may be terminated to another power source for terminating the emitter follower. it can.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. In this embodiment, the resistor 14 in FIG. 1 is replaced by a constant current source 17, and all other circuit configurations are the same as those in FIG.

In this case, if the current value of the constant current source 17 is 1 mA, this current value is constant regardless of whether the output terminal 3 is high or low. The relationship between the output levels in the case of the above can be explained similarly to the case of FIG.

As described above, also in the second embodiment, when the constant current source 17 is not connected, the potential of the output terminal 3 is fixed to high, and the failure can be detected in the logic operation test.

〔The invention's effect〕

As described above, according to the present invention, by inserting a resistor between the emitter and base of the emitter-follower transistor of the ECL circuit, even if a failure occurs such that the discharge element of the load capacitance of the output terminal is not connected on the circuit. This has the effect that the defect can be detected only by the logical operation test.

[Brief description of the drawings]

1 and 2 are circuit diagrams of first and second embodiments of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional ECL circuit. 1,2 ... input terminal, 3 ... output terminal, 4 ... higher power supply, 5 ... lower power supply, 6 ... reference voltage, 7,17 ... constant current source, 8,9 ... input transistor , 10 ... Comparison transistor, 11 ... Emitter follower transistor, 12,13,1
4,16: Resistance, 15: Load capacity.

Claims (1)

(57) [Claims] An emitter follower type output transistor is connected to an output side of an ECL circuit section, and a terminating resistor or a constant current source is connected between an emitter of the emitter follower type output transistor and a low potential side power supply to form a circuit. ECL to configure
An ECL circuit, wherein a resistor having a resistance value for flowing a current that does not affect an operation level of the circuit is connected between an emitter and a base of the emitter-follower type output transistor.