JP2868693B2 - Method for manufacturing LED array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an LED array.

[0002]

2. Description of the Related Art When an LED array is manufactured, a semiconductor substrate of a first conductivity type (N type) is formed on a semiconductor substrate of a first conductivity type (N type) by forming a pn junction for a light emitting diode (LED) with the substrate.
Shape) It is necessary to form a large number of impurity diffusion regions in an array. In this case, since the openings of the substrate where the p-type impurity diffusion regions are formed are formed as an anti-diffusion film having a function of exposing and covering other portions in an array, an insulating film is used, and the impurity diffusion is performed. You. As a conventional example of a method of manufacturing an LED array including such an impurity diffusion step, there is one disclosed in Documents I and II (Document I: JP-A-56-30776, "Method of Manufacturing Light-Emitting Element Array", Reference II: "Development of Zn selective diffusion technology using plasma CVD SiO _X N _Y film", Oki Electric R & D, No. 1
No. 28, Vol. 52, no. 4. October 1985,
PP 104-110).

FIG. 7 shows a conventional L disclosed in Reference I.
One LE in a sample in the process of forming an ED array
D part (this part is called an array element part) is shown.

In the method of manufacturing an LED array disclosed in Document I, Zn is used as a P-type impurity when selectively forming a large number of P-type diffusion regions 32 on an N-type semiconductor substrate 30 to prevent diffusion at that time. An alumina (Al ₂ O ₃ ) film 34 having an opening is used as the film, and an SiO ₂ film 36 is used as a low concentration diffusion mask. When forming the P-type diffusion region 32 by zinc diffusion, the alumina film 34 has a property of slowing down the zinc diffusion rate. For this reason, the alumina film 34 serves to suppress the lateral diffusion of the P-type diffusion region. In addition, since the alumina film 34 can make the bottom surface of the P-type diffusion region 32 flat,
It has been reported that ED arrays can be made denser. Further, a SiO ₂ film 36 serving as a low concentration diffusion mask is used.
Is generally removed in a post-process in the LED array formation process (see Document III: “Solid-state light-emitting device and its application”, Industrial Report, 1971, p. 80).

FIG. 8 shows an example of an LED array element portion in the process of forming a conventional LED array disclosed in Document II.

In the method of manufacturing an LED array disclosed in Document II, silicon having an opening 43 as a diffusion preventing film for P-type impurities when selectively forming a large number of P-type diffusion regions 42 on an N-type semiconductor substrate 40 is provided. A laminated film of a nitride film 44 and a SiON film 46 having an opening 45 is used. The P-type diffusion region 42 is formed by diffusing zinc as in FIG. The manufacturing method from the conventional LED array element portion to the final process of the LED array in FIGS. 7 and 8 is as follows.
Since it is disclosed in Reference III, detailed description is omitted here.

[0007] Each of the above methods I to II is
Although not shown, an alumina film 3 as a diffusion prevention film is used.
4 and the SiON film 46 are used as they are as an interlayer insulating film, and one end of p
A wiring layer connected to the shaped diffusion region 32 (42) is formed.

[0008]

However, the LED array manufacturing methods disclosed in the above-mentioned Documents I and II have the following problems.

In the method of Document I, there is only one insulating film (Al ₂ O ₃ film) 34 formed on the N-type semiconductor substrate 30 (the SiO ₂ film 36 is formed in a later step as described above). Removed). Therefore, when a pinhole exists in the alumina film 34 of the conventional LED array element portion, the wiring layer (not shown) formed on the alumina
The semiconductor substrate 30 is electrically connected to the semiconductor substrate 30 via a pinhole, resulting in a short circuit. For this reason, even when a signal is applied between the electrodes formed on the upper and lower surfaces of the substrate 30, dots that do not emit light are generated in the elements of the LED array. In addition, P
When the shaped diffusion region 32 is formed, light is emitted also from the pinhole portion, and there is a problem that a regular light emission amount cannot be obtained. As described above, there is a problem that it is difficult to uniformly form a film having no pinhole on the N-type semiconductor substrate 30 using only one of the alumina films 34.

In the method of Document II (an example in which two layers of a silicon nitride film (SiN film) 44 and a SiON film 46 are used as an insulating film), the problem of pinholes is reduced by the use of two insulating films. Although it is thought that it can be done, it is still considered that the factors that cause pinholes are inherent. The factors are considered as follows. SiO used as upper layer
The internal stress of the N film 46 is larger than that of a silicon nitride film (SiN film) or an alumina film (Al ₂ O ₃ film), and therefore, cracks and the like are easily generated. In addition, pinholes are generated due to flakes or the like when the insulating film is formed (see FIG. 6A). Therefore, as shown in FIG.
It is considered that pinhole defects 50a are also likely to occur in the resist pattern 48 formed as a mask for forming the openings 45 and 43 in the film 46 and the SiN film 44. Therefore, the openings 45, 43 are formed in the SiON film 46 and the SiN film 44.
Pinhole 50b in the etching for forming
Is further enlarged, and a pinhole 50c is formed in the underlying SiN film 44 via the pinhole 50.
For this reason, the wiring layer of the Al thin film and the N-type semiconductor substrate 40 are short-circuited similarly to the method of the above-mentioned document I, and light emission failure occurs in the element portion of the LED array.

This application has been made in view of the above-mentioned problems, and it is an object of each invention of this application to provide a method capable of manufacturing an excellent LED array having an insulating film with few pinholes. It is in.

[0012]

According to a first aspect of the present invention, there is provided an N-type semiconductor substrate comprising:
A plurality of P-type diffusion regions provided on the N-type semiconductor substrate;
An LED comprising: an insulating film having an opening exposing the P-type diffusion region; and a wiring layer having one end connected to a part of the P-type diffusion region and extending over the insulating film. In manufacturing an array, (a) an alumina film (Al ₂ O ₃ ) is formed on an N-type semiconductor substrate as a first layer portion of the insulating film.
(B) forming a first opening in the alumina film; and (c) selectively diffusing a P-type impurity into the N-type semiconductor substrate in which the opening has been formed. (D) forming a second insulating film as a second layer portion of the insulating film on the N-type semiconductor substrate on which the first opening has been formed;
Selectively etching the second insulating film to form a second opening corresponding to the first opening in the second insulating film (provided that the second insulating film and its etching means are A material and a means for selectively etching the insulating film with respect to the alumina film by utilizing a difference between the etching rates thereof); (e) forming a wiring layer on the second insulating film in which the second opening is formed; And a step of performing

In practicing the first invention, the etching means of the second insulating film is dry etching, and the second insulating film is formed of a silicon nitride film (SiN film) and a SiON film.
It is preferable to use one kind of film or a laminated film selected from films.

Further, in carrying out the present invention, a diffusion protection film is formed on the entire surface of the N-type semiconductor substrate on which the first opening has been formed, and zinc is selectively diffused with the diffusion protection film formed. Is preferred.

According to a second aspect of the present invention, an N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, and a P-type diffusion region are provided. Manufacturing an LED array comprising: an insulating film having an opening exposing a region; and a wiring layer having one end connected to a part of the P-type diffusion region and extending over the insulating film. (I) forming an alumina film (Al ₂ O ₃ film) as a first layer portion of an insulating film on an N-type semiconductor substrate; and (ii) forming a first opening in the alumina film. (Iii) forming a PSG film on the N-type semiconductor substrate on which the first opening has been formed, and (iv) selecting a P-type impurity for the N-type semiconductor substrate with the PSG film formed. (V) forming a sample on the PSG film of the sample in which the diffusion of the P-type impurity has been completed. Forming a second alumina film as a second layer portion of the insulating film; and (vi) selectively etching the second alumina film using hot phosphoric acid and utilizing the difference in their etching rates. Forming a second opening corresponding to the first opening in the second insulating film by (v)
ii) The PSG film portion exposed by forming the second opening is etched using buffered hydrofluoric acid to form the PSG film.
Forming a third opening in the SG film; and (viii) forming a wiring layer on the second alumina film of the sample in which the third opening has been formed.

[0016]

According to the first aspect of the present invention, the P-type impurity diffusion preventing film at the time of forming the P-type diffusion region and the insulating film serving as the interlayer insulating film between the subsequent wiring layer and the N-type semiconductor substrate are formed as follows. It is composed of a laminated film of an alumina film and a predetermined second insulating film.
The alumina film serves to suppress the lateral diffusion of the P-type impurity. Further, since the second insulating film is a material which is selectively etched as compared with the alumina film, that is, a material having an etching rate higher than that of the alumina film, the second insulating film is formed by forming a second opening in the second insulating film. When etching the insulating film, it can be said that the alumina film is not substantially etched. This means that even if a pinhole exists in the second insulating film, the alumina film is not substantially etched through the pinhole. That is, it can be said that, when the opening is formed in the second insulating film, the pinhole does not continue from the second insulating film to the alumina film due to the pinhole of the second insulating film. Further, even if pinholes are formed in the alumina film and the second insulating film when the respective films are formed, the probability that the pinholes of both films overlap each other is very low. From these facts, according to the method of the first invention, an insulating film having few pinholes can be obtained as a result.

Further, in the first invention, between the step (b) and the step (c), the entire surface of the N-type semiconductor substrate on which the first opening has been formed is 1/10 or less of the alumina film. Thick PS
Forming a diffusion protection film made of a G film; performing the step (c), that is, the selective diffusion of the P-type impurity in a state where the diffusion protection film is formed; and performing the step (d). After that, as a pre-process of performing the process (e), the PSG film exposed from the second opening is formed by utilizing the difference in etching removal time between the PSG film, the alumina film, and the second insulating film.
By selectively etching away, a third opening is formed in the PSG film. The function of the PSG film is to prevent, for example, phosphorus or arsenic from leaking out from a compound semiconductor generally used as an N-type semiconductor substrate in a diffusion step.

According to the structure of the second invention, the PSG film is not etched by the etchant (hot phosphoric acid) for etching the second alumina film, so that the lower alumina film is etched by the second alumina film. At this time, it is protected by the PSG film. Therefore, even if a pinhole is formed in the second alumina film, it does not occur that the pinhole is connected to the lower alumina film through the pinhole. Therefore, as in the first invention, an insulating film having few pinholes can be obtained. The alumina film is made of SiN film, Si
Since the film stress is smaller than the ON film and the SiO ₂ film, it can be said that the second invention is less likely to cause problems due to the film stress than the first invention.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing an LED array according to the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the shape, size, and arrangement of each component so that the present invention can be understood. Prior to the method of manufacturing the LED array, the structure of the LED array of the present invention will be briefly described.

FIG. 1A is a plan view schematically showing the structure of the LED array of the present invention, and FIG.
FIG. 4 shows a cross-sectional view taken along the line A.

First, an LED array according to a first embodiment of the present invention will be described with reference to FIGS. 1 (A) and 1 (B). In this case, one element of the LED array is LE
This is referred to as a D array element section. The LED array element portion of the present invention includes an N-type semiconductor substrate 10 (for example, an N-type GaAsP substrate) and a plurality of P-type diffusion regions 12 on the N-type GaAsP substrate 10. Further, the N-type GaAsP substrate 10
An alumina (Al ₂ O ₃ ) film 14 having a first opening 15 on which the P-type diffusion region 12 is exposed, and a second insulating film
A PSG film 16 having a third opening 27 and a silicon nitride film (SiN film) 18 having a second opening 21 are laminated. Here, the alumina film 14, the PSG film 1
6 and the silicon nitride film 18 are collectively referred to as an insulating film 23.

Further, the alumina film 1 is removed from the P-type diffusion region 12.
4. A lead portion 20a is provided to the surface of the substrate 10 along a part of the ends of the PSG film 16 and the silicon nitride film 18. The lead portion 20a has one end face fixed to the P-type diffusion region 12 and the other end face bonded to the bonding pad 20.
b. And the drawer 20a
And the bonding pad 20b constitute the wiring layer 20.

On the other hand, on the back surface of the substrate 10, an AuGeNi film 22 and an Au film 24 serving as N-type electrodes are laminated. The AuGeNi film 22 and the Au film 24 are collectively referred to as a lower wiring layer 25.

Next, L of the modification of the first embodiment of the present invention will be described.
FIG. 2 shows the structure of the ED array.

The structure of a modification of the first embodiment of the present invention is as follows.
As the insulating film 23 provided on the N-type GaAsP substrate 10, an alumina film 14 and a silicon nitride film (second insulating film) 1
9 is laminated.

Next, a method of manufacturing the LED array according to the first embodiment of the present invention will be described with reference to FIGS. 3 (A), 3 (B) and 4 (C) and FIGS. 4 (A), 4 (B) and 4 (C). And FIG.
(A) and (B).

As the N-type semiconductor substrate 10, N-type GaAsP
A substrate (hereinafter, referred to as a substrate) is used. This substrate 10
Prior to the formation of the film, the substrate 10 is first washed with any suitable cleaning liquid to remove dirt on the surface of the substrate 10, and then the substrate 10 is dried.

An alumina (Al ₂ O ₃ ) film 14 is formed on the substrate 10 by, for example, a sputtering method (FIG. 3A). At this time, the thickness of the alumina (Al ₂ O ₃ ) film 14 is set to, for example, 2000 A ° to 3000 A ° (the symbol of A ° represents Angstroms).

Next, a first opening for forming a diffusion region of zinc as an example of a P-type impurity is formed in the alumina (Al ₂ O ₃ ) film 14 by photolithography (FIG. 3B). . The etching conditions for forming the openings in the alumina film 14 are as follows: hot phosphoric acid is used as an etchant;
An etching process is performed for 2 minutes in a temperature range of 80 ° C. to 85 ° C.

Next, PS is formed on the alumina (Al ₂ O ₃ ) film 14 having the first opening 15 by using, for example, the CVD method.
A G film 16 is formed. The PSG film 16 has a thickness of 100
A ° to 200 A °. The PSG film 16 is preferably formed so that the refractive index of the film thickness is preferably about 1.4. Thereafter, zinc (Zn) is selectively diffused into the substrate 10 on which the first opening 15 has been formed to form a P-type diffusion region 12 (C in FIG. 3). The PSG film 16 serves to prevent gallium (Ga) and arsenic (As) atoms from evaporating when zinc is diffused. In addition, when performing zinc diffusion, any of an open tube method and a sealed tube method may be used as a diffusion furnace, and as a diffusion condition, in the case of a sealed tube method, the heating temperature is preferably set to 700 ° C. The treatment is performed for 6 hours at a temperature in the range of -800 ° C. At this time, since the alumina film 14 is formed on the substrate 10, P
Lateral diffusion of the shaped diffusion region 12 can be suppressed.

Next, after cleaning and drying the structure shown in FIG. 3C by using any suitable method, the substrate 10 having the first opening 15 formed thereon is formed by using, for example, a plasma CVD method.
A second insulating film (for example, a silicon nitride film (SiN film)) 18 is formed thereon as a second layer portion of the insulating film 23 (FIG. 4).
(A)).

The thickness of the silicon nitride film (SiN film) 18 is about 1000 A °.

Next, a second opening 21 is formed in the silicon nitride film 18 at a portion corresponding to the first opening 15 by photolithography (FIG. 4B). At this time, a dry etching method is used for etching the silicon nitride film 18.

The silicon nitride film 18 is made of the alumina film 1
4 and the PSG film 16, the alumina film 14 and the PSG film 16 are not etched even when the silicon nitride film 18 is etched. When dry etching is used, a SiON film may be used instead of the SiN film 18 as the second insulating film. However, when an SiON film is used, since the internal stress of the film is large, the substrate may be warped. Therefore, it is necessary to pay close attention to the film formation conditions.

The width L ₂ of the second opening 21 of the silicon nitride film is equal to the width L ₂ of the first opening 15 of the alumina film.
_It is desirable to set it larger than ₁ . The reason will be described later. Further, for example, an arbitrary suitable resist pattern (not shown) is formed on the silicon nitride film 18 as an etching mask, and etching is performed. At this time, plasma etching is used as a method for etching the silicon nitride film 18. The plasma etching conditions at this time are as follows.

Etching gas: carbon tetrafluoride (CF ₄ ) gas + oxygen (O ₂ ) gas RF frequency: 13.56 MHz Power: 250 W Etching time: about 2 minutes The silicon nitride film 18 is selectively formed by the above-described etching conditions. Although removed, the PSG film 16 and the alumina film 14 remain without being removed.

Next, as an example of the second invention of the present invention, a second alumina film is used instead of the silicon nitride film.
Since the second alumina film has a smaller internal stress than the silicon nitride film, the warpage of the substrate 10 can be suppressed. Width L ₂ of the even second opening 21 when the second alumina film is desirably larger than the width L ₁ of the first opening of the alumina film 14 of the first layer portion. Further, the etching of the second alumina film uses a wet etching method, and the second alumina film on the PSG film 16 is almost selectively etched by, for example, hot phosphoric acid. At this time, the PSG film 16
Since the alumina film 14 remains without being etched, the alumina film 14 as the first layer portion is not etched.

FIGS. 6A and 6B are schematic diagrams for explaining the occurrence of pinholes formed in the insulating film. FIG. 6B is a schematic diagram of the first embodiment, and FIG. 6A is a schematic diagram of a conventional example for comparison with the present invention. As described above, in the conventional example, when the pin holes 50a, 50b, and 50c are formed in the resist pattern 48, the SiON film 46, and the SiN film 44, the silicon nitride film 4 is formed when forming the openings 43, 45.
Since the etching rates of the SiON film 4 and the SiON film 46 are substantially equal to each other, the SiON film 46 is etched through the pinholes of the resist pattern 48 and further etched to the silicon nitride film 44 on the lower surface. Resist pattern 4
8 pinhole 50a and the SiON film 46 pinhole 5
When 0b overlaps, the pinhole is considered to reach the substrate 10 through the silicon nitride film 44. On the other hand, in the embodiment of the present invention, even if the resist pattern 48, the silicon nitride film 19, and the alumina film 14 have the pinholes 51a, 51b, and 51c, the etching speed of the silicon nitride film 19 is lower than that of the alumina film 14. Since it is large, the alumina film 14 is not etched. Therefore, even when the resist pattern 48 and the pinholes 51a and 51b in the silicon nitride film 19 overlap, the probability that the pinhole penetrates the alumina film 14 and reaches the substrate 10 is reduced.

Next, returning to the process chart again, after removing the resist pattern by using any suitable method, the silicon nitride film 18 is used as a mask and the lower portion of the second opening 21 is formed by buffer hydrofluoric acid, for example. PSG being formed
The film 16 is removed. At this time, the third opening 27 is formed in the PSG film 16.

Next, after forming a preliminary film (not shown) for a wiring layer on the entire surface of the sample using, for example, EB vapor deposition, the lead portion 2 from the P-type diffusion region is formed by photolithography.
0a is formed (FIG. 4C). This drawer 20
a is an Al film, and the film thickness is 1.5 μm to 2.5 μm. Further, the lead portion 20a and a bonding pad (not shown) formed on the silicon nitride film are joined to form a wiring layer (see FIG. 1A).

The etching of the lead portion 20a is performed by a wet etching method. At this time, the alumina film 14 is also etched in the same manner as the lead portion 20a, but the PSG film 16 and the silicon nitride film 18 are not etched.

The second opening 2 of the silicon nitride film 18
The width L ₂ of ₁ is larger than the width L ₁ of the first opening of the alumina film 14 (L ₂ > L ₁ ). For this reason, it is possible to reduce the formation of voids due to the overetching of the portion of the alumina film 14 that is in close contact with the lead portion 20a. A
For example, hot phosphoric acid or the like is used for etching the lead portion 20a of the l-wiring layer. In such a gap, hot phosphoric acid remains even after cleaning (cleaning for removing the etchant). Sometimes. The residual hot phosphoric acid between the wiring layer and the alumina film may cause the corrosion of the wiring electrode to gradually progress, leading to disconnection of the wiring layer. However, as described above, L ₂ >
If there as L _1, becomes void hardly occurs is over-etched, even if generated a small air gap.
Further, when L ₂ > L ₁ , the thickness of the wiring pattern can be reduced compared to the case where L ₂ = L ₁ , so that disconnection of the electrode is less likely to occur. In addition, when the second opening is formed, even if the second opening forming mask is misaligned, the second insulating film can be prevented from covering the P-type diffusion region. The contact resistance with the shaped diffusion region can be kept constant.

Next, after the back surface of the substrate 10 is polished by any suitable method, an AuGeNi film 22 for an N-type electrode is formed by, for example, EB evaporation (FIG. 5A). The thickness of the N-type electrode AuGeNi film 22 is set to 1000 A °.
２０００2000 A °.

Further, an Au film 24 is formed on the AuGeNi film 22 by using the EB evaporation method (FIG. 5B).
Note that the AuGeNi film 22 and the Au film 24 are collectively referred to as a lower wiring layer 25. Through the series of steps described above, the main structure of the LED array of the present invention is formed.

Next, a manufacturing method according to a modification of the first embodiment of the present invention will be described with reference to FIG.

After the step (C) of FIG. 3 of the first embodiment, the PSG film 16 is completely removed by using any suitable method. Thereafter, an LED array is formed in the same steps as those in FIG. Therefore, detailed description is omitted. Thus, the insulating film 23 may have a two-layer structure of the alumina film 14 and the silicon nitride film 19.

As can be understood from the above description, according to the present invention, the number of pinholes generated in the insulating film 23 can be reduced by using different materials and changing the etching rate. In addition, short-circuit defects of the substrate 10 are reduced, and the yield of products is improved.
According to the experimental results of the present inventors, the conventional yield is 70%.
% To 80%, the yield of the present invention is 10%.
A result close to 0% has been obtained. Therefore, it was found that the LED array formed according to the embodiment of the present invention can provide a high-quality LED array with good yield.

Further, since the present invention has the alumina film as the first layer portion on the N-type semiconductor substrate, the present invention has the excellent property of the prior art, that is, the property that the lateral diffusion of the P-type diffusion region can be suppressed. There is also an advantage that it can be inherited as it is.

Also, the present invention has an advantage that the warpage of the substrate can be reduced as compared with a conventional SiON film or SiO ₂ film because an alumina film or a silicon nitride film having small internal stress is laminated on the N-type semiconductor substrate. There is also.

[0050]

As is clear from the above description, according to the LED array manufacturing methods of the first and second aspects of the present invention, the insulating film can be used both as a diffusion preventing film and as an interlayer insulating film. An insulating film having characteristics of suppressing lateral diffusion of a P-type impurity (for example, Zn) contained in an alumina film and having fewer pinholes than before can be obtained. For this reason, the lateral diffusion of the P-type impurity can be prevented, so that a high-density LED array with high light emission intensity of each LED can be obtained. Shorts and shorts between LED dots can be prevented. In addition, light emission loss can be reduced because the number of pinholes is small.

In the structure of the second invention, the alumina film has a smaller film stress than the SiN film or the SiON film.
Wafer warpage is less likely to occur than when a SiN film or a SiON film is used as the second insulating film. Therefore, it is possible to reduce the deterioration of the characteristics of the LED array due to the warpage of the wafer.

[Brief description of the drawings]

FIG. 1A is a plan view of an LED array according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA.

FIG. 2 is a structural sectional view of an LED array provided for explaining a modification of the first embodiment of the present invention.

FIGS. 3A to 3C are manufacturing process diagrams provided for explaining a manufacturing method according to the first embodiment of the present invention.

4 (A) to 4 (C) are manufacturing process diagrams following FIG. 3 for explaining the manufacturing method of the first embodiment of the present invention.

FIGS. 5A and 5B are manufacturing process diagrams following FIG. 4 for explaining the manufacturing method according to the first embodiment of the present invention;

FIG. 6A is a schematic diagram for explaining a state of occurrence of a pinhole formed in a conventional insulating film, and FIG. 6B is a schematic view of a state of occurrence of a pinhole according to the first embodiment of the present invention. It is a schematic diagram for description.

FIG. 7 is a cross-sectional view illustrating a structure of a conventional LED array element unit.

FIG. 8 is a cross-sectional view illustrating a structure of a conventional LED array element unit.

[Explanation of symbols]

 10: N-type GaAsP substrate 12: P-type diffusion region 14: Alumina film 15: First opening 16: PSG film 18: SIN film 19: Second insulating film 20a: Leading portion from P-type diffusion region 20b: Wire bonding Pad 20: Wiring layer 21: Second opening 22: AuGeNi film 23: Insulating film 24: Au film 25: Lower wiring layer 27: Third opening

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masumi Yanaka 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-58-139480 (JP, A) JP-A-58-139480 Hei 4-239184 (JP, A) JP-A-63-56967 (JP, A) JP-A-51-140559 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 33 / 00

Claims (6)

(57) [Claims] 1. An N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, an insulating film having an opening exposing the P-type diffusion region, In manufacturing an LED array including a wiring layer partially connected at one end and extending over the insulating film, (a) a first layer of the insulating film on an N-type semiconductor substrate; Forming an alumina film (Al ₂ O ₃ film) as a portion; (b) forming a first opening in the alumina film; and (c) forming a P on the N-type semiconductor substrate after the opening is formed. (D) forming a second insulating film as a second layer portion of the insulating film on the N-type semiconductor substrate in which the first opening has been formed; The film is selectively etched to form a second opening corresponding to the first opening in the second insulating film. Forming step (however, the second insulating film and its etching means are materials and means for selectively etching the second insulating film with respect to the alumina film by utilizing a difference in etching rate between them). (E) forming the wiring layer on the second insulating film on which the second opening has been formed. 2. The method for manufacturing an LED array according to claim 1, wherein the etching means for the second insulating film is dry etching, and the second insulating film is a silicon nitride film (SiN film) and a silicon nitride film.
A method for manufacturing an LED array, comprising a single film selected from iON films or a laminated film. 3. The method of manufacturing an LED array according to claim 1, wherein, between the step (b) and the step (c), the entire surface of the N-type semiconductor substrate on which the first opening is formed is formed. A step of forming a diffusion protection film made of a PSG film having a thickness of 1/10 or less as compared with the alumina film, and the step (c), that is, the selective formation of the P-type impurity in a state where the diffusion protection film is formed. After performing the diffusion, and after performing the step (d), as a pre-process of performing the step (e), the PSG film exposed from the second opening portion is subjected to the PSG film, the alumina film, and the A method for manufacturing an LED array, wherein a third opening is formed in the PSG film by selectively etching using a difference in an etching removal time from the second insulating film. 4. The method for manufacturing an LED array according to claim 1, characterized in that the width L ₂ of the second opening second insulating film is larger than the width L ₁ of the first opening of the alumina film LE
Method for manufacturing D array. 5. An N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, an insulating film having an opening exposing the P-type diffusion region, In manufacturing an LED array comprising a wiring layer partially connected at one end and extending over the insulating film, (i) a first layer of the insulating film on an N-type semiconductor substrate; Forming an alumina film (Al ₂ O ₃ film) as a portion; (ii) forming a first opening in the alumina film; and (iii) forming the first opening in the N-type semiconductor substrate. A step of forming a PSG film thereon; (iv) a step of selectively diffusing a P-type impurity into the N-type semiconductor substrate with the PSG film formed; and (v) a step of diffusing the P-type impurity. The PSG of the finished sample
Forming a second alumina film as a second layer portion of the insulating film on the film; and (vi) selecting the second alumina film using hot phosphoric acid and utilizing the difference in their etching rates. Forming a second opening corresponding to the first opening in the second insulating film by selectively etching; and (vii) forming a PS exposed by forming the second opening.
Etching the G film portion using buffered hydrofluoric acid to form a third opening in the PSG film; and (viii) forming the wiring on the second alumina film of the sample in which the third opening has been formed. Forming a layer. 6. The method for manufacturing an LED array according to claim 5, wherein the width L ₂ of the second opening of the second alumina film is larger than the width L ₁ of the first opening of the alumina film in the first layer portion. A method for manufacturing an LED array, wherein the LED array is also large.