JP2868115B2 - Power supply circuit for driving semiconductor integrated circuits - Google Patents
Power supply circuit for driving semiconductor integrated circuitsInfo
- Publication number
- JP2868115B2 JP2868115B2 JP8219884A JP21988496A JP2868115B2 JP 2868115 B2 JP2868115 B2 JP 2868115B2 JP 8219884 A JP8219884 A JP 8219884A JP 21988496 A JP21988496 A JP 21988496A JP 2868115 B2 JP2868115 B2 JP 2868115B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- supply circuit
- semiconductor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Continuous-Control Power Sources That Use Transistors (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体集積回路
に所定の動作電圧（電流）を供給してこの半導体集積回
路を動作状態に駆動する半導体集積回路駆動用電源回路
に関し、特に温度変化や電源電圧の変動等により半導体
集積回路の遅延回路部での遅延時間が変動するのを極力
防止することができる半導体集積回路駆動用電源回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for driving a semiconductor integrated circuit, which supplies a predetermined operating voltage (current) to the semiconductor integrated circuit and drives the semiconductor integrated circuit to an operating state. The present invention relates to a power supply circuit for driving a semiconductor integrated circuit, which can prevent a delay time in a delay circuit portion of a semiconductor integrated circuit from fluctuating due to a voltage fluctuation or the like.
【０００２】[0002]
【従来の技術】例えば半導体メモリのような半導体集積
回路（以下、ＩＣと称す）を試験するためのＩＣ試験装
置（一般にＩＣテスタと呼ばれる）においては、試験を
受けるＩＣ（被試験ＩＣ）に与える所定のパターンのテ
スト信号や、種々の制御信号等を発生させるために各種
のタイミング信号を必要とする。このためＩＣ試験装置
には各種のタイミング信号を発生させるためのタイミン
グ信号発生回路が使用されており、このタイミング信号
発生回路は、一般に、論理ゲート素子よりなる遅延素子
を多数個縦続接続し、この縦続接続された遅延素子の各
段間或いは各出力側から所望の遅延時間を持つタイミン
グ信号を得るように構成した遅延回路を備えている。2. Description of the Related Art For example, in an IC test apparatus (generally called an IC tester) for testing a semiconductor integrated circuit (hereinafter, referred to as an IC) such as a semiconductor memory, an IC to be tested (IC under test) is given. Various timing signals are required to generate a test signal of a predetermined pattern, various control signals, and the like. Therefore, a timing signal generating circuit for generating various timing signals is used in the IC test apparatus. In general, this timing signal generating circuit cascade-connects a large number of delay elements each composed of a logic gate element. There is provided a delay circuit configured to obtain a timing signal having a desired delay time between stages of cascaded delay elements or from each output side.
【０００３】従来、このような縦続接続された多数個の
論理ゲート素子より構成された遅延回路はＴＴＬ (Tran
sistor Transistor Logic)やＥＣＬ (Emitter-CoupledL
ogic)によって構成されていた。ＴＴＬやＥＣＬを使用
した遅延回路は温度変化や電圧の変動によって信号の伝
播遅延時間が殆ど影響を受けないため、この種の遅延回
路では温度変化や電圧の変動はあまり問題にされなかっ
た。Conventionally, a delay circuit composed of a large number of cascade-connected logic gate elements has a TTL (Tran
sistor Transistor Logic) and ECL (Emitter-CoupledL)
ogic). A delay circuit using TTL or ECL is hardly affected by a signal propagation delay time due to a change in temperature or a change in voltage. Therefore, in a delay circuit of this type, a change in temperature or a change in voltage is not much of a problem.
【０００４】近年、遅延回路での消費電力を極力少なく
し、また、集積回路の集積度をより一層高めるためにＭ
ＯＳ構造のＩＣ（ＭＯＳ・ＩＣ）により構成された遅延
回路がＩＣ試験装置のタイミング信号発生回路に用いら
れている。例えば、縦続接続された多数個の論理ゲート
素子をＣＭＯＳ（相補形ＭＯＳ）構造のＩＣとして形成
し、縦続接続された多数個のＣＭＯＳデバイスの各段間
或いは各出力側から遅延時間が異なる信号を取り出すこ
とができるようにした遅延回路は従来より知られてい
る。（例えば、本出願人の特願平６ー１４３９５０号
「タイミング信号発生回路」を参照。） しかしながら、ＭＯＳ・ＩＣによって構成された遅延回
路は温度変化や電圧の変動によって伝播する信号に与え
る遅延時間が比較的大きく変動する難点があり、このた
め精度の高いタイミング信号を発生することができな
い。タイミング信号を高精度に発生することができない
と被試験ＩＣを高精度に試験することができない。従っ
て、ＭＯＳ・ＩＣによって構成された遅延回路の遅延時
間が温度変化や電圧の変動によって影響を受けないよう
にするための方法や装置が従来より数多く提案されてい
る。In recent years, in order to minimize power consumption in a delay circuit and further increase the degree of integration of an integrated circuit, M
2. Description of the Related Art A delay circuit constituted by an IC (MOS · IC) having an OS structure is used for a timing signal generation circuit of an IC test apparatus. For example, a plurality of cascade-connected logic gate elements are formed as CMOS (complementary MOS) structure ICs, and signals having different delay times are output from each stage or from each output side of the cascade-connected many CMOS devices. A delay circuit that can be extracted is conventionally known. (For example, refer to Japanese Patent Application No. 6-143950, “Timing signal generation circuit” of the present applicant.) However, the delay circuit constituted by the MOS-IC has a delay time given to a signal propagated by a temperature change or a voltage change. However, there is a difficulty that the timing signal fluctuates relatively largely, and therefore, a timing signal with high accuracy cannot be generated. If the timing signal cannot be generated with high precision, the IC under test cannot be tested with high precision. Therefore, many methods and devices have been proposed for preventing the delay time of a delay circuit constituted by MOS-IC from being affected by a change in temperature or a change in voltage.
【０００５】一般に、上述のＭＯＳ・ＩＣによって構成
された遅延回路を有するタイミング信号発生回路はＩＣ
試験装置の他の回路と一緒に１つのＩＣチップとして形
成されることがしばしばある。図７はこのようなＩＣチ
ップ上のＩＣのレイアウトの一例を示すもので、タイミ
ング信号発生回路を含むＩＣ試験装置の第１半導体回路
部１と、その他のロジック回路等を含むＩＣ試験装置の
第２半導体回路部２とが１つのＩＣチップ３上に分離さ
れた状態で形成されている。タイミング信号発生回路は
伝播する信号に高精度の遅延時間を与えるためのＣＭＯ
Ｓ・ＩＣによって構成された遅延回路を有する。これら
第１及び第２半導体回路部１及び２には図示しない共通
の１つの電源回路から所定の動作電圧がそれぞれ供給さ
れる。Generally, a timing signal generating circuit having a delay circuit constituted by the above-mentioned MOS IC is an IC
Often formed as one IC chip with other circuits of the test equipment. FIG. 7 shows an example of the layout of an IC on such an IC chip. The first semiconductor circuit section 1 of the IC test apparatus including a timing signal generation circuit and the first semiconductor circuit section 1 of the IC test apparatus including other logic circuits and the like are shown in FIG. The two semiconductor circuit portions 2 are formed on one IC chip 3 in a state where they are separated from each other. A timing signal generating circuit is a CMO for giving a highly accurate delay time to a propagated signal.
It has a delay circuit composed of S · IC. A predetermined operating voltage is supplied to each of the first and second semiconductor circuit units 1 and 2 from one common power supply circuit (not shown).
【０００６】[0006]
【発明が解決しようとする課題】このように構成された
ＩＣチップ３においては、第２半導体回路部２の動作率
が変化し、その消費電力が変化（増加又は減少）する
と、この第２半導体回路部２における発熱量が変化し、
その温度が変化する。第２半導体回路部２の温度が変化
すると、同一チップ上の第１半導体回路部１の温度も変
化し、従ってこの第１半導体回路部１に含まれる遅延回
路のＣＭＯＳ・ＩＣが温度変化の影響を受け、伝播する
信号に与える遅延時間が比較的大きく変動する。よっ
て、高精度の遅延時間を与えることができなくなる。In the IC chip 3 configured as described above, when the operating rate of the second semiconductor circuit section 2 changes and its power consumption changes (increases or decreases), the second semiconductor circuit section 2 changes its operation rate. The amount of heat generated in the circuit section 2 changes,
The temperature changes. When the temperature of the second semiconductor circuit section 2 changes, the temperature of the first semiconductor circuit section 1 on the same chip also changes. Therefore, the CMOS IC of the delay circuit included in the first semiconductor circuit section 1 is affected by the temperature change. As a result, the delay time given to the propagating signal fluctuates relatively largely. Therefore, a highly accurate delay time cannot be given.
【０００７】図８は第２半導体回路部２の消費電力Ｐ2
の変化、従ってその温度Ｔ1 の変化により第１半導体回
路部１の遅延回路の遅延時間τ1 が変動する状態を示す
グラフである。このグラフから、第２半導体回路部２の
消費電力Ｐ2 （従って、温度Ｔ1 ）が増加するに従って
半導体回路部１のＣＭＯＳ・ＩＣによって構成された遅
延回路の遅延時間τ1 が増大することが分かる。FIG. 8 shows the power consumption P 2 of the second semiconductor circuit unit 2.
5 is a graph showing a state in which the delay time τ 1 of the delay circuit of the first semiconductor circuit section 1 fluctuates due to a change in the temperature T 1 and a change in the temperature T 1 . From this graph, it can be seen that the delay time τ 1 of the delay circuit constituted by the CMOS IC of the semiconductor circuit unit 1 increases as the power consumption P 2 of the second semiconductor circuit unit 2 (therefore, the temperature T 1 ) increases. I understand.
【０００８】その上、第１半導体回路部１は電源回路か
ら供給される動作電圧が変動してもその遅延回路の遅延
時間τ1 が変動する。図９は電源電圧Ｅ1 の変動により
第１半導体回路部１の遅延回路の遅延時間τ1 が変動す
る状態を示すグラフである。このグラフから、電源電圧
Ｅ1 が高くなるに従ってＣＭＯＳ・ＩＣによって構成さ
れた遅延回路の遅延時間τ1 が減少することが分かる。
このようなＩＣを駆動する従来の電源回路は、共通の１
つの電源回路から第１及び第２半導体回路部１及び２に
それぞれ動作電圧を供給するか、又は２つの電源回路を
設けて、これら電源回路から第１及び第２半導体回路部
１及び２に別々に動作電圧を供給するように構成されて
いた。いずれの場合にも、第１半導体回路部１の遅延回
路の遅延時間τ1 が温度変化によって変動するのを電源
回路によって防止しようと言う考えはなかった。このた
め第１半導体回路部１の遅延回路の遅延時間が温度及び
電源電圧の変動によって比較的大きく影響を受け、伝播
する信号に高精度の遅延時間を与えることができなかっ
た。In addition, even if the operating voltage supplied from the power supply circuit of the first semiconductor circuit section 1 fluctuates, the delay time τ 1 of the delay circuit fluctuates. FIG. 9 is a graph showing a state in which the delay time τ 1 of the delay circuit of the first semiconductor circuit section 1 fluctuates due to the fluctuation of the power supply voltage E 1 . From this graph, it can be seen that the delay time τ 1 of the delay circuit constituted by the CMOS IC decreases as the power supply voltage E 1 increases.
A conventional power supply circuit for driving such an IC has a common one.
One power supply circuit supplies operating voltages to the first and second semiconductor circuit sections 1 and 2 respectively, or two power supply circuits are provided, and the first and second semiconductor circuit sections 1 and 2 are separately supplied from these power supply circuits. It is configured to supply an operating voltage to the power supply. In either case, the delay time tau 1 of the first delay circuit of the semiconductor circuit portion 1 was not idea of trying to prevent the power circuit from varying due to temperature change. For this reason, the delay time of the delay circuit of the first semiconductor circuit section 1 is relatively greatly affected by changes in the temperature and the power supply voltage, and a highly accurate delay time cannot be given to a propagated signal.
【０００９】この発明の目的は、ＩＣによって構成され
た遅延回路の遅延時間が温度変化によって影響を受ける
のを極力防止することができるＩＣ駆動用電源回路を提
供することである。An object of the present invention is to provide an IC driving power supply circuit capable of preventing a delay time of a delay circuit constituted by an IC from being affected by a temperature change as much as possible.
【００１０】[0010]
【課題を解決するための手段】請求項１の発明によれ
ば、第１半導体回路部と第２半導体回路部とがＩＣとし
て一体的に形成された１つのＩＣチップであって、かつ
上記第１半導体回路部は、伝播する信号に高精度の遅延
時間を与えるためのＩＣより構成された遅延回路を有
し、この遅延回路の遅延時間が、上記第２半導体回路部
の消費電力の変化により変化するとともに上記第１半導
体回路部に供給される電源電圧の変動により変化する、
１つのＩＣチップを駆動するＩＣ駆動用電源回路におい
て、上記第１半導体回路部に動作電圧を供給する第１電
源回路と、上記第２半導体回路部に動作電圧を供給する
と共に、上記第１電源回路の出力電圧を変化させる第２
電源回路とを具備し、上記第２電源回路によって、温度
に起因する上記第１半導体回路部の遅延回路の遅延時間
の変動をキャンセルするように、上記第２半導体回路部
の消費電力の変化に応じて、上記第１電源回路の出力電
圧を制御するＩＣ駆動用電源回路が提供される。According to the first aspect of the present invention, the first semiconductor circuit section and the second semiconductor circuit section are one IC chip integrally formed as an IC, and One semiconductor circuit unit has a delay circuit constituted by an IC for giving a highly accurate delay time to a signal to be propagated, and the delay time of the delay circuit is changed by the change in power consumption of the second semiconductor circuit unit. And changes due to fluctuations in the power supply voltage supplied to the first semiconductor circuit unit.
In an IC driving power supply circuit for driving one IC chip, a first power supply circuit for supplying an operation voltage to the first semiconductor circuit section, and an operation voltage for supplying an operation voltage to the second semiconductor circuit section, Second to change the output voltage of the circuit
A power supply circuit, wherein the second power supply circuit adjusts the change in the power consumption of the second semiconductor circuit unit so as to cancel the fluctuation of the delay time of the delay circuit of the first semiconductor circuit unit caused by the temperature. Accordingly, an IC driving power supply circuit for controlling the output voltage of the first power supply circuit is provided.
【００１１】請求項２の発明においては、上記第２電源
回路は時定数回路を有し、この時定数回路に、上記第２
半導体回路部の消費電力が変化した時点から上記第１半
導体回路部の温度が変化する迄の時間遅れに対応する上
記第１半導体回路部の温度時定数にほぼ等しい時定数を
持たせ、この時定数だけ遅らせて上記第２電源回路は上
記第１電源回路の出力電圧を制御する。According to the second aspect of the present invention, the second power supply circuit has a time constant circuit, and the time constant circuit includes the second power supply circuit.
A time constant substantially equal to the temperature time constant of the first semiconductor circuit portion corresponding to the time delay from the time when the power consumption of the semiconductor circuit portion changes to the time when the temperature of the first semiconductor circuit portion changes is provided. The second power supply circuit controls the output voltage of the first power supply circuit with a delay by a constant.
【００１２】請求項３の発明においては、上記第１電源
回路は時定数回路を有し、この時定数回路に、上記第２
半導体回路部の消費電力が変化した時点から上記第１半
導体回路部の温度が変化する迄の時間遅れに対応する上
記第１半導体回路部の温度時定数にほぼ等しい時定数を
持たせ、上記第１電源回路は、上記第２電源回路から電
源電圧が供給されたときに、上記時定数だけ遅らせてそ
の出力電圧を変化させる。According to a third aspect of the present invention, the first power supply circuit has a time constant circuit, and the time constant circuit includes the second power supply circuit.
A time constant that is substantially equal to a temperature time constant of the first semiconductor circuit portion corresponding to a time delay from a point in time when the power consumption of the semiconductor circuit portion changes to a temperature change in the first semiconductor circuit portion; The one power supply circuit changes its output voltage with a delay of the time constant when the power supply voltage is supplied from the second power supply circuit.
【００１３】請求項４の発明においては、上記ＩＣチッ
プの温度を検出するセンサを設け、このセンサの出力に
よって上記第１電源回路の出力電圧を制御する。請求項
５の発明においては、上記第２電源回路は、コレクタが
直流電源に接続され、エミッタが電流／電圧変換器を介
して上記第２半導体回路部に電源電圧を供給するための
出力端子に接続されているトランジスタを含むトランジ
スタ回路と、上記第２電源回路の出力端子から出力され
る電源電圧と基準電圧との差値を増幅し、その増幅した
出力電圧を上記トランジスタのベースに与えて、上記第
２電源回路の出力端子からの電源電圧が上記基準電圧に
ほぼ等しくなるように制御する差動増幅回路とを含み、
上記電流／電圧変換器で変換された電圧を上記第１電源
回路に供給して上記第１電源回路の出力電圧を制御す
る。According to a fourth aspect of the present invention, a sensor for detecting the temperature of the IC chip is provided, and the output voltage of the first power supply circuit is controlled by the output of the sensor. According to a fifth aspect of the present invention, in the second power supply circuit, a collector is connected to a DC power supply, and an emitter is connected to an output terminal for supplying a power supply voltage to the second semiconductor circuit unit via a current / voltage converter. A transistor circuit including a connected transistor, and amplifying a difference value between a power supply voltage and a reference voltage output from an output terminal of the second power supply circuit, and applying the amplified output voltage to a base of the transistor; A differential amplifier circuit that controls a power supply voltage from an output terminal of the second power supply circuit to be substantially equal to the reference voltage,
The voltage converted by the current / voltage converter is supplied to the first power supply circuit to control an output voltage of the first power supply circuit.
【００１４】請求項６の発明においては、上記第２電源
回路は、上記電流／電圧変換器の上記第１電源回路に対
する出力側に、上記第１半導体回路部の温度時定数にほ
ぼ等しい時定数を有するローパスフィルタをさらに含ん
でいる。請求項７の発明においては、上記第１電源回路
は、上記第１半導体回路部の温度時定数にほぼ等しい時
定数を有するローパスフィルタをさらに含んでいる。According to a sixth aspect of the present invention, the second power supply circuit includes a time constant substantially equal to a temperature time constant of the first semiconductor circuit section on an output side of the current / voltage converter with respect to the first power supply circuit. And a low-pass filter having In the invention according to claim 7, the first power supply circuit further includes a low-pass filter having a time constant substantially equal to a temperature time constant of the first semiconductor circuit portion.
【００１５】[0015]
【発明の実施の形態】以下、この発明によるＩＣ駆動用
電源回路の実施例について図１〜図６を参照して詳細に
説明する。なお、以下においては、説明を簡明にするた
めに、この発明をＩＣ試験装置に適用した場合について
説明する。また、タイミング信号発生回路の遅延回路が
ＭＯＳ・ＩＣ、特にＣＭＯＳ・ＩＣによって構成されて
いる場合を例に取って説明するが、この発明がそれらに
限定されるものでないことは言うまでもない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an IC driving power supply circuit according to the present invention will be described below in detail with reference to FIGS. In the following, a case where the present invention is applied to an IC test apparatus will be described for the sake of simplicity. Further, the case where the delay circuit of the timing signal generation circuit is constituted by a MOS IC, particularly a CMOS IC will be described as an example, but it is needless to say that the present invention is not limited thereto.
【００１６】図１はこの発明によるＩＣ駆動用電源回路
の第１の実施例を示すブロック図である。電源回路によ
って駆動されるＩＣチップ３には、図７に示したよう
に、伝播する信号に高精度の遅延時間を与えるためのＣ
ＭＯＳ・ＩＣによって構成された遅延回路を有するタイ
ミング信号発生回路を含む第１半導体回路部１と、その
他のロジック回路等を含む第２半導体回路部２とがそれ
ぞれ形成されている。FIG. 1 is a block diagram showing a first embodiment of an IC driving power supply circuit according to the present invention. As shown in FIG. 7, the IC chip 3 driven by the power supply circuit has a C for giving a highly accurate delay time to the propagated signal.
A first semiconductor circuit section 1 including a timing signal generating circuit having a delay circuit constituted by a MOS IC and a second semiconductor circuit section 2 including other logic circuits and the like are formed.
【００１７】この発明においてはＩＣチップ３を駆動す
る電源回路を、上記遅延回路を含む第１半導体回路部１
を駆動する第１電源回路５と、上記その他のロジック回
路等を含む第２半導体回路部２を駆動する第２電源回路
６とに分離するとともに、この第２電源回路６によって
制御信号線７を通じて第１電源回路５を制御してその電
源電圧Ｅ1 を変化させることができるように構成したも
のである。この第２電源回路６の制御は、第２半導体回
路部２の消費電力Ｐ2 が変化し、それによって第２半導
体回路部２の温度が変化して第１半導体回路部１の遅延
回路の遅延時間が変化したときに、第１半導体回路部１
に供給される第１電源回路５の電源電圧Ｅ1 を、この遅
延回路の遅延時間の変化をキャンセルする方向に変化さ
せるものである。つまり、第２半導体回路部２の消費電
力Ｐ2 の変化に応じて、第１半導体回路部１の遅延回路
の遅延時間の変化をキャンセルするように、第１電源回
路５の電源電圧Ｅ1 を制御するものである。In the present invention, the power supply circuit for driving the IC chip 3 is replaced with the first semiconductor circuit section 1 including the delay circuit.
And a second power supply circuit 6 for driving the second semiconductor circuit portion 2 including the other logic circuits and the like, and the second power supply circuit 6 controls the second power supply circuit 6 through a control signal line 7. those configured to be able to change its power supply voltage E 1 and controls the first power supply circuit 5. The control of the second power supply circuit 6 is performed by changing the power consumption P 2 of the second semiconductor circuit unit 2, thereby changing the temperature of the second semiconductor circuit unit 2 and delaying the delay circuit of the first semiconductor circuit unit 1. When the time changes, the first semiconductor circuit unit 1
The power supply voltage E 1 of the first power supply circuit 5 is supplied to, thereby changing the direction of canceling the change in the delay time of the delay circuit. That is, the power supply voltage E 1 of the first power supply circuit 5 is changed so as to cancel the change in the delay time of the delay circuit of the first semiconductor circuit section 1 in accordance with the change in the power consumption P 2 of the second semiconductor circuit section 2. To control.
【００１８】従来技術のＩＣ駆動用電源回路に関連して
前記したように、第１半導体回路部１のＣＭＯＳ・ＩＣ
によって構成された遅延回路の遅延時間τ1 は、第２半
導体回路部２の消費電力Ｐ2 が変化し、その温度Ｔ1 が
変化すると、図２に示すように変化し、また、第１半導
体回路部１に第１電源回路５から供給される動作電圧Ｅ
1 が変動すると、その遅延回路の遅延時間τ1 が図９に
示すように変化する。よって、上記この発明の第１の実
施例によれば、第２半導体回路部２の消費電力Ｐ2 が例
えば増大し、それによって第２半導体回路部２の温度が
高くなって第１半導体回路部１の遅延回路の遅延時間τ
1 が増大したときに、第１半導体回路部１に供給される
第１電源回路５の電源電圧Ｅ1 を高くすることになるか
ら、図９に示すように遅延回路の遅延時間τ1 は減少す
る。従って、第２半導体回路部２の温度上昇による遅延
回路の遅延時間τ1 の増大を、第１半導体回路部１に供
給される第１電源回路５の電源電圧Ｅ1 を高くすること
によってキャンセルすることが可能となる。かくして、
遅延回路を伝播する信号に高精度の遅延時間を与えるこ
とができ、所望とするタイミング信号を高精度で得るこ
とができる。As described above with reference to the prior art IC driving power supply circuit, the CMOS IC of the first semiconductor circuit section 1 is used.
Delay time tau 1 of the delay circuit formed by the power P 2 of the second semiconductor circuit section 2 is changed, the temperature T 1 is changed, changes as shown in FIG. 2, also, the first semiconductor The operating voltage E supplied from the first power supply circuit 5 to the circuit section 1
When 1 fluctuates, the delay time τ 1 of the delay circuit changes as shown in FIG. Therefore, the according to the first embodiment of the present invention, the power consumption P 2 of the second semiconductor circuit section 2 is for example increased, whereby the first semiconductor circuit portion higher temperature of the second semiconductor circuit section 2 1 delay time τ
When 1 is increased, since thus increasing the power supply voltage E 1 of the first power supply circuit 5 is supplied to the first semiconductor circuit section 1, a delay time tau 1 of the delay circuit as shown in FIG. 9 decreases I do. Therefore, the increase in the delay time τ 1 of the delay circuit due to the temperature rise of the second semiconductor circuit unit 2 is canceled by increasing the power supply voltage E 1 of the first power supply circuit 5 supplied to the first semiconductor circuit unit 1. It becomes possible. Thus,
A highly accurate delay time can be given to a signal propagating through the delay circuit, and a desired timing signal can be obtained with high accuracy.
【００１９】図１に示す第１の実施例では、第１及び第
２電源回路５及び６の入力端子ＩＮ１及びＩＮ２に直流
電源４から電圧Ｅをそれぞれ供給し、これら電源回路５
及び６の出力端子ＯＵＴ１及びＯＵＴ２から電源電圧
（動作電圧）Ｅ1 及びＥ2 を対応する第１及び第２半導
体回路部１及び２にそれぞれ供給するように構成した
が、図２に示すこの発明の第２の実施例のように、第２
電源回路６にのみ直流電源４から電圧Ｅを供給し、この
第２電源回路６から、電源線を兼用した制御信号線７ａ
を介して、所定の直流電圧を第１電源回路５の入力端子
ＩＮ１に供給するように構成してもよい。In the first embodiment shown in FIG. 1, a voltage E is supplied from a DC power supply 4 to input terminals IN1 and IN2 of first and second power supply circuits 5 and 6, respectively.
The power supply voltages (operating voltages) E 1 and E 2 are supplied from the output terminals OUT 1 and OUT 2 of the first and second semiconductor circuits 1 and 2 to the corresponding first and second semiconductor circuit units 1 and 2, respectively. As in the second embodiment,
The voltage E is supplied from the DC power supply 4 only to the power supply circuit 6, and the control signal line 7 a serving also as the power supply line is supplied from the second power supply circuit 6.
, A predetermined DC voltage may be supplied to the input terminal IN <b> 1 of the first power supply circuit 5.
【００２０】図３はこの第２の実施例の第１及び第２電
源回路５及び６の一具体例をそれぞれ示す。第２電源回
路６は、ｎｐｎトランジスタＱを含むトランジスタ回路
１１と、差動増幅器１２と、電流／電圧変換器８と、抵
抗器ＲとコンデンサＣよりなるローパスフィルタ（ＬＰ
Ｆ）９とを含み、トランジスタＱのコレクタは第２電源
回路６の入力端子ＩＮ２に接続され、エミッタは電流／
電圧変換器８の入力ポートに接続されるとともにローパ
スフィルタ９の入力ポートに接続され、ベースは差動増
幅器１２の出力ポートに接続されている。また、電流／
電圧変換器８の出力ポートは第２電源回路６の出力端子
ＯＵＴ２に接続されるとともに差動増幅器１２の−（マ
イナス）入力ポートに接続されている。FIG. 3 shows a specific example of the first and second power supply circuits 5 and 6 of the second embodiment. The second power supply circuit 6 includes a transistor circuit 11 including an npn transistor Q, a differential amplifier 12, a current / voltage converter 8, a low-pass filter (LP) including a resistor R and a capacitor C.
F) 9, the collector of the transistor Q is connected to the input terminal IN2 of the second power supply circuit 6, and the emitter is
It is connected to the input port of the voltage converter 8 and to the input port of the low-pass filter 9, and the base is connected to the output port of the differential amplifier 12. The current /
The output port of the voltage converter 8 is connected to the output terminal OUT2 of the second power supply circuit 6 and to the-(minus) input port of the differential amplifier 12.
【００２１】上記構成において、トランジスタＱのコレ
クタに電源４より直流電圧Ｅが供給されると、トランジ
スタＱはベースバイアス電圧Ｖ0 によって導通状態にあ
るから、エミッタ電流が流れる。このエミッタ電流は電
流／電圧変換器８（この例では抵抗器Ｒ）を通って第２
電源回路６の出力端子ＯＵＴ２に供給され、この際エミ
ッタ電流は電流／電圧変換器８で電圧に変換される。こ
の変換された電圧はローパスフィルタ８を介して第１電
源回路５の入力端子ＩＮ１に電源電圧Ｅ3 として供給さ
れる。ここで、ローパスフィルタ９を介して第１電源回
路５に流れる電流は、第１電源回路５のバッファ回路１
０の入力インピーダンスが非常に高いので、無視し得る
程度であり、従って、エミッタ電流は実質的に殆どが電
流／電圧変換器８を通って出力端子ＯＵＴ２に流れる。
ここではこの電流をエミッタ電流Ｉ2 と称する。In the above configuration, when the DC voltage E is supplied from the power supply 4 to the collector of the transistor Q, the transistor Q is conducting by the base bias voltage V 0 , so that the emitter current flows. This emitter current is passed through a current / voltage converter 8 (resistor R in this example) to a second
The current is supplied to the output terminal OUT2 of the power supply circuit 6. At this time, the emitter current is converted into a voltage by the current / voltage converter 8. The converted voltage is supplied to the input terminal IN1 of the first power supply circuit 5 via the low-pass filter 8 as the power supply voltage E 3. Here, the current flowing to the first power supply circuit 5 through the low-pass filter 9 is equal to the current flowing through the buffer circuit 1 of the first power supply circuit 5.
The input impedance of 0 is so high that it is negligible, so that substantially all of the emitter current flows through the current / voltage converter 8 to the output terminal OUT2.
It is referred to herein as the current and the emitter current I 2.
【００２２】差動増幅器１２の＋（プラス）入力ポート
には基準電圧Ｖr が供給されているから、その−入力ポ
ートに供給される電圧、つまり、第２電源回路６の電源
電圧Ｅ2 との差（Ｖr −Ｅ2 ）を増幅してその出力ポー
トからバイアス電圧Ｖ0 としてトランジスタＱのベース
に供給する。差動増幅器１２の利得は非常に大きいか
ら、トランジスタＱ、電流／電圧変換器８、及び差動増
幅器１２からなるフィードバック回路によって第２電源
回路６の電源電圧Ｅ2 をほぼ基準電圧Ｖr に等しい一定
値に制御することができる。[0022] Since the reference voltage V r in + (plus) input port of the differential amplifier 12 is supplied, the - voltage applied to the input port, i.e., the power supply voltage E 2 of the second power supply circuit 6 supplied to the base of the transistor Q from the output port as the bias voltage V 0 amplifies the difference (V r -E 2). Since the gain of the differential amplifier 12 is very large, equal to the transistor Q, substantially the reference voltage V r to the power source voltage E 2 of the second power supply circuit 6 by a feedback circuit consisting of a current / voltage converter 8 and a differential amplifier 12, It can be controlled to a constant value.
【００２３】次に、上述した第２電源回路６の制御動作
について具体的に説明する。今、差動増幅器１２の利得
をＡとすれば、次式が成り立つ。 （Ｖr −Ｅ2 ）Ａ＝Ｖ0 ・・・（１） エミッタ電圧Ｖe は、ベース・エミッタ電圧をＶbeとす
れば、 Ｖe ＝Ｖ0 −Ｖbe ＝（Ｖr −Ｅ2 ）Ａ−Ｖbe ・・・（２） 電流／電圧変換器８の入力インピーダンスをＺ（この例
ではＺ＝Ｒ）とすれば、その入力ポートの電圧Ｉ2 Ｚは Ｉ2 Ｚ＝Ｖe −Ｅ2 ＝（Ｖr −Ｅ2 ）Ａ−Ｖbe−Ｅ2 ＝Ｖr Ａ−Ｅ2 （Ａ＋１）−Ｖbe ・・・（３） 第２半導体回路部２の全負荷インピーダンスをＺ2 とす
れば、 Ｅ2 ＝Ｚ2 Ｉ2 ・・・（４） （４）式を（３）式に代入すれば Ｉ2 Ｚ＝Ｖr Ａ−Ｚ2 Ｉ2 （Ａ＋１）−Ｖbe ∴Ｉ2 ＝（Ｖr Ａ−Ｖbe）／｛Ｚ＋Ｚ2 （Ａ＋１）｝ ＝（Ｖr −Ｖbe／Ａ）／｛Ｚ／Ａ＋Ｚ2 （１＋１／Ａ）｝・・（５） 上述したように差動増幅器１２の利得Ａは極めて大きい
ので、Ｖbe／Ａ≒０、Ｚ／Ａ≒０、１／Ａ≒０とみなせ
る。Next, the control operation of the second power supply circuit 6 will be specifically described. Now, assuming that the gain of the differential amplifier 12 is A, the following equation holds. (V r -E 2) A = V 0 ··· (1) the emitter voltage V e, if the base-emitter voltage V be, V e = V 0 -V be = (V r -E 2) A−V be (2) Assuming that the input impedance of the current / voltage converter 8 is Z (Z = R in this example), the voltage I 2 Z of the input port is I 2 Z = V e −E 2 = (V r -E 2) a full load impedance of a-V be -E 2 = V r a-E 2 (a + 1) -V be ··· (3) second semiconductor circuit section 2 by a Z 2 if, E 2 = Z 2 I 2 ··· (4) substituting (4) into (3) I 2 Z = V r a- Z 2 I 2 (a + 1) -V be ∴I 2 = (V r A-V be) / {Z + Z 2 (A + 1)} = (V r -V be / A) / {Z / A + Z 2 (1 + 1 / A)} ·· (5) differential as described above amplifier since the gain a of 12 is extremely large, V be / a 0, it can be regarded as a Z / A ≒ 0,1 / A ≒ 0.
【００２４】 ∴Ｉ2 ≒Ｖr ／Ｚ2 ∴Ｖr ≒Ｉ2 Ｚ2 ＝Ｅ2 ・・・（６） 上式（６）から、第２電源回路６の電源電圧（出力電
圧）Ｅ2 は基準電圧Ｖr にほぼ等しい電圧になるように
制御されることが分かる。第２半導体回路部２の消費電
力Ｐ2 は Ｐ2 ＝Ｅ2 Ｉ2 ≒Ｖr Ｉ2 ・・・（７） よって、消費電力Ｐ2 はエミッタ電流Ｉ2 にほぼ比例す
る。∴I 2 ≒ V r / Z 2 ∴V r ≒ I 2 Z 2 = E 2 (6) From the above equation (6), the power supply voltage (output voltage) E 2 of the second power supply circuit 6 it can be seen that is controlled to be substantially equal voltage to the reference voltage V r. The power consumption P 2 of the second semiconductor circuit unit 2 is P 2 = E 2 I 2 ≒ V r I 2 (7) Therefore, the power consumption P 2 is almost proportional to the emitter current I 2 .
【００２５】一方、エミッタ電流は電流／電圧変換器８
で電圧に変換され、この電圧がローパスフィルタ９でフ
ィルタされて電圧Ｅ3 として第２電源回路６から出力さ
れるが、この電圧Ｅ3 はこの例ではＤＣ的にはエミッタ
電圧Ｖｅに等しい。よって、次式が成り立つ。 Ｅ3 ＝Ｖe ＝ＺＩ2 ＋Ｅ2 ≒ＺＩ2 ＋Ｖr ≒ＺＰ2 ／Ｖr ＋Ｖr ・・（８） この式（８）から第２半導体回路部２の消費電力Ｐ2 に
応じて変化する電源電圧Ｅ3 がバッファ回路１０とツェ
ナーダイオードＤｚにより構成された第１電源回路５に
供給されることが分かる。その結果、第１電源回路５の
電源電圧Ｅ1 は、ツェナーダイオードＤｚでの電圧降下
分をＶZ とすると、 Ｅ1 ＝Ｅ3 −ＶZ ＝ＺＰ2 ／Ｖr ＋Ｖr −Ｖz ・・・（９） となる。よって、第１電源回路５の電源電圧Ｅ1 は、図
４に示すように第２半導体回路６の消費電力Ｐ2 の変化
に応じて変化する。図４から、例えば第２半導体回路６
の消費電力Ｐ2 が増大すると比例的に第１電源回路５の
電源電圧Ｅ1 が高くなり、第２半導体回路６の消費電力
Ｐ2 が減少すると比例的に第１電源回路５の電源電圧Ｅ
1 が低くなることが分かる。On the other hand, the emitter current is the current / voltage converter 8
In is converted to a voltage, this voltage is output is filtered by the low pass filter 9 from the second power supply circuit 6 as the voltage E 3, the voltage E 3 in this example is equal to the emitter voltage Ve in a DC manner. Therefore, the following equation holds. E 3 = V e = ZI 2 + E 2 ≒ ZI 2 + V r ≒ Z P 2 / V r + V r (8) From this equation (8), it changes according to the power consumption P 2 of the second semiconductor circuit unit 2. the power supply voltage E 3 it can be seen that supplied to the first power supply circuit 5 constituted by the buffer circuit 10 and a Zener diode Dz. As a result, the power supply voltage E 1 of the first power supply circuit 5, when the voltage drop at the Zener diode Dz and V Z, E 1 = E 3 -V Z = ZP 2 / V r + V r -V z ··・ (9) Therefore, the power supply voltage E 1 of the first power supply circuit 5 changes according to the change of power P 2 of the second semiconductor circuit 6 as shown in FIG. From FIG. 4, for example, the second semiconductor circuit 6
Power P 2 proportionally higher power supply voltage E 1 of the first power supply circuit 5 and increases the power supply voltage proportionally first power supply circuit 5 and the power consumption P 2 of the second semiconductor circuit 6 is decreased E
It turns out that 1 becomes low.
【００２６】かくして、第２半導体回路６の消費電力Ｐ
2 の増大（減少）に応じて第１電源回路５の電源（出
力）電圧Ｅ1 が高く（低く）なると、第１半導体回路部
１の遅延回路の遅延時間τ1 は図９に示すように減少
（増加）し、消費電力Ｐ2 の増大（減少）に起因する遅
延時間τ1 の増加分をキャンセルすることができる。と
ころで、第２半導体回路部２の消費電力Ｐ2 がΔＰ2 増
加（減少）した時点から、第１半導体回路部１の温度Ｔ
1 がΔＴ1 上昇（降下）すると共に遅延回路の遅延時間
τ1 がΔτ1 増加（減少）する時点迄には多少の時間遅
れτd が存在する。そのため第２電源回路６は、第１半
導体回路部１の時間遅れτd に対応する温度時定数にほ
ぼ等しい時定数をもって、第１電源回路５の電源電圧Ｅ
1 を制御することが望ましい。このため、この実施例で
は第２電源回路６にローパスフィルタ９を挿入し、この
ローパスフィルタ９によって第１電源回路５に供給する
電源電圧Ｅ3 に、第１半導体回路部１の時間遅れτd に
対応する温度時定数にほぼ等しい時定数を持たせ、実質
的にτd だけ遅らせて電源電圧Ｅ3 を第１電源回路５に
供給するようにしている。なお、第１電源回路５のバッ
ファ回路１０は電圧利得が１のバッファ（電圧ホロア回
路）であり、電圧源として電流供給能力を持たせるため
に設けている。Thus, the power consumption P of the second semiconductor circuit 6
When the power supply (output) voltage E 1 of the first power supply circuit 5 increases (lowers) in accordance with the increase (decrease) of 2 , the delay time τ 1 of the delay circuit of the first semiconductor circuit unit 1 becomes as shown in FIG. Decrease (increase), and an increase in the delay time τ 1 caused by increase (decrease) in the power consumption P 2 can be canceled. By the way, from the time when the power consumption P 2 of the second semiconductor circuit unit 2 increases (decreases) by ΔP 2 , the temperature T of the first semiconductor circuit unit 1
1 the delay time tau 1 of the delay circuit is until time of .DELTA..tau 1 increases (decreases) there is some time delay tau d with [Delta] T 1 rises (drops). Therefore, the second power supply circuit 6 supplies the power supply voltage E of the first power supply circuit 5 with a time constant substantially equal to the temperature time constant corresponding to the time delay τ d of the first semiconductor circuit section 1.
It is desirable to control one . For this reason, in this embodiment, a low-pass filter 9 is inserted into the second power supply circuit 6, and the power supply voltage E 3 supplied to the first power supply circuit 5 by the low-pass filter 9 causes the time delay τ d of the first semiconductor circuit unit 1. The power supply voltage E 3 is supplied to the first power supply circuit 5 with a delay substantially equal to τ d . Note that the buffer circuit 10 of the first power supply circuit 5 is a buffer (voltage follower circuit) having a voltage gain of 1, and is provided to have a current supply capability as a voltage source.
【００２７】また、第２電源回路６に挿入したローパス
フィルタ９を第１電源回路５の入力側（例えばバッファ
回路１０の前段又は後段）に挿入し、第２電源回路６か
らは電流／電圧変換器８の電圧をそのまま電源電圧Ｅ3
として第１電源回路５に供給し、第１電源回路５におい
て供給された電源電圧Ｅ3 にローパスフィルタにより第
１半導体回路部１の温度時定数にほぼ等しい時定数を持
たせて、出力電圧Ｅ1を実質的にτd だけ遅らせて変化
させるようにしても同じ効果が得られる。Further, the low-pass filter 9 inserted in the second power supply circuit 6 is inserted into the input side of the first power supply circuit 5 (for example, before or after the buffer circuit 10), and the current / voltage conversion from the second power supply circuit 6 is performed. Power supply voltage E 3
The first power supply circuit 5 supplies the power supply voltage E 3 with a time constant substantially equal to the temperature time constant of the first semiconductor circuit unit 1 by a low-pass filter, and the output voltage E 3 The same effect can be obtained by changing 1 with a delay substantially by τ d .
【００２８】さらに、ＩＣチップ３の温度を検出する温
度センサ１４を設け、このセンサ１４の出力を図１又は
図２の第１電源回路５に供給し、第１電源回路５の出力
電圧Ｅ1 を温度センサ１４の出力によってさらに制御す
る、つまり、微調整するように構成すれば、第１半導体
回路部１の遅延時間の時間遅れτd を高精度に補償する
ことができる。図５はこの発明の第３の実施例を示すブ
ロック図であり、図１の第１の実施例に温度センサ１４
を付加した場合を示す。また、図６は図２の第２の実施
例に温度センサ１４を付加したこの発明の第４の実施例
を示す。両実施例とも第１電源回路５から出力される電
源電圧を温度センサ１４の出力信号によって補正するよ
うにしているが、第１電源回路５に入力される電圧を温
度センサ１４の出力信号によって補正するようにしても
よい。Furthermore, a temperature sensor 14 for detecting the temperature of the IC chip 3 is provided, the output of the sensor 14 is supplied to the first power supply circuit 5 of FIG. 1 or FIG. 2, the output voltage of the first power supply circuit 5 E 1 Is further controlled by the output of the temperature sensor 14, that is, fine adjustment is performed, so that the time delay τ d of the delay time of the first semiconductor circuit unit 1 can be compensated with high accuracy. FIG. 5 is a block diagram showing a third embodiment of the present invention. In the first embodiment shown in FIG.
Shows the case where is added. FIG. 6 shows a fourth embodiment of the present invention in which a temperature sensor 14 is added to the second embodiment of FIG. In both embodiments, the power supply voltage output from the first power supply circuit 5 is corrected by the output signal of the temperature sensor 14, but the voltage input to the first power supply circuit 5 is corrected by the output signal of the temperature sensor 14. You may make it.
【００２９】なお、上記各実施例は第１半導体回路部１
の遅延回路がＣＭＯＳ・ＩＣによって構成されている場
合を例に取って説明したが、遅延回路がＭＯＳ・ＩＣに
よって構成されている場合にも、或いはＭＯＳ・ＩＣ以
外のＩＣによって構成されている場合にも、この発明が
適用でき、同様の作用効果が得られることは言うまでも
ない。In each of the above embodiments, the first semiconductor circuit unit 1
Has been described by taking as an example the case where the delay circuit is constituted by a CMOS IC, but also when the delay circuit is constituted by a MOS IC, or when the delay circuit is constituted by an IC other than the MOS IC Needless to say, the present invention can be applied and the same effects can be obtained.
【００３０】なお、この明細書で記載した「遅延回路」
は、たとえ遅延回路と言う名称が付いていない回路で
も、入力信号が所定の時間遅れて出力される回路を全て
含むものである。[0030] It should be noted, was described in this specification to "delay circuit"
Includes all circuits in which an input signal is output with a predetermined delay, even if the circuit is not named delay circuit.
【００３１】[0031]
【発明の効果】以上の説明から明白なように、この発明
によれば、高精度の遅延時間を与えるためのＩＣによっ
て構成された遅延回路を含む第１半導体回路部１と、そ
の他のロジック回路等を含む第２半導体回路部２とにそ
れぞれ別々に動作電圧を供給する第１及び第２電源回路
５及び６を設け、第２電源回路６によって、第２半導体
回路部２の消費電力Ｐ2 の変化に応じて、第１電源回路
５の動作電圧を変化させて第１半導体回路部１の温度に
起因する遅延時間の変動をキャンセルするようにしたの
で、第１半導体回路部１の遅延時間の温度変動を従来よ
り大幅に減少させることができるという顕著な利点があ
る。As is apparent from the above description, according to the present invention, the first semiconductor circuit section 1 including a delay circuit constituted by an IC for providing a highly accurate delay time, and other logic circuits The first and second power supply circuits 5 and 6 for separately supplying operating voltages to the second semiconductor circuit section 2 including the same are provided, and the power consumption P 2 of the second semiconductor circuit section 2 is controlled by the second power supply circuit 6. In response to the change in the operating voltage of the first power supply circuit 5, the fluctuation of the delay time caused by the temperature of the first semiconductor circuit unit 1 is cancelled. There is a remarkable advantage that the temperature fluctuation can be greatly reduced as compared with the conventional case.
【図１】この発明によるＩＣ駆動用電源回路の第１の実
施例を示すブロック図である。FIG. 1 is a block diagram showing a first embodiment of an IC driving power supply circuit according to the present invention.
【図２】この発明によるＩＣ駆動用電源回路の第２の実
施例を示すブロック図である。FIG. 2 is a block diagram showing a second embodiment of an IC driving power supply circuit according to the present invention.
【図３】図２に示す第２の実施例の一具体例を示す回路
接続図である。FIG. 3 is a circuit connection diagram showing a specific example of the second embodiment shown in FIG. 2;
【図４】図１及び図２に示す実施例の第１電源回路５の
出力電圧Ｅ1 と第２半導体回路部２の消費電力Ｐ2 との
関係を示す特性図である。FIG. 4 is a characteristic diagram showing a relationship between an output voltage E 1 of a first power supply circuit 5 and power consumption P 2 of a second semiconductor circuit unit 2 of the embodiment shown in FIGS. 1 and 2;
【図５】この発明によるＩＣ駆動用電源回路の第３の実
施例を示すブロック図である。FIG. 5 is a block diagram showing a third embodiment of an IC driving power supply circuit according to the present invention.
【図６】この発明によるＩＣ駆動用電源回路の第４の実
施例を示すブロック図である。FIG. 6 is a block diagram showing a fourth embodiment of an IC drive power supply circuit according to the present invention.
【図７】１つのＩＣチップ上のＩＣのレイアウトの一例
を説明するための概略平面図である。FIG. 7 is a schematic plan view for explaining an example of an IC layout on one IC chip.
【図８】図７に示すＩＣの第１半導体回路部に含まれる
遅延回路の遅延時間τ1 と第２半導体回路部の消費電力
Ｐ2 との関係を示す特性図である。8 is a characteristic diagram showing a relationship between a delay time τ 1 of a delay circuit included in a first semiconductor circuit unit of the IC shown in FIG. 7 and power consumption P 2 of a second semiconductor circuit unit.
【図９】図７に示すＩＣの第１半導体回路部に含まれる
遅延回路の遅延時間τ1 と電源電圧Ｅ1 との関係を示す
特性図である。9 is a characteristic diagram showing a relationship between a delay time τ 1 of a delay circuit included in a first semiconductor circuit portion of the IC shown in FIG. 7 and a power supply voltage E 1 .
１：第１半導体回路部 ２：第２半導体回路部 ３：ＩＣチップ ４：直流電源 ５：第１電源回路 ６：第２電源回路 ７、７ａ：制御信号線 ８：電流／電圧変換器 ９：ローパスフィルタ １１：トランジスタ回路 １４：温度センサ 1: First semiconductor circuit section 2: Second semiconductor circuit section 3: IC chip 4: DC power supply 5: First power supply circuit 6: Second power supply circuit 7, 7a: Control signal line 8: Current / voltage converter 9: Low-pass filter 11: Transistor circuit 14: Temperature sensor
Claims (7)
が半導体集積回路として一体的に形成された１つの半導
体集積回路チップであって、かつ上記第１半導体回路部
は、伝播する信号に高精度の遅延時間を与えるための半
導体集積回路より構成された遅延回路を有し、この遅延
回路の遅延時間が、上記第２半導体回路部の消費電力の
変化により変化するとともに上記第１半導体回路部に供
給される電源電圧の変動により変化する、１つの半導体
集積回路チップを駆動する半導体集積回路駆動用電源回
路において、 上記第１半導体回路部に動作電圧を供給する第１電源回
路と、 上記第２半導体回路部に動作電圧を供給すると共に、上
記第１電源回路の出力電圧を変化させる第２電源回路
と、 を具備し、 上記第２電源回路は、温度に起因する上記第１半導体回
路部の遅延回路の遅延時間の変動をキャンセルするよう
に、上記第２半導体回路部の消費電力の変化に応じて、
上記第１電源回路の出力電圧を制御することを特徴とす
る半導体集積回路駆動用電源回路。1. A semiconductor integrated circuit chip in which a first semiconductor circuit portion and a second semiconductor circuit portion are integrally formed as a semiconductor integrated circuit, and wherein the first semiconductor circuit portion transmits a signal to be propagated. And a delay circuit constituted by a semiconductor integrated circuit for giving a highly accurate delay time to the first semiconductor circuit while the delay time of the delay circuit changes due to a change in power consumption of the second semiconductor circuit unit. A power supply circuit for driving one semiconductor integrated circuit chip, the power supply circuit driving a single semiconductor integrated circuit chip, the power supply circuit supplying an operating voltage to the first semiconductor circuit part; A second power supply circuit that supplies an operating voltage to the second semiconductor circuit portion and changes an output voltage of the first power supply circuit, wherein the second power supply circuit is caused by temperature. Serial to cancel the variation in the delay time of the delay circuit of the first semiconductor circuit section, in response to changes in the power consumption of the second semiconductor circuit section,
A power supply circuit for driving a semiconductor integrated circuit, wherein an output voltage of the first power supply circuit is controlled.
この時定数回路に、上記第２半導体回路部の消費電力が
変化した時点から上記第１半導体回路部の温度が変化す
る迄の時間遅れに対応する上記第１半導体回路部の温度
時定数にほぼ等しい時定数を持たせ、この時定数だけ遅
らせて上記第１電源回路の出力電圧を制御することを特
徴とする請求項１に記載の半導体集積回路駆動用電源回
路。2. The second power supply circuit has a time constant circuit,
In this time constant circuit, the temperature time constant of the first semiconductor circuit unit corresponding to the time delay from the time when the power consumption of the second semiconductor circuit unit changes to the time when the temperature of the first semiconductor circuit unit changes is substantially equal. 2. The power supply circuit for driving a semiconductor integrated circuit according to claim 1, wherein the output voltage of the first power supply circuit is controlled with an equal time constant and delayed by the time constant.
この時定数回路に、上記第２半導体回路部の消費電力が
変化した時点から上記第１半導体回路部の温度が変化す
る迄の時間遅れに対応する上記第１半導体回路部の温度
時定数にほぼ等しい時定数を持たせ、上記第１電源回路
は、上記第２電源回路から電源電圧が供給されたとき
に、上記時定数だけ遅らせてその出力電圧を変化させる
ことを特徴とする請求項１に記載の半導体集積回路駆動
用電源回路。3. The first power supply circuit has a time constant circuit,
In this time constant circuit, the temperature time constant of the first semiconductor circuit unit corresponding to the time delay from the time when the power consumption of the second semiconductor circuit unit changes to the time when the temperature of the first semiconductor circuit unit changes is substantially equal. 2. The power supply circuit according to claim 1, wherein the first power supply circuit changes the output voltage by delaying the time constant when the power supply voltage is supplied from the second power supply circuit. 4. A power supply circuit for driving a semiconductor integrated circuit according to the above.
するセンサを設け、このセンサの出力によって上記第１
電源回路の出力電圧を制御することを特徴とする請求項
１に記載の半導体集積回路駆動用電源回路。4. A sensor for detecting a temperature of the semiconductor integrated circuit chip is provided, and the output of the sensor is used to detect the temperature of the first integrated circuit chip.
2. The power supply circuit for driving a semiconductor integrated circuit according to claim 1, wherein an output voltage of the power supply circuit is controlled.
変換器を介して上記第２半導体回路部に電源電圧を供給
するための出力端子に接続されているトランジスタを含
むトランジスタ回路と、 上記第２電源回路の出力端子から出力される電源電圧と
基準電圧との差値を増幅し、その増幅した出力電圧を上
記トランジスタのベースに与えて、上記第２電源回路の
出力端子からの電源電圧が上記基準電圧にほぼ等しくな
るように制御する差動増幅回路と、 を含み、 上記電流／電圧変換器で変換された電圧を上記第１電源
回路に供給して上記第１電源回路の出力電圧を制御する
ことを特徴とする請求項１に記載の半導体集積回路駆動
用電源回路。5. The second power supply circuit, wherein a collector is connected to a DC power supply, and an emitter is connected to an output terminal for supplying a power supply voltage to the second semiconductor circuit unit via a current / voltage converter. Amplifying a difference value between a power supply voltage output from an output terminal of the second power supply circuit and a reference voltage, and providing the amplified output voltage to a base of the transistor; And a differential amplifier circuit for controlling a power supply voltage from an output terminal of the power supply circuit to be substantially equal to the reference voltage, and supplying the voltage converted by the current / voltage converter to the first power supply circuit. 2. The power supply circuit for driving a semiconductor integrated circuit according to claim 1, wherein the output voltage of the first power supply circuit is controlled by the first power supply circuit.
換器の上記第１電源回路に対する出力側に、上記第１半
導体回路部の温度時定数にほぼ等しい時定数を有するロ
ーパスフィルタをさらに含んでいることを特徴とする請
求項５に記載の半導体集積回路駆動用電源回路。6. The second power supply circuit further includes a low-pass filter having a time constant substantially equal to a temperature time constant of the first semiconductor circuit unit on an output side of the current / voltage converter with respect to the first power supply circuit. 6. The power supply circuit for driving a semiconductor integrated circuit according to claim 5, wherein the power supply circuit includes:
路部の温度時定数にほぼ等しい時定数を有するローパス
フィルタをさらに含んでいることを特徴とする請求項５
に記載の半導体集積回路駆動用電源回路。7. The power supply circuit according to claim 5, wherein the first power supply circuit further includes a low-pass filter having a time constant substantially equal to a temperature time constant of the first semiconductor circuit unit.
3. A power supply circuit for driving a semiconductor integrated circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8219884A JP2868115B2 (en) | 1995-08-25 | 1996-08-21 | Power supply circuit for driving semiconductor integrated circuits |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21714595 | 1995-08-25 | ||
| JP7-217145 | 1995-08-25 | ||
| JP8219884A JP2868115B2 (en) | 1995-08-25 | 1996-08-21 | Power supply circuit for driving semiconductor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09128068A JPH09128068A (en) | 1997-05-16 |
| JP2868115B2 true JP2868115B2 (en) | 1999-03-10 |
Family
ID=26521844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8219884A Expired - Fee Related JP2868115B2 (en) | 1995-08-25 | 1996-08-21 | Power supply circuit for driving semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2868115B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7085982B2 (en) | 2002-01-18 | 2006-08-01 | Hitachi, Ltd. | Pulse generation circuit and semiconductor tester that uses the pulse generation circuit |
| JP4761833B2 (en) * | 2005-05-24 | 2011-08-31 | 株式会社東芝 | Semiconductor device and system |
-
1996
- 1996-08-21 JP JP8219884A patent/JP2868115B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09128068A (en) | 1997-05-16 |
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