JP3186001B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus used for testing whether a semiconductor integrated circuit (hereinafter referred to as an IC) such as a memory operates normally or not.

[0002]

2. Description of the Related Art The present applicant has proposed an IC test apparatus as shown in FIG. 3 by Japanese Patent Application No. 3-1858: "IC Test Apparatus". This IC test apparatus is an invention for solving the inconvenience that occurs when a plurality of IC devices under test IC1 and IC2 are tested at the same time. That is, in the invention proposed earlier, the driver 11 and the IC elements under test IC1, IC1, IC
Buffers B1 and B2 are provided between the relay contacts K1 and K2.
Or K2 is configured such that no reflection or the like occurs in the signal path even if it is turned off because there is no IC element to be tested.
The present invention proposes a structure of a buffer that can automatically maintain the state by adjusting and once adjusting the characteristics of B1 and B2.

[0003] The schematic configuration and operation will be described below. The output side of the driver 11 is connected to one ends of the first and second level shift resistors 12a and 12b through the level shift transistors 10a and 10b.
The other ends of the level shift resistors 12a and 12b are connected to first and second power terminals 14a and 14b through first and second current sources 13a and 13b, respectively. First current source 13a
For example, the collector of the pnp transistor 15a is connected to the first level shift resistor 12a, the emitter is connected to the first power supply terminal 14a via the resistor 16a, and the base is connected to the first power supply terminal 14a via the resistor 17a. It is connected to and configured. The second current source 13b is similarly configured by the npn transistor 15b and the resistors 16b and 17b. The potential applied to the second power supply terminal 14b is lower than the potential applied to the first power supply terminal 14a. In this example, + V is applied to the first power terminal 14a and the second power terminal 14b
To −V.

[0004] First and second level shift resistors 12a,
The input side of the first and second emitter follower circuits 18a and 18b is connected to each connection point between the first and second current sources 13a and 13b. The output sides of the first and second emitter follower circuits 18a and 18b are connected to each other and to an output terminal 19. That is, the first emitter follower circuit 18
a, the collector of the npn transistor 21a is connected to the first power supply terminal 14a through the protection current limiting circuit 22a.
, The emitter is connected to the output terminal 19 through a resistor 23a, and the base is connected to the first level shift resistor 12a.
a and the connection point of the first current source 13a. In the second emitter follower circuit 18b, the collector of the pnp transistor 21b is connected to the second power supply terminal 14b through the current limiting circuit 22b, the emitter is connected to the output terminal 19 through the resistor 23b, and the base is connected to the second level shift resistor. 12b and the second current source 13b. The current from the first emitter follower circuit 18a is discharged to the cable C1, and the current from the cable C1 is sucked by the second emitter follower circuit 18b. Thus, the first,
The second emitter follower circuits 18a and 18b are connected to each other in a push-pull manner.

A voltage dividing circuit 25 including resistors 24a and 24b is connected between the emitter of the transistor 21a and the emitter of the transistor 21b. The voltage dividing point of the voltage dividing circuit 25 is connected to the non-inverting input terminal of the operational amplifier 27 through the resistor 26. The non-inverting input terminal of the operational amplifier 27 is connected to a resistor 28
To the variable voltage source 29, and the inverting input terminal is grounded through the resistor 31. At the same time, it is connected to the output side of the driver 11 through the resistor 32, and the output terminal is connected to the resistor 33.
a and 33b through the transistors 15a and 15b, respectively.
b respectively. That is, the difference between the output of the voltage dividing circuit 25 and the output of the driver 11 is detected by the operational amplifier 27, and the first and second current sources 13a, 13
3b is subjected to negative feedback control.

The procedure for adjusting the buffers B1 and B2 is performed as follows. First, the output V _{0 of the} driver 11 is set to be 0V. This together with the output V _01, V ₀₂ of the buffer B1, B2 is to be 0V, respectively, to adjust the voltage of the variable voltage source 29 in the buffer B1, B2.
The gain of the buffer B1 is determined by the resistors 24a, 24b, 26, 2
The resistance is set by each of the resistances 8, 31, and 32, and similarly, in the buffer B2, the resistance is set by the resistance of the corresponding resistor.

When the output of the driver 11 becomes, for example, a high level VH from this state, the inverting input side of the operational amplifier 27 becomes higher than the non-inverting input side, the output of the operational amplifier 27 decreases, and the current of the first current source 13a increases. And the second current source 1
3b, the base potentials of the transistors 21a and 21b increase, the emitter potentials of the transistors 21a and 21b increase, and the output voltage at the output terminal 19 becomes VH. Similarly, when the output of the driver 11 becomes low level VL, the output of the output terminal 19 also becomes VL.

If the output level of the output terminal 19 of the buffer B1 drops for some reason, the level of the non-inverting input terminal of the operational amplifier 27 also drops, and
7 also decreases, forming the first and second current sources 13a and 13b. The base potentials of the transistors 15a and 15b also decrease, the collector current of the transistor 15a increases, and the base potential of the transistor 21a increases. Further, the collector current of the transistor 15b decreases, and the base potential of the transistor 21b increases. Therefore, output terminal 1
The level drop of 9 is reversed.

The first and second level shift resistors 12
a and 12b, the output level of the driver 11 is raised to make the transistor 21a low, and the output level of the
1b. If the output is deviated from the predetermined value by adjusting once as described above, the output is automatically returned to the predetermined value, and the same output from a plurality of buffers connected to one driver is respectively supplied to the IC device under test. Can be supplied.

[0010]

In the above configuration,
If the first and second current sources 13a and 13b can always operate with a constant gain in response to the output signal of the driver 11, the linearity of the input-output characteristics of the buffers B1 and B2 is maintained. An operational amplifier 27 is provided to linearize and correct the deterioration of input-output characteristics due to the change in the gain of the first and second current sources 13a and 13b. Depends on frequency characteristics, from DC to several k
Hz is the limit. That is, in the related art, a response delay occurs at the time of rising and falling as shown by a dotted line in FIG. Since ICs have recently been trending toward higher speeds, linearization of input-output characteristics is required even at higher frequencies.

An object of the present invention is to provide an IC test apparatus having a buffer capable of linearizing and correcting input-to-output characteristics even in a high frequency region which cannot be compensated by the operational amplifier 27.

[0012]

According to the present invention, a positive feedback circuit is provided for the active elements 15a and 15b constituting the first and second current sources 13a and 13b constituting the buffers B1 and B2. Thus, the input-output characteristics at a high frequency are corrected for deterioration.

[0013]

FIG. 1 shows an embodiment of the present invention. Parts corresponding to those in the drawings are denoted by the same reference numerals. In the present invention, the first
It is characterized in that the transistors 15a and 15b constituting the current source 13a and the second current source 13b are provided with positive feedback circuits 41 and 42. Positive feedback circuits 41 and 42 are PNP transistors 15a constituting first current source 13a.
Now, for example, the emitter and the level shift transistor 10
It can be configured by connecting a resistor between the light emitting device and the emitter a. Further, the NPN transistor 15b constituting the second current source 13b can be constructed by connecting a resistor between the emitter of the level shift transistor 10b and the emitter of the NPN transistor 15b.

The positive feedback circuits 41 and 42 are connected to the driver 11
Is zero, a voltage difference is generated between the emitters and collectors of the transistors 15a and 15b, so that current flows through the resistors constituting the positive feedback circuits 41 and 42. This current also flows through resistors 16a and 16b connected to the emitters of transistors 15a and 15b. That is, resistor 1
The currents flowing through 6a and 16b are transistors 15a and 1
5b and the sum of the current flowing through the positive feedback circuits 41 and 42. By connecting the positive feedback circuits 41 and 42, the respective emitter potentials of the transistors 15a and 15b are biased toward the base potential, respectively.
The current flowing through 5a and 15b is set to a reduced state.

If, for example, the output voltage of the driver 11 is shifted to the positive side, the voltage between the emitter and the collector of the transistor 15a becomes small,
The emitter-collector voltage of b changes in the increasing direction. On the side of the transistor 15a, the voltage applied to the resistors constituting the positive feedback circuit 41 becomes smaller, so that the positive feedback circuit 41
The current flowing through is reduced. As a result, the current flowing through the resistor 16a also decreases, so that the voltage drop generated in the resistor 16a decreases, and the potential of the emitter of the transistor 15a increases in the positive direction. Due to the rise of the emitter potential, the base-emitter voltage of the transistor 15a shifts in the forward direction, and the current flowing through the transistor 15a increases. Due to the increase of the current, the current of the first emitter follower circuit 18a is also corrected in the increasing direction, and the reduction of the output level of the input-output characteristic is corrected.

At this time, when the output voltage of the driver 11 shifts in the positive direction on the transistor 15b side, the voltage between the collector and the emitter of the transistor 15b increases. As a result, the current flowing through the resistor constituting the positive feedback circuit 42 increases, and the voltage drop of the resistor 16b increases. Therefore, the emitter potential of the transistor 15b is controlled to increase, and the current flowing through the transistor 15b is reduced. As the current flowing through the transistor 15b decreases, the current of the second emitter follower circuit 18b decreases, which acts to increase the potential of the output terminal 19.

On the other hand, if the output voltage of the driver 11 changes in the negative direction, the collector-emitter voltage of the transistor 15a increases, and the current flowing through the positive feedback circuit 41 increases. This increase in current increases the voltage drop across resistor 16a and lowers the emitter potential of transistor 15a. This decrease in emitter potential is caused by the transistor 1
It acts in the direction of decreasing the current of 5a.

On the other hand, when the output voltage of the driver 11 changes in the negative direction on the transistor 15b side,
The voltage applied to the positive feedback circuit 42 decreases, and the positive feedback circuit 4
2 reduce the current flowing through it. This decrease in current reduces the voltage drop across resistor 16b, lowering the emitter potential of transistor 15b. Due to the decrease in the emitter potential, the bias of the transistor 15b is shifted in the forward direction, and acts in a direction to increase the current flowing through the transistor 15b. As a result, the current of the second emitter follower circuit 18b increases, and the current is shifted in a direction to lower the potential of the output terminal 19.

As described above, the decrease in the output amplitude is corrected by the positive feedback action. Therefore, as shown by the dotted line A in FIG. There is a delay in the waveform,
According to the present invention, there is no delay in rising and falling as shown by the solid line B.

[0020]

As described above, according to the present invention, the positive feedback circuit 4 which can be constituted by a resistor is provided.
By providing only 1 and 42, it is possible to output a drive signal with no response delay even for a high-speed signal. Therefore, a drive signal having a correct waveform can be given to the IC devices IC1 and IC2 under test, so that the reliability of the test can be improved. Also, the transistor 15
a, 15b, the transistor 15
a, 15b, or the transistor 2 forming the first and second emitter follower circuits 18a, 18b.
1a and 21b, each buffer B
1 and B2 can be made uniform. Therefore, the waveform of the output signal of any buffer is made uniform, and
The C elements IC1 and IC2 can be tested under the same conditions.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the effect of the present invention.

FIG. 3 is a connection diagram for explaining a conventional technique.

[Explanation of symbols]

 11 Driver 12a, 12b First and second level shift resistors 13a, 13b First and second current sources 14a, 14b First and second power supply terminals 18a, 18b First and second emitter follower circuits 19 Output terminals 25 Voltage divider 27 Operational amplifier 41, 42 Positive feedback circuit

Claims (1)

(57) [Claims] 1. A first and second level shift resistor to which an output of a driver is applied to one end, and a first level shift resistor inserted between the other end of the first level shift resistor and a first power supply terminal. A first current source, a second current source inserted between the other end of the second level shift resistor and a second power supply terminal to which a potential lower than the potential of the first power supply terminal is applied; 1,
First and second emitter follower circuits connected to respective connection points of the second level shift resistor and the first and second current sources, connected to each other in a push-pull manner, and connected to an output terminal. A resistor divider connected between the emitters of the transistors of the first and second emitter follower circuits; and a difference between the divided output of the resistor divider and the output of the driver. (2) An IC that supplies a test signal to a plurality of buffer amplifiers constituted by an operational amplifier that feeds back to a current source via a common driver, and supplies the output of each buffer amplifier to an IC under test individually to perform a test. An IC test apparatus, wherein a positive feedback circuit is provided in an active element constituting the first and second current sources.