JP2867515B2 - Liquid crystal device and driving method thereof - Google Patents

Description

The present invention relates to a method for driving a liquid crystal display device.

[Conventional technology]

Conventionally, when a simple matrix type liquid crystal display device is driven, a driving method generally called a voltage averaging method is employed. However, an actual liquid crystal panel is made of a scanning / signal electrode having a non-zero resistance, and the liquid crystal layer functions as a dielectric. For this reason, when driving by the above-mentioned conventional voltage averaging method, the effective voltage applied to the display dot formed by the intersection of the scanning electrode and the signal electrode changes variously depending on the character or graphic pattern displayed by the liquid crystal panel. As a result, the display becomes uneven.

This problem has been known in the prior art, and as a countermeasure, for example, a method of inverting the polarity of the voltage applied to the liquid crystal panel a plurality of times during one frame (hereinafter, referred to as a line inversion driving method) is disclosed in Japanese Patent Application Laid-Open Publication No. Sho. Nos. 62-31825, 60-19195, and 60-19196.

Further, there is a method of improving display unevenness according to Japanese Patent Application No. 63-159914 previously proposed by the authors.

[Problems to be solved by the invention]

However, the above-described line inversion driving method has only a certain effect in improving the display unevenness caused by the change in the optical characteristics of the liquid crystal sandwiched by the liquid crystal panel due to the frequency component of the applied voltage. Was not completely removed.

The display unevenness could be considerably improved by the improvement method (hereinafter referred to as a voltage correction method) proposed by the present inventors in Japanese Patent Application No. 63-159914, but the display unevenness as shown below was improved. It turns out that it remains.

Here, with reference to FIG. 14, description will be given of display unevenness that remains after the voltage correction method is performed. FIG. 14 shows the liquid crystal panel 1 and display contents. In the liquid crystal panel 1, a pair of substrates 2 and 3 sandwich a liquid crystal (not shown), a plurality of scanning electrodes Y1 to Y6 are formed on the substrate 2, and a plurality of signal electrodes X1 to X6 are formed on the substrate 3 vertically. X6 is formed. Then, the scanning electrodes Y1 to
The display dots are where the Y6 and the signal electrodes X1 to X6 cross each other. Here, in this liquid crystal panel 1, 6 × 6
The display dots are for convenience of explanation, and are usually much more. In the figure, the display dots with hatching indicate that they are lit. (Hereinafter, the lit display dots are referred to as lit dots, and the non-lit display dots are referred to as non-lit dots.) This figure shows a checkered display content. On the left side of the scanning electrode, a scanning voltage waveform that changes according to a display pattern based on a voltage correction method for every other display in the method for improving display unevenness according to Japanese Patent Application No. 63-159914 proposed by the writer is applied. ing. That is, when the selection shifts from one scan electrode to the next scan electrode, the non-selection voltage is corrected according to the difference I between the number of lit dots on a certain scan electrode and the number of lit dots on the next selected scan electrode. The voltage is superimposed. However, in the case of the display content shown in this figure, since the difference I is always 0, no correction voltage is applied to the non-selection voltage. Then, signal voltage waveforms are alternately applied to the signal electrodes from the upper and lower sides alternately. Here, the liquid crystal panel 1 performs a so-called positive display that becomes black when the effective voltage applied to the display dots increases.

When the display pattern shown in FIG.
The display dots created by 1, X3, and X5 are thinner as the display dots are at the top and blacker at the bottom. Conversely, signal electrodes X2, X4, X6
The display dots created by are thinner at lower display dots and darker at higher positions. In other words, the closer the display dot is to the side where the signal voltage waveform is applied, the smaller the effective voltage actually applied.

As a result of further investigation and research on the irregularity of the display, the following was discovered.

 This will be described with reference to FIGS. 15 (a) to 15 (c).

FIGS. 15 (a) to 15 (c) show respective voltage waveforms of the liquid crystal panel 1 of FIG. Fig. 15- (a) shows the dots displayed in Fig. 14.
The voltage waveform on the signal electrode X3 at the position of D31 is shown by a solid line. Then, the voltage waveform on the signal electrode X2 at the position of the display dot D21 is indicated by a dotted line. Here, the waveform of the solid line and the waveform of the dotted line are slightly shifted from each other, but this is to make it easier to see, and actually coincides. Fig. 15-(b)
Is the signal electrode at the position of the display dots D21 to D31 in FIG.
3 shows a voltage waveform on X1. FIG. 15- (c) shows the difference between the voltage waveform on the scanning electrode Y1 and the voltage waveform on the signal electrode X3 at the position of the display dot D31 in FIG. That is, the voltage waveform applied to the display dot D31 is shown by a solid line. And, similarly,
The waveform shown by the dotted line in FIG. 15- (c) shows the voltage waveform applied to the display dot D21. The hatched portion indicates the difference in voltage applied between the lit dot and the non-lit dot, and is not a voltage difference that causes display unevenness. Here, in the figure, V0, V1, V2, V3, V4, and V5 indicate voltages. Then, the voltages V5, V3, V0, and V4 are used as the first set of lighting, non-lighting, selection, and non-selection voltages, and the voltages V0, V2, V5, and V1 are used as the second set of lighting, non-lighting, selection, and non-selection voltages. As selection voltages, selection and non-selection voltages are applied to the scanning electrodes, and lighting and non-lighting voltages are applied to the signal electrodes. (Hereinafter, the voltage waveform applied to the scanning electrode is referred to as a scanning voltage waveform, and the waveform applied to the signal electrode is referred to as a signal voltage waveform.) The first and second voltage sets are switched periodically. In this example, the switching is performed after the selection voltage is applied to all the scan electrodes Y1 to Y6. (This cycle is called one frame, and is shown in the figure as F1 and F2.) Here, as shown in FIG. 15- (a), the dot D31 and the signal are placed on the signal electrode X3 at the position of the dot D31. Since the distance between the ends to which the voltage waveform is applied is short, the voltage waveform has almost no attenuation, and the almost applied signal voltage waveform is applied as it is. However, as shown in FIG. 15- (b), the distance between the dot D21 and the end to which the signal voltage waveform was applied was long on the signal electrode X2 at the position of the dot D21, so that the voltage waveform was greatly attenuated or dull. Signal voltage waveform is applied. In other words, the voltage waveform is attenuated or largely rounded due to the integration circuit formed by the electric resistance of the signal electrodes X1 to X6 and the capacitor using liquid crystal as a dielectric. Therefore, the signal electrodes X1, X3,
When X5 switches from the lighting (non-lighting) voltage to the non-lighting (lighting voltage) voltage, the signal electrodes X2, X4, and X6 light (non-lighting)
When switching from voltage to non-lighting (lighting voltage) voltage,
Large spike-like noise is generated on the scan electrode Y1. As a result, the spike noise generated on the scan electrode Y1 due to the switching of the signal electrodes X1, X3, X5 from the lighting (non-lighting) voltage to the non-lighting (lighting voltage) voltage becomes dominant. Therefore, the effective voltage applied to the display dot D31 becomes small as shown by the solid line waveform in FIG. 15- (c). Then, as indicated by the dotted waveform,
The effective voltage applied to D21 increases.

At this time, on the contrary, the noise generated on the scanning electrode Y6 in FIG. 14 is dominated by the noise generated by the signal electrodes X2, X4, X6, the effective voltage applied to the display dot D26 becomes small, and the effective voltage applied to the display dot D36 becomes small. The voltage increases.

Here, a general description will be given. First, the n-th scanning electrode from the top is the scanning electrode Yn, the m-th signal electrode from the left is the signal electrode Xm, and the display dot formed by the intersection of the signal electrode Xm and the scanning electrode Yn is the display dot Dmn. (Hereinafter, this will be referred to unless otherwise noted.) Then, each signal electrode of the signal electrodes to which the signal voltage waveform is applied from one end (the upper side in FIG. 14) and the scanning electrode Yn are formed. The number of both display dots and display dots created by the scanning electrode Yn + 1 is a lighting dot a1, and the number of both display non-lighting dots is b.
1, the number of display dots made with the scanning electrode Yn is a lighting dot, and the number of display dots made with the scanning electrode Yn + 1 is a non-lighting dot is c.
1.The number of display dots made with the scanning electrode Yn is a non-lighting dot, and the number of display dots made with the scanning electrode Yn + 1 is a lighting dot is d1.
The display dot formed by each of the signal electrodes to which the signal voltage waveform is applied from the other end (the lower side in FIG. 14) and the scan electrode Yn, and the display dot formed by the scan electrode Yn + 1 are both lit. The number of dots is a2, the number of both non-lighting dots is 62, the number of display dots made with the scanning electrode Yn and the scanning electrode Yn + 1 is the number of non-lighting dots c2 and the number of scanning electrodes Yn and the scanning electrode Yn The number of display dots to be formed is non-lighting dots and the number of display dots to be formed to be the lighting dots with the scanning electrode Yn + 1 is d2.

Further, among the display dots formed by each signal electrode of the signal electrodes to which the signal voltage waveform is applied from one end (the upper side in FIG. 14) and the scanning electrode Yn, the number of lit dots is N1 _ON and the number of non-lit dots is N1 _ON .
N1 _OFF , of the display dots created with the scanning electrode Yn + 1, the number of lit dots is set to M1 _ON , and the number of non-lit dots is set to M1 _OFF .
Of the display dots formed by the signal electrodes to which the signal voltage waveform is applied from the other end (the lower side in FIG. 14) and the scanning electrode Yn, the number of lit dots is N2 _ON and the number of non-lit dots is N
2 _OFF , of the display dots formed with the scanning electrode Yn + 1, the number of lit dots is M2 _ON and the number of non-lit dots is M2 _OFF .

Then, N1 _ON = a1 + c1 N1 _OFF = b1 + d1 M1 _ON = a1 + d1 M1 _OFF = b1 + c1.

Here, the numerical value I1 and _{I1 = c1-d1 = N1 ON} -M1 ON.

Similarly, N2 _ON = a2 + c2 N2 _OFF = b2 + d2 M2 _ON = a2 + d2 M2 _OFF = b2 + c2

Here, the numerical value I2 is set as I2 = c2−d2 = N2 _ON− M2 _ON .

Further, a function I (k) is defined as I (k) = f (k) * I1 + f (Lk) * I2.

Here, f (k) is a function whose value decreases as k increases. This function f (k) means that the magnitude of the spike-like noise generated by each signal electrode on the scanning electrode is closer to the end where the signal voltage waveform is applied (hereinafter simply referred to as the driving end). It means that the larger the electrode, the larger.

L is the total number of scanning electrodes. k is 1 ≦ k ≦ L
It is.

Then, to conclude, in conclusion, the scanning electrode Yn
When the selection shifts to +1 on the k-th scan electrode Yk,
A spike-like noise having a magnitude corresponding to the absolute value of the value of the function I (k) is generated. That is, when the value of the function I (k) increases, large noise occurs. The direction in which the noise is generated depends on whether the value of the function I (k) is positive or negative.

That is, when the direction of the voltage of the spike-like noise corresponding to the value of the function I (k) and the change of the voltage waveform applied to each signal electrode are the same in the scanning electrode Yk, this signal electrode and the scanning The effective voltage applied to the display dots created by the electrodes Yk becomes smaller and the display becomes thinner.
Darkens. As described above, display unevenness remains due to the mechanism described above.

In addition, FIGS. 16 and 17 illustrate different display unevenness that remains after the voltage correction method is performed. 16 and 17 show display contents different from those of the liquid crystal panel 1, respectively.
In the figure, the liquid crystal panel 1 has exactly the same structure as the liquid crystal panel 1 of FIG. Therefore, the same numbers are assigned and the description is omitted.
In FIGS. 16 and 17, on the left side of the scan electrodes Y1 to Y6, a voltage correction method for display unevenness due to weft threading is one of the display unevenness improvement methods according to the patent application (Showa 63-159914) filed by the present inventors. , A scanning voltage waveform that changes according to the display pattern is applied. That is, the correction voltage is superimposed on the selection voltage in accordance with the number Z of lighting dots on the selected scanning electrode. Here, the display contents of FIG. 16 and FIG. 17 indicate that the congruent rectangle is displayed at a position shifted to the left end and the right end, respectively. Therefore, when the display shown in FIGS. 16 and 17 is performed, exactly the same correction voltage is applied to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 1 shown in FIGS. 16 and 17.

However, in the case of FIG. 16, the correction voltage is too large, and display unevenness occurs in the horizontal direction of the displayed square. Conversely, in the case of FIG. 17, the correction voltage is small, and display unevenness due to weft threading remains. That is, display unevenness that becomes thinner in the horizontal direction of the displayed square remains generated.
This means that the resistance of each of the scanning electrodes Y1 to Y6 constituting the liquid crystal panel 1 and the capacitor for forming the display dot constitute an integration circuit. by. That is, the effect of blunting the waveform of the lighting dot located far from the end to which the scanning voltage waveform is applied (hereinafter, simply referred to as the driving end) is greater than the effect of the lighting dot located near. For this reason, if there is a lit dot in a distant place, a large rounding occurs. As a result, if there is a lighting dot at a position far from the drive ends of the scan electrodes Y1 to Y6, the scan voltage waveform including the correction voltage becomes blunt. This is because the effective voltage applied to the display dots becomes smaller.

Here, generally speaking, s scan electrodes Y1 to Ys
Of the selected scanning electrodes, the scanning electrodes and the signal electrodes Xi (i = 1, 2) of p signal electrodes X1 to Xp are selected.
..., the position of the display dot created by p) is i, The unevenness of the display due to the weft threading occurs to the extent corresponding to the numerical value Z 'calculated by the following equation.

Here, the function q (i) is an increasing function that increases as the variable i increases.

The function δ (i) is 1 when the display dot at the position i on the selected scanning electrode is turned on, and becomes 0 when the display dot is not turned on.

Therefore, the numerical value Z 'is obtained by giving a larger weight to the lighting dots far from the supply end of the scanning electrode to obtain the number of lighting dots.

Therefore, In the conventional voltage correction method for the uneven display due to the weft threading using the numerical value Z obtained in the above, the uneven display cannot be completely eliminated.

As described above, display unevenness also occurs due to the mechanism described above. Therefore, the display quality has been reduced.

Accordingly, the present invention provides a method disclosed in Japanese Patent Application No.
In the method of improving the display unevenness according to No. 14, that is, the method of extracting the regularity of the display contents into a fixed amount drop and performing a correction corresponding to this extraction amount, when calculating the extraction amount, the display position of the display pattern By taking into account the positional relationship between the scanning electrode and the driving end of the scanning electrode or signal electrode, display unevenness is further improved, the display quality is enhanced, and an easy-to-view liquid crystal display device is provided.

[Means for solving the problem]

The liquid crystal device of the present invention includes a pair of substrates sandwiching a liquid crystal layer, in which a scan electrode group is formed on one substrate and a signal electrode group is formed on the other substrate, and a scan voltage waveform is applied to the scan electrode group. Means for applying, a means for applying a signal voltage waveform to the signal electrode group, and a correction voltage for compensating for a shift in the effective voltage applied to the liquid crystal layer which occurs when the voltage level of the signal voltage waveform changes. Means for superimposing the correction voltage on the scanning voltage waveform, wherein the correction voltage is varied according to a distance from an end of the signal electrode to which the voltage waveform is applied to the selected scanning electrode. It is characterized by having.

Further, the method of driving a liquid crystal device according to the present invention is configured such that a scanning electrode group is formed on one of a pair of substrates sandwiching a liquid crystal layer, and a signal electrode group is formed on the other substrate. A correction voltage for applying a scanning voltage waveform to the liquid crystal layer, applying a signal voltage waveform to the signal electrode group, and compensating for a shift in the effective voltage applied to the liquid crystal layer that occurs when the voltage level of the signal voltage waveform changes. And applying the correction voltage to the scanning electrode selected from an end on the side where the voltage waveform is applied to the signal electrode. And applying the applied voltage to the liquid crystal layer.

[Action]

With the above configuration, it is possible to supply a correction voltage in consideration of the positional relationship between the display position of the character or graphic pattern displayed on the liquid crystal panel and the drive end of the electrode.

Further, the amount of the correction voltage can be changed and supplied for each electrode.

〔Example〕

Example 1 Hereinafter, an example will be specifically described. First, a description will be given of an embodiment for display unevenness that occurs when a checkered pattern is displayed.

As described above, the degree of display unevenness is obtained by adding the difference between the number of lit dots on the selected scanning electrode and the number of lit dots on the next selected scanning electrode in consideration of the position from the driving end of the signal electrode. It is determined by the combination. Therefore, the sum may be calculated while operating the liquid crystal display device, and the waveform may be corrected according to the result. An embodiment of a specific liquid crystal display device for performing such correction will be described.

FIG. 1 shows the configuration of this embodiment. In the figure, reference numeral 101 denotes a liquid crystal unit, which comprises a liquid crystal panel 201, a scanning electrode driving circuit 205, and a signal electrode driving circuit 213. Reference numeral 102 denotes a series of control signals for controlling the operation of the liquid crystal display device, which includes a latch signal LP, a frame signal FR, a data-in signal DIN, an X driver shift clock signal SCL, and others. 103 is a data signal,
This signal determines the display pattern. The data signal 103 changes at the rise of the signal XSCL, and is taken into the liquid crystal unit 101 and the voltage waveform correction circuit 104 at the fall. 104 is a voltage waveform correction circuit (hereinafter abbreviated as a correction circuit), 105
Denotes a power supply circuit, and 108 denotes a circuit for generating a clock signal 110 synchronized with the signal LP (hereinafter, abbreviated as a frequency dividing circuit). Reference numeral 106 denotes a power supply (hereinafter, referred to as a Y power supply) for two sets of scan electrodes required to drive the scan electrodes output from the power supply circuit 105. Reference numeral 107 denotes a power supply (hereinafter, referred to as an X power supply) for two sets of signal electrodes required to drive the signal electrodes output from the power supply circuit 105. 109 is a correction circuit 104
Is a correction signal for determining the amount of the correction voltage to be output. Reference numeral 110 denotes a signal synchronized with the signal LP output from the frequency dividing circuit 108 (hereinafter, referred to as a correction clock).

Here, an example of a specific configuration of each component in FIG. 1 is shown. FIG. 2 shows an example of a specific configuration of the liquid crystal unit 101. In the figure, reference numeral 201 denotes a liquid crystal panel on which scanning electrodes Y1 to Y6 arranged on one substrate 202 of a pair of substrates 202 and 203 sandwiching a liquid crystal layer are formed, and signals arranged vertically on the other substrate 203. Electrodes X1 to X6 are formed. Here, the signal electrodes X1,
X3 and X5 have terminals for supplying signal voltage waveforms on the upper side.
2, X4 and X6 have terminals on the lower side. And the scanning electrodes Y1 to Y6
And the signal electrodes X1 to X6 intersect to form display dots 204. Although the liquid crystal panel 201 has a 6 × 6 dot configuration, this is for the sake of simplicity of description, and the present invention is not limited to this. 205 is a scan electrode drive circuit (hereinafter, referred to as
It is called Y driver. ), A shift register circuit 206, a shift register circuit 207, a latch circuit 208, a counter circuit 209, a coincidence detection circuit 210, a switch circuit 211, and a level shifter circuit in which a register composed of a plurality of bits simultaneously shifts.
It consists of 212. Then, the level shifter circuit 212
Are guided to the respective scanning electrodes Y1 to Y6 of the liquid crystal panel 201. Here, FIG. 3 shows a more detailed specific example of the Y driver 205, and the Y driver 205 will be described in detail.
In the figure, reference numeral 206 denotes a shift register circuit which takes in the signal DIN at the fall of the signal LP and sequentially transfers the signal DIN to each register of the shift register circuit 206 at the fall of the signal LP. Here, the signal DIN sets the high potential “H” to active “1”, and usually, the signal LP includes the number of the scan electrodes Y1 to Y6 or more.
Is output once at intervals of Therefore, the shift register
“1” data passes through 206, otherwise inactive “0”
Becomes Here, each register outputs the contents of the register as a control signal CO.

Reference numeral 207 denotes a shift register circuit composed of a register having a plurality of bits. In this embodiment, one register is composed of 5 bits. The shift register operates by a Y correction shift clock (hereinafter, referred to as a signal YCSCL) constituting the correction signal 109, and an intensity signal (4 in this embodiment) for determining the amount of the correction voltage constituting the correction signal 109.
(Bits I0 to I3) and a sign signal F for determining the polarity of the correction voltage are sequentially taken in as a signal YCSCL.

A latch circuit 208 captures the contents of the shift register circuit 207 by a signal LP.

Reference numeral 209 denotes a counter circuit, which is an up counter having the same number of bits as the number of bits of the intensity signals I0 to I3. The counter 209 counts up by the correction clock 110 and is reset to 0 by the signal LP.

210 is a coincidence detection circuit, and each circuit 210 compares each corresponding register of the latch circuit 208 with the output of the counter circuit 209 to detect whether or not they match. That is, when they match,
The control signal C2 which becomes active "1" is output. At this time, the contents of the code signal F taken into the register (this is the control signal
C1), the sign signal F indicates a negative value (the sign signal F is active "1"), and the contents of the shift register are negative numbers represented by two's complements. Is inverted to indicate whether each bit is equal to a value obtained by adding 1 to the numerical value represented by inverting each bit. The detection result is held until the next signal LP comes.

211 is a switch circuit. Among the ten voltages V0, V1U, V1, V1L, V2, V3, V4U, V4, V4L, and V5 constituting the Y power supply 106, the voltages V0, V4U, V4, and V4L are a first voltage set, and the voltage V5 ,
A switch circuit that divides V1L, V1, and V1U into a second set of voltages and switches to one of these two sets of voltages by a signal FR.

Here, the voltages V0, V4U, V4, and V4L are referred to as a selection voltage, a correction voltage (U), a non-selection voltage, and a correction voltage (L) of a first voltage set, respectively. The correction voltages (U) and (L) are collectively referred to simply as a correction voltage. Similarly, the voltage V
5, V1L, V1, and V1U are referred to as a selection voltage, a correction voltage (U), a non-selection voltage, and a correction voltage (L) of the second voltage set.

A level shifter circuit 212 includes a plurality of four-circuit one-contact switches.

When the control signal C0 is "1", each switch selects S1. That is, the selection voltage is selected.

When the control signal C0 is "0" and the control signal C2 is "1", each switch selects S3. That is, the non-selection voltage is selected.

When the control signals C0 and C2 are both "0" and the control signal C1 is "0", each switch selects S2, and when C1 is "1", each switch selects S4.

The configuration of the Y driver 205 is as described above. Note that the shift register circuit 207 has a 5-bit configuration for the intensity signals I0 to I3 and the sign signal F. However, by increasing or decreasing the number of bits of the intensity signal,
The number of bits of 207 may be increased or decreased as appropriate.

It should be noted that the number of registers constituting the shift registers 206 and 207, the number of latch circuits 208, the number of coincidence detecting circuits, and the number of switches constituting the level shifter circuit are as shown in FIG. ~ Y6.

Here, the operation of the Y driver 205 will be described. In FIG. 3, the signal DIN is taken into the shift register 206 in synchronization with the signal LP and transferred. As a result, the level shifter circuit 212 sequentially outputs the selection voltage in response thereto. (Hereinafter, a switch that outputs a selected voltage is called a selected switch, and a switch that outputs another voltage is called a non-selected switch.) In synchronization with this, a signal LP is output.
During one cycle of the intensity signal I0 to I3 and the sign signal F
The data is taken into the shift register circuit 207 by SCL.
The correction voltages (U) to (L) are not selected until the absolute value of the numerical value represented by the intensity signals I0 to I3 matches the numerical value of the counter 209 counting up by the correction clock. Each switch outputs. Here, which of the correction voltages (U) and (L) is output depends on whether
Depends on the control signal C1. In other words, it depends on whether the code signal F is from “0” to “1”. When the value matches the value of the counter circuit 209, each switch that is not selected outputs a non-selection voltage. Therefore, the switches that are not selected output the correction voltage for a longer time as the absolute value of the numerical value represented by the intensity signals I0 to I3 increases. The configuration and operation of the Y driver are as described above.

Here, it returns to FIG. In the figure, reference numeral 213 denotes a signal electrode driving circuit (hereinafter, referred to as an X driver), which includes a shift register circuit 214, a latch circuit 215, and a level shifter circuit 216. Then, the output of the level shifter circuit 216 is guided to the signal electrodes X1 to X6 of the liquid crystal panel 201.

The shift register circuit 214 determines a display pattern,
The data signal 103 indicating whether to light or not is fetched using the signal XSCL as a clock. (Here, lighting is set to active “1” and non-lighting is set to inactive “0”.) Then, after taking in all data signals 103 corresponding to the signal electrodes X1 to X6, the latch circuit 215 is activated by the signal LP. It is taken in. Then, the level shifter circuit outputs a predetermined voltage according to the content of the latch circuit 215 and the signal FR. That is, 4 which constitutes the X power supply 107
Of the voltages V0, V2, V3, and V5, the voltages V5 and V3 are divided into a first set of voltages, and the voltages V0 and V2 are divided into a second set of voltages. Take one or the other. (Here, the first set of voltages V5 and V3 are referred to as a first set of lighting voltage and non-lighting voltage, respectively, and the second set of voltages V0 and V2 are respectively referred to as a second set of lighting voltage and non-lighting. It is called voltage.)
If the content of the latch circuit 215 is “1”, one of the lighting voltages determined by the signal FR is output, and if “0”, the non-lighting voltage is output.

The liquid crystal unit 101 has the above configuration.
Therefore, the liquid crystal unit 101 synchronizes with the signals DIN and LP,
A selection voltage is sequentially applied to the scan electrodes Y1 to Y6, and in synchronization with this, a lighting or non-lighting voltage according to the display pattern is applied to the signal electrodes X1 to X6, and the liquid crystal panel 201 displays. At this time, the scan electrodes Y1 to Y6 to which no selection voltage is applied
, A correction voltage having a length and polarity corresponding to the intensity signals I0 to I3 of the correction signal 109 and the code signal F is applied instead of the non-selection voltage.

 The liquid crystal unit 101 performs the above configuration and operation.

Next, in FIG. 1, reference numeral 104 denotes a correction circuit, which is a scanning electrode Yn of the liquid crystal panel 201 of FIG.
1, 2,... 5, 6 However, when n = 6, it becomes 1 instead of n + 1. ) Is a circuit which counts the number of the above-mentioned lighting dots 204 in consideration of the distance from the end to which the drive waveform of the signal electrodes x1 to x6 is applied, and generates the intensity signals I0 to I3 and the sign signal F from the difference. FIG. 4 shows a specific configuration example, which will be described in detail. In FIG. 4, reference numeral 401 denotes a toggle flip-flop circuit (hereinafter referred to as TF / F);
3, 404 are counter circuits, 405U and L are multiplier generation circuits, 406U
And L are counter circuits, 407U and L are latch circuits, 408U and L
Is an operation circuit for performing subtraction, 409U and L are storage elements, 410U and L are latch circuits, 411U and L are operation circuits for performing multiplication, 41
An operation circuit 2 performs addition and division.

Here, the TF / F circuit 401 is reset by the signal LP and outputs “0”, and functions as an active input to the gate circuit 402L and functions as an inactive input to the gate 402U. Then, when the clock by the signal XSCL is input, it is inverted. Therefore, when data signals corresponding to the even electrodes X2, X4, X6 of the signal electrodes X1 to X6 of the liquid crystal panel 201 of FIG. 2 enter the gate circuits 402U and L of FIG. 4, only the gate circuit 402L Becomes active and outputs the data signal as it is. Then, the output of gate circuit 402U is inactive regardless of the data signal. Conversely, when the data signals corresponding to the odd-numbered electrodes X1, X3, and X5 in FIG. 2 enter the gate circuits 402U and L in FIG. 4, only the gate circuit 402U becomes active and outputs the data signal as it is. Then, the output of the gate circuit 402L becomes inactive regardless of the data signal. That is, the three circuits separate the data signal for the electrode driven from above and the data signal for the electrode driven from below. The separated data signals are called an upper data signal and a lower data signal, respectively.

The counters 406U and 406L count the number of "1" states indicating lighting for each of the separated data signals.

That is, the counters 406U and L are added only when the output of the gate 402U and L is active when the signal XSCL falls. The addition results (the numerical values are set to N1 _ON and N2 _ON ) are taken into the latch circuits 407U and L, respectively, in synchronization with the signal LP. The arithmetic circuits 408U and L respectively subtract the values of the latch circuits 407U and L just before taking in (these values are M1 _ON and M2 _ON ) and the values of the counters 406U and L N1 _ON and N2 _ON . Here, this calculation result is set as I1 = N1 _ON− M1 _ON , and I2 = N2 _ON− M2 _ON .

Here, the counter 403 is an up counter circuit capable of indicating the number of states of the scan electrodes Y1 to Y6 in FIG. 2, and in this embodiment, counts up from 0 to 5 and is reset to 0 by the signal DIN. The output of the counter 403 in FIG. 4 is a storage element (hereinafter referred to as a memory). Used as addresses of 409U and L. The value of the address is the liquid crystal panel 20 in FIG.
When a selection voltage is applied to one scan electrode Yn, it becomes n-1.

Then, the numerical values I1 and I2 described above are respectively stored in the memory 409U.
And L to the address indicated by the counter 403.

Explaining the operation in detail, the counters 406U and 406L count the number N1 _ON and N2 _ON of the lighting dots on Yn + 1, respectively, while the selection voltage is applied to the scanning electrode Yn in FIG. Then, just before the selection voltage is applied to the scan electrode Yn + 1, the differences I1 and I2 between the numbers M1 _ON and M2 _ON held in the latch circuits 408U and L, that is, the number of lit dots on the scan electrode Yn are calculated. The data is written to addresses n-1 of the memories 409U and L. This operation is repeated from n going from 0 to 6 and back to 0. That is, in the memories 409U and L, the difference I1 and I2 of the number of lighting dots on the scan electrodes Y1 and Y2 is stored at address 0.
Are respectively stored.

Addresses 1 to 5 are scanning electrodes Y2 and Y3, Y3 and Y4, and Y4, respectively.
And the differences I1 and I2 between the numbers of lighting dots on Y5 and Y5 and Y1 are stored.

Here, the counter 404 is an up-counter circuit capable of indicating the number of states of the scan electrodes Y1 to Y6. In this embodiment, the counter 404 counts up from 0 to 5, and is reset to 0 by the signal LP. The clock input to the counter 404 (this clock is referred to as a signal YCSCL) may be any clock that changes by the number of the scan electrodes Y1 to Y6 within one cycle of the signal LP. YCSCL. The output of the counter 404 is used as an address of the multiplier generation circuit 405U and L.

Numerals 405U and L denote multipliers, which are numerical tables composed of read-only storage elements (hereinafter referred to as ROMs), diode matrices, and the like, and generate values of functions using input addresses as variables. Circuit. That is, 405U
Is a function table that returns a numerical value f (K), where k is the address. Function f
(K) is a decreasing function whose value decreases as k increases. The form of the function is obtained, for example, by an experiment or the like. Here, for the sake of simplicity, the function is linearly changed as follows.

When k = 0, f (0) = 15 k = 1, f (1) = 14 k = 2, f (2) = 13 k = 3, f (3) = 12 k = 4, f (4) = 11, k = 5, f (5) = 10 Similarly, the multiplier generation circuit 405L is a circuit that generates a function that can be defined by f (L−k). Here, L is a number obtained by subtracting 1 from the number of the scanning electrodes Y1 to Y6. In this embodiment, L = 5.

During the period when the selection voltage is applied to the scan electrode Yn of the liquid crystal panel 201 in FIG. 2, the arithmetic circuits 411U and L performing the multiplication in FIG. 4 respectively operate at the address (address n-1) indicated by the counter 403. Contents of memory 409U and L and multiplier generation circuit
Multiply 405U by L. At this time, since the counter 404 is counted up by the signal YCSCL, the values output from the multiplier generation circuits 405U and L change in synchronization with the signal YCSCL. In other words, the arithmetic circuit 4 is synchronized with the signal YCSCL.
The calculation results of 11U and L are as follows, respectively.

f (0) * I1, f (5) * I2 f (1) * I1, f (4) * I2 f (2) * I1, f (3) * I2 f (3) * I1, f (2) * I2 f (4) * I1, f (1) * I2 f (5) * I1, f (0) * I2 An arithmetic circuit 41 for adding and dividing the result
Add the two together and divide the result by four. When the numerical value is I, I = {f (0) * I1 + f (5) * I2} / 4 I = {f (1) * I1 + f (4) * I2} / 4 I = {f (2) * I1 + f (3) * I2｝ / 4 I = ｛f (3) * I1 + f (2) * I2｝ / 4 I = ｛f (4) * I1 + f (1) * I2｝ / 4 I = ｛f (5) * I1 + f (0) * I2｝ / 4 are sequentially output in synchronization with the signal YCSCL. When the output numerical value is negative, it is represented by a two's complement. 4
The reason for this is that the shift register circuit 207 in FIG. 3 has a 4-bit configuration except for the sign signal F, so that the numerical value I falls within these 4 bits. Therefore, it is not essential.

Generally speaking, during the period when the scanning electrode Yn of the liquid crystal panel 201 of FIG. 2 is selected, the differences I1 and I2 between the number of lighting dots on the scanning electrode Yn and Yn + 1 are f (n-1),
After multiplying by f (L-n + 1), the result of adding these two results is I = f (n-1) * I1 + F (L-n + 1) *
I2 is sequentially output in synchronization with the signal YCSCL. Assuming that the magnitude of this result is an intensity signal I0 to I3 and that the sign is a sign signal F,
It is output together with the signal YCSCL as the correction signal 109 in FIG. The correction circuit 104 operates as described above. Here, this configuration is not limited to this. For example, in FIG. 4, I = f (n-1) * I1 + F (L-n +
1) * I2 is calculated in real time by the circuits of 405U, L, 411U, L and 412, but it is calculated in advance by a CPU or the like, written in a newly provided memory, and the outputs of the counters 403 and 404 are used as addresses. They may be read out sequentially and output as the correction signal 109.

FIG. 5 shows an example of a specific configuration of the power supply circuit 105 in FIG. In the figure, 501 to 509 are resistors, which are connected in series. Voltages V0 and V5 are applied to both ends. These resistors 501-509 work as a voltage dividing circuit. Here, the voltages generated in the resistors 501 to 509 are V0, V1
If U, V1, V1L, V2, V3, V4U, V4, V4L, V5, V≡V0−V1 = V1−V2 = V3−V4 = V4−V5, V2−V3 = a * V, a is a constant , 1 to 50.

The resistance values of the resistors 501 to 509 are set so that the following four equations are satisfied: V1U−V1 = V4−V4L and V1−V1L = V4U−V4.

Reference numeral 510 denotes a voltage stabilizing circuit that lowers only the impedance without changing each voltage generated by the resistors 501 to 509, and includes a voltage follower circuit using an operational amplifier circuit, an emitter follower circuit using a transistor, and the like. The voltage stabilizing circuit 510 is provided for each voltage divided by the resistors 501 to 509 as shown in the drawing.

With the above configuration, the voltages V0, V1U, V1, V1L, V4
U, V4, V4L, and V5 are set to Y power supply 106, and voltages V0, V2, V3, and V5 are set to X
The light source is supplied to the liquid crystal unit 101 shown in FIG.

In FIG. 1, reference numeral 108 denotes a circuit for generating a correction clock 110, which generates a clock synchronized with the signal LP. As the clock 110, for example, a signal obtained by dividing or multiplying the signal XSCL may be used, or may be constituted by a PLL circuit. At this time, the clock 110 is not always in the same cycle, for example, the signal LP
The period may be gradually increased or decreased in synchronization with. The cycle of this clock is obtained, for example, by experiment. In the present embodiment, one period of the signal LP has 16 periods.

 The liquid crystal display device of FIG. 1 has the above configuration.

Here, the operation of the present embodiment in the case where a checkerboard pattern is actually displayed will be described. FIG. 6 is a view showing display contents displayed by the liquid crystal panel 201 of FIG.

In FIG. 6, hatched display dots represent lighting, and this display example indicates that a checkered pattern is displayed. The embodiment at the time of this display operates as follows.

First, the correction circuit 104 shown in FIG.
Of 01 of the scanning electrodes Y1 to Y6, the number N1 _ON although the drive end and the scanning electrode Yn + 1 is lit inner display dot created by the signal electrodes X1, X3, X5 at the top when Yn is selected The number N2 _ON of the lit ones of the display dots formed by the signal electrodes X2, X4, and X6 below the drive end are separately counted.

Immediately before the scanning electrode Yn + 1 is selected next, the counted value and the latch circuit 4 of the correction circuit 104 shown in FIG.
Signal electrodes X1 to drive end and the scan electrode Yn, which had been held in 07U and L is above, X3, signal electrode drive end to the number M1 _ON but has internal lighting of the display dots X5 and make is below X2, X4,
The respective differences I1 and I2 of the number M2 _ON of the display dots formed by X6 and the display dots made by X6 are obtained as I1 = N1 _ON -M1 _ON , I2 = N2 _ON -M2 _ON , and n- of the memories 409U and L 1
Write to address. This is repeated from n = 1 to 5, 5 to 1. Therefore, the differences I1 and I2 for all the scan electrodes Y1 to Y6 are written in the memories 409U and L. In the case of the display of FIG. 6, the memory 409U sequentially stores addresses from 0 to 5 in the order of −
2, 2, -2, -2, -2 are written and the memory 409L
Are written in the order 2, -2, -2, -2, -2.

In parallel with the writing operation to the memories 409U and L, the values I1 and I2 of the addresses n-1 of the memories 409U and L are given by Δf
The operation of (k-1) * I1 + f (L-k + 1) * I2｝ / 4 is sequentially performed on k = 1, 2,...
The data is transferred to the shift register circuit 207 in the Y driver in FIG.

Here, for example, when n = 3, the above operation is performed with the memory 409U at the address n-1 = 2 and the values -2 and 2 of L being numerical values I1 and L2. Thereby, the scanning electrode Y (n + 1)
Immediately before is selected next, the shift register circuit 207 includes, from the top, I = {f (0) * I1 + f (5) * I2} / 4 = {15 * (-2) + 10 * 2} / 4 ≒ -3 I = ｛f (1) * I1 + f (4) * I2｝ / 4 = ｛14 * (-2) + 11 * 2｝ / 4 ≒ -2 I = ｛f (2) * I1 + f (3) * I2｝ / 4 = {13 * (-2) + 12 * 2} / 4 ≒ -1 I = {f (3) * I1 + f (2) * I2｝ / 4 = {12 * (-2) + 13 * 2} / 4 ≒ 1 I = ｛f (4) * I1 + f (1) * I2｝ / 4 = ｛11 * (-2) + 14 * 2｝ / 4 ≒ 2 I = ｛f (5) * I1 + f (0) * I2｝ / 4 = {10 * (-2) + 15 * 2｝ / 4 ≒ 3 is acquired. Here, each numerical value I is rounded off to the nearest decimal point.

Then, when the signal LP falls and the scan electrode Yn + 1 is selected, these values are taken into the latch circuit 208. At the same time, the counter 209 is reset to zero. Thereafter, the count is incremented by the correction clock 110.

Here, since n = 3, the selected scan electrode Yn + 1 becomes the scan electrode Y4, so that the switches of the level shifter circuit 212 are S4 (correction voltage (L)), S2 (correction voltage (U)), S4 (correction voltage (L)), S1 (selection voltage), S4
(Correction voltage (L)) and S2 (correction voltage (U)) are selected and output to the respective scanning electrodes Y1 to Y6 of the liquid crystal panel 201.

Each of the switches selecting S2 to S4 has the number of correction clocks 110 input to the counter 209 by the number indicated by the corresponding latch circuit 208, and the output of the counter 209 is equal to the number indicated by the corresponding latch circuit 208. This state is maintained until they match. Then, when they match, each switch selects S3 (non-selection voltage) and outputs it. That is, whether the correction voltage (U) or (L) is taken depends on whether the numerical value I is positive or negative, and the longer the absolute value of the numerical value I, the longer the correction voltage is selected instead of the non-selection voltage. .

Thus, the voltage is supplied to the scan electrodes Y1 to Y6 of the liquid crystal panel 201.

At this time, each signal electrode X1 is placed on the selected scanning electrode Yn + 1.
The X driver 213 operates so as to supply a lighting voltage to the signal electrodes X1 to X6 if the display dots formed by .about.X6 are turned on, and a non-lighting voltage if not.

As described above, the liquid crystal display of this embodiment operates. Here, voltage waveforms applied to the scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 of the liquid crystal panel 201 when the display shown in FIG. 6 is performed are shown in FIGS. 7 (a) to 7 (g). The operation will be described in detail. FIG. 7 (a) shows the voltage waveforms of the signal electrodes X3 and X5 at the positions of the display dots D31 and D51 by solid lines in FIG. 6, and the signal electrodes X2 and X4 at the positions of the display dots D21 and D41.
Are shown by broken lines. In FIG. 3B, the voltage waveform applied to the scanning electrode Y1 is shown by a solid line, and the disturbance of the waveform to be generated at the position of the display dot D31 of the scanning electrode Y1 is shown by a broken line. Similarly, FIG. 3C shows the scanning electrode Y2.
FIG. 3 (d) shows the voltage waveform applied to the scan electrode Y3 and the waveform intended to be generated at the position of the display dot D33. (E) shows the voltage waveform applied to the scan electrode Y4, and (b) shows the voltage waveform applied to the position of the display dot D34, and (f) shows the voltage applied to the scan electrode Y5. FIG. 11G shows the waveform and the waveform to be generated at the position of the display dot D35, and FIG. 14G shows the voltage waveform applied to the scan electrode Y6 and the waveform to be generated at the position of the display dot D36. These are indicated by solid lines and broken lines, respectively. 7 (a) to 7 (g), the influence of the change in the voltage waveform indicated by the solid line in FIG. 7 (a) is greatly affected in the order of the upper scanning electrodes Y1, Y2, and Y3. Scanning electrode
It can be seen that waveform disturbances are likely to occur on Y1, Y2, and Y3 according to the magnitude of the influence. Similarly, the scanning electrode located below
It can be seen that, in the order of Y6, Y5, and Y4, the waveforms of the signals are affected by changes in the voltage waveforms of the signal electrodes X2 and X4 to which the signal voltage waveforms are supplied from below, and a corresponding waveform disturbance is about to occur. However, as can be seen from the waveforms shown by solid lines in FIGS. 2B to 2G, the Y driver 205 shown in FIG. A correction voltage (U) or (L) having a direction opposite to the direction of the disturbance of the waveform to be generated on the electrodes Y1 to Y6 is output instead of the non-selection voltage. The output time depends on each of the scanning electrodes Y1 to Y6.
Increases or decreases according to the magnitude of the disturbance of the waveform to be generated. In other words, the correction voltage is supplied for a long time for a large disturbance and a short time for a small disturbance, and thereafter, a non-selection voltage is supplied.

Therefore, the disturbance of the waveform to be generated in each of the scan electrodes Y1 to Y6 is substantially canceled. This allows the LCD panel 20
There is no difference in the effective voltage applied to each display dot of 1,
The display unevenness is eliminated.

As described above, when calculating the difference between the number of lit dots on one selected scan electrode and the next selected scan electrode, the position of the display pattern and the position driving the drive voltage waveform are considered. In addition, by making the amount of the correction voltage applied to the scanning electrodes different for each electrode based on this difference, display unevenness can be eliminated.

Second Embodiment In the first embodiment, a liquid crystal panel in which signal electrodes alternately supply signal voltage waveforms from above and below is described. For example, let us consider a case where supply is performed from above. Instead of the output of the TF / F 401 in FIG. 4, a signal that is always "1" may be supplied to the gate circuits 402U and L. (This means the same as disabling each of the circuits 402L and 406L to 410L. Therefore, these circuits become unnecessary. In addition, the circuit 405L becomes unnecessary, and the circuit 412 becomes unnecessary. Can be simplified because the input from 411L is always 0). Thus, the numerical value 1 is calculated as I = (I1 + I2) * f (k).

By performing the same operation as in the first embodiment based on this numerical value I, the same effect can be obtained.

Third Embodiment In the first and second embodiments, the liquid crystal panel that supplies a signal voltage waveform from only one of the signal electrodes has been described.

That is, in the first embodiment, when calculating the numerical value I, the function f
What is necessary is just to calculate by replacing (k) with the function g (| k−L / 2 |). Here, the function g (x) is an increasing function that increases as the numerical value x increases.

By performing the same operation as in the first embodiment based on this numerical value I, the same effect can be obtained.

In the first to third embodiments, as a method of adjusting the correction amount, a method of making the voltage difference between the correction voltage and the non-selection voltage constant and increasing or decreasing the time during which the correction voltage is applied (hereinafter referred to as time-axis correction) Is used, but the time for applying the correction voltage may be fixed, and the difference between the correction voltage and the non-selection voltage may be changed. (This is referred to as voltage axis correction.) Further, both the time for applying the correction voltage and the voltage may be changed. (This is called time voltage axis correction.) Further, a waveform represented by an exponential function whose peak value changes according to a required correction amount or a triangular waveform may be used as the correction voltage. (This is referred to as function waveform correction.) Embodiment 4 Next, an embodiment for display unevenness due to weft threading will be described.

As described above, for the selected scan electrode among the scan electrodes Y1 to Ys, this scan electrode and each signal electrode Xp (p
= 1, 2,..., R) represents the position of the display dot, The unevenness of the display due to the weft threading occurs to the extent corresponding to the numerical value Z 'calculated by the following equation. In other words, according to the numerical value Z ', the effective voltage applied to the display dot on the scan electrode of interest becomes smaller. Therefore, the numerical value Z 'may be calculated while operating the liquid crystal display device, and the correction may be performed according to the numerical value Z'. This will be described with a specific configuration example. FIG. 8 shows the configuration of this embodiment. In FIG. 8, 102
And 103 have the same control signal and data signal as those in FIG. 1, and therefore are denoted by the same reference numerals and description thereof will be omitted. A liquid crystal unit 801 includes a liquid crystal panel 201, a scanning electrode driving circuit 805, and a signal electrode driving circuit 213. Reference numeral 804 denotes a voltage waveform correction circuit (hereinafter abbreviated as a correction circuit) which calculates a numerical value Z 'and activates a correction signal 809 for a time corresponding to the numerical value.
make. 805 is a power supply circuit. And 806 is the power circuit
Power supply for two sets of scan electrodes required to drive the scan electrodes output from 805 (consists of select voltage and non-select voltage,
Hereinafter, it is referred to as a Y power source. ). And the power supply circuit 805
Outputs a different voltage as a selection voltage of the Y power supply 806 when the correction signal 809 is active and inactive. 106 is the 2 necessary to drive the signal electrode output from the power supply circuit 805
A power supply for a set of signal electrodes (hereinafter referred to as an X power supply) is the same as the X power supply 107 in FIG. Reference numeral 809 denotes a correction signal that determines the amount of the correction voltage output from the correction circuit 804.

Here, an example of a specific configuration of each component in FIG. 8 is shown. FIG. 9 shows an example of a specific configuration of the liquid crystal unit 801. In the figure, reference numeral 201 denotes a liquid crystal panel which is the same as that of the first embodiment. Reference numeral 805 denotes a scan electrode drive circuit (hereinafter, referred to as a Y driver), which includes a shift register circuit 206, a switch circuit 911, and a level shifter circuit 912. Then, the output of the level shifter circuit 912 is guided to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 201. The shift register circuit 206 is the same as in the first embodiment, and the description is omitted. The switch circuit 911 selects one of the two sets of voltages of the Y power supply 806 output from the power supply circuit 804 of FIG. 8 by the signal FR. That is,
Of the four voltages V0 ', V1, V4, V5' constituting the Y power supply 806, the voltages V0 ', V4 are divided into a first set of voltages and the voltages V5', V1 are divided into a second set of voltages. , A switch circuit for switching to one of the two sets of voltages in response to a signal FR. Here, the voltages V0 'and V4 are referred to as a selection voltage and a non-selection voltage of the first voltage set, respectively. Similarly, the voltage V5 ′,
V1 is referred to as a selection voltage and a non-selection voltage of the second voltage set. One of the two sets of voltages selected by the switch circuit 911 is supplied to the level shifter circuit 912.

Reference numeral 912 denotes a level shifter circuit which is constituted by a plurality of two-circuit, one-contact switches, which are switched according to the contents of the shift register 206.

That is, when the content is “1”, each switch selects the selection voltage and the corresponding scan electrode Y1
Output to ~ Y6.

When “0”, each switch selects the non-selection voltage, and the corresponding scan electrode
Output to Y1 to Y6.

The configuration of the Y driver 905 is as described above. Here, the operation of the Y driver 905 will be described. Signal DIN
The data is taken into the shift register 206 and transferred in synchronization with the LP. As a result, one switch of the level shifter circuit 912 sequentially outputs the selection voltage in response thereto.
Then, the remaining switches output the non-selection voltage. The configuration and operation of the Y driver are as described above. Reference numeral 213 denotes a signal electrode drive circuit (hereinafter referred to as an X driver), which is the same as that of the first embodiment, and a description thereof will be omitted.

The liquid crystal unit 801 has the above configuration.
Therefore, the liquid crystal unit 801 synchronizes with the signals DIN and LP,
A selection voltage is sequentially applied to the scan electrodes Y1 to Y6, and in synchronization with this, a lighting or non-lighting voltage according to the display pattern is applied to the signal electrodes X1 to X6, and the liquid crystal panel 201 displays.

 The liquid crystal unit 801 performs the above operation.

Next, in FIG. 8, reference numeral 804 denotes a correction circuit, and among the scanning electrodes Y1 to Y6, for the scanning electrode selected next, this scanning electrode and each signal electrode Xp (p = 1, 2,..., 6) are formed. Let p be the position of the display dot, Is calculated, and when the next selected scanning electrode is selected, the active correction signal 809 is output in synchronization with the signal LP by a length corresponding to the numerical value Z '. FIG. 10 shows a specific configuration example, which will be described in detail. In FIG. 10, reference numeral 1001 denotes a counter, 1002 denotes a constant generation circuit, 1003 denotes a gate circuit which takes the logical product of each of a plurality of output signals representing numerical values output from the constant generation circuit 1002 and the data signal 103,
4 is an arithmetic circuit for performing addition, 1005 is a first latch circuit for holding the arithmetic result of the arithmetic circuit 1005, 1006 is a second latch circuit, 1007 is an active correction for a time corresponding to the contents of the second latch circuit. A correction signal generation circuit (hereinafter, abbreviated as a generation circuit) that generates the signal 809 in synchronization with the signal LP.

The counter circuit 1001 is a counter that is reset to 0 by a signal LP and counts up by a signal XSCL. The output of the counter 1001 is supplied to a constant generation circuit 1002.

The constant generation circuit 1002 is configured by a ROM, a diode matrix, or the like, and outputs different numerical values according to the output of the counter circuit 1001. That is, the counter circuit 1001
When the numerical value output by becomes large, a large numerical value is output accordingly. This corresponds to the function q (i) in equation (1). Here, i is obtained by adding 1 to the numerical value output from the counter circuit 1001.

The value of the function may be obtained by an experiment or the like, and is simply set as follows in the present embodiment.

When i = 1, q (1) = 1 When i = 2, q (2) = 1.1 When i = 3, q (3) = 1.2 When i = 4, q (4) = 1.3 i = 5, q (5) = 1.4, i = 6, q (6) = 1.5 The gate circuit 1003 forms the logical product of the numerical value output from the constant generation circuit 1002 and the data signal 103. That is, at the time of falling of a certain signal XSCL, if the data signal is active “1”, the numerical value of the constant generation circuit 1002 is output as it is, and if it is inactive “0”, 0 is output. this is,
This corresponds to q (i) * δ (i) in equation (1).
Here, i is the number of falls of the signal XSCL after the fall of the signal LP, and is equal to the value output by the counter 1001 plus one.

1004 is an arithmetic circuit, which is used to output the numerical value of the gate circuit and the first
The contents of the latch circuit 1005 are added in synchronization with the signal XSCL,
The result is returned to the first latch circuit 1005.

1005 and 1006 are first and second latch circuits. The first latch circuit holds the result of the arithmetic circuit 1004. The first latch circuit 1005 is reset to 0 by the signal LP. The contents of the latch circuit 1005 immediately before being reset are expressed by the following equation (1). Corresponding to the numerical value Z ′ of That is, the number of lighting dots on the next selected scanning electrode is counted by weighting according to the position of the lighting dot.

The contents of the second latch circuit 10 are set at the falling edge of the signal LP just before the first latch circuit is reset.
Get absorbed in 06. Here, since the next scan electrode is selected at the fall of the signal LP, the numerical value indicated by the second latch circuit 1006 indicates the number of weighted lighting dots on the selected scan electrode.

Reference numeral 1007 denotes a generation circuit which outputs an active "1" correction signal 809 for a time corresponding to the value indicated by the second latch circuit 1006 in synchronization with the signal LP.

The circuit 1007 generates, for example, a signal XSCL as it is, or an oscillation circuit 1008 that generates a clock obtained by dividing or multiplying the signal (hereinafter referred to as a correction clock), counts up using the correction clock, and sets the count to 0 by the signal LP. This can be easily realized by a counter circuit 1009 to be reset and a coincidence detection circuit 1010 that generates an active “1” signal until the value indicated by the output of the counter circuit 1009 and the value indicated by the second latch circuit match. Here, the period of the correction clock does not have to be at regular intervals, and is determined by, for example, an experiment.

Since the correction circuit is constructed as described above, the number of lighting dots on this scanning electrode is weighted and counted for the next selected scanning electrode, and the scanning electrode is activated by a length corresponding to the numerical value Z '. When the next scanning electrode to be selected is selected, the correction signal 809 is output in synchronization with the signal LP.

Next, the power supply circuit 805 in FIG. 8 will be described with reference to FIG. Eleventh
The figure shows an example of a specific configuration of the power supply circuit 805. In the figure, 110
1-1107 are resistors, which are connected in series. Voltages V0U and V5L are applied to both ends. These resistors 1101-1107 work as a voltage divider. Here, the voltage generated in each of the resistors 1101-1107 is represented by V0U, V0, V1, V
Assuming that 2, V3, V4, V5, V5L, V≡V0−V1 = V1−V2 = V3−V4 = V4−V5, V2−V3 = a * V, a is a constant, and a value of about 1 to 50 Take.

The resistance values of each of the resistors 1101 to 1107 are set so that the following equation (3) holds: V0U−V0 = V5−V5L.

510 is the same as the voltage stabilizing circuit 510 of the first embodiment, and the description is omitted.

1108 and 1109 are switch circuits. The switch circuit selects the voltage V0U when the correction signal 809 is active “1”, and selects the voltage V0 when the correction signal 809 is inactive “0”. Then, the selected voltage is set to a voltage V0 '. Similarly, the switch 1109 selects the voltage V5L when the correction signal 809 is active “1”, and selects the voltage V5 when the correction signal 809 is inactive “0”. Then, the selected voltage is set to a voltage V5 '. Here, the voltages V0U and V5L are called correction voltages.

With the above configuration, the voltages V0 ', V4, V5', and V1 are supplied to the liquid crystal unit 801 shown in FIG. 8 as the Y power supply 106 and the voltages V0, V2, V3, and V5 as the X power supply.

 The liquid crystal display device of FIG. 8 has the above configuration.

Here, the operation of the present embodiment in the case where a quadrangle is actually displayed will be described. FIGS. 12 and 13 show the liquid crystal panel of FIG.
FIG. 4 is a diagram showing display contents displayed by 201. Figures 12 and 13
In the figure, the hatched display dots represent lighting, and in this display example, both of FIG. 12 and FIG. 13 indicate that the congruent rectangle is displayed by left and right respectively. . The embodiment at the time of this display operates as follows.

First, when the display of FIG. 12 or FIG. 13 is performed,
The correction circuit 804 in FIG. 8 counts the number of lighting dots on each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 201 in FIG. 12 or FIG. . Here, the numerical value Z 'for each of the scanning electrodes Y1 to Y6 is as follows.

When the display shown in FIG. 12 is performed, scanning electrodes Y1... Z '= 0 + 0 + 0 + 0 + 0 + 0 = 0 scanning electrodes Y2... = 2.1 scan electrode Y4 ... Z '= 1.0 * 1 + 1.1 * 1 + 0 + 0 + 0 + 0 = 2.1 scan electrode Y5 ... Z' = 1.0 * 1 + 1.1 * 1 + 0 + 0 + 0 + 0 = 2.1 scan electrode Y6 ... Z '= 0 + 0 + 0 + 0 + 0 + 0 = 0 As shown in FIG. When performed, scan electrode Y1 ... Z '= 0 + 0 + 0 + 0 + 0 + 0 = 0 scan electrode Y2 ... Z' = 0 + 0 + 0 + 0 + 1.4 * 1 + 1.5 * 1 = 2.9 scan electrode Y3 ... Z '= 0 + 0 + 0 + 0 + 1.4 * 1 + 1.5 * 1 = 2.9 Scan electrode Y4 ... Z '= 0 + 0 + 0 + 0 + 1.4 * 1 + 1.5 * 1 = 2.9 Scan electrode Y5 ... Z' = 0 + 0 + 0 + 0 + 1.4 * 1 + 1.5 * 1 = 2.9 Scan electrode Y6 ... Z '= 0 + 0 + 0 + 0 + 0 + 0 = 0 Te, of Figure 8 correction circuit 804 outputs only active correction signal 809 length of time corresponding to a number Z '.

The power supply circuit 805 outputs the correction voltages V0U and V5L instead of the voltages V0 and V5 as the selection voltage only during the period when the correction signal 809 is active.

Here, the numerical value Z 'for the scan electrodes Y2 to Y5 in the case of the display of FIG. 12 is smaller than that in the case of the display of FIG. Therefore, when the display of FIG. 12 is performed, the scanning electrodes Y2 to
When Y5 is selected, the time during which the correction voltages V0U and V5L are applied as the selection voltage is shorter than that in the case of the display of FIG. The Y driver 905 of FIG. 9 sequentially applies the selection voltage to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 201 using the selection voltage that changes according to the numerical value Z ′.

The operation of the X driver 213 is the same as in the first embodiment, and a description thereof will be omitted.

In order to perform the above operation, as shown in a display example as shown in FIG. 12, for the scan electrodes Y2 to Y5, when the lighting dot is near the drive end of the scan electrode, the voltage on the scan electrode is changed. A selection voltage having a small amount of correction voltage is supplied to the selected scan electrode in response to the fact that the waveform does not become too large. That is, the correction voltages V0U and V5L
Instead of V0 and V5, a voltage with a short applied time is supplied as a selection voltage. Conversely, as shown in a display example as shown in FIG. 13, with respect to the scan electrodes Y2 to Y5, when the lighting dot is far from the drive end of the scan electrode, the voltage waveform on the scan electrode becomes blunt. A selection voltage having a large amount of correction voltage is supplied to the selected scan electrode in response to an increase in the generation potential. That is, the correction voltages V0U and V5L are equal to the voltages V0 and V5.
Is supplied as the selection voltage. Accordingly, it is possible to substantially correct the difference in the correction amount from the display positions in FIG. 12 and FIG. As described above, when counting the number of lighting dots on each scanning electrode, weighting is performed in consideration of the position of the lighting dot, the counting is performed, and the selection voltage supplied to each scanning electrode is changed according to the result. Can eliminate display unevenness.

Fifth Embodiment In the fourth embodiment, the liquid crystal panel in which the scanning voltage waveform is supplied from only one of the scanning electrodes has been described. That is, in the fourth embodiment, when calculating the numerical value Z ′, the function q (i) is replaced by the function p (| i−S /
2 |). Where the function p
(X) is a decreasing function that decreases as the numerical value x increases.

By performing the same operation as in the fourth embodiment based on this numerical value Z ', the same effect can be obtained.

In the fourth embodiment, as a method of adjusting the correction amount, the difference between the voltages V0U and V0 and the difference between the voltages V5 and V5 are kept constant, and the voltage V0
How to increase or decrease the time that U, V5L is added as the selection voltage,
That is, although the time axis correction is used, other methods such as a voltage axis correction, a time voltage axis correction, and a function waveform correction method may be used.

Further, the first to second and third embodiments change the non-selection voltage,
In the fourth and fifth embodiments, since the selection voltage is changed, it goes without saying that the correction method for the uneven display according to the first and fourth embodiments can be performed simultaneously. In the first to fifth embodiments, the correction voltage applied to the scanning electrode has been described. However, the correction voltage can be applied to the signal electrode according to the distance to the selected pixel.

〔The invention's effect〕

As described above, according to the present invention, the correction voltage for compensating for the deviation of the effective voltage applied to the liquid crystal layer, which is generated when the voltage level of the signal voltage waveform changes, is applied to the scan electrode, Since the difference is made according to the distance from the end on the side to which the waveform is applied to the selected scanning electrode, the effective voltage applied to the liquid crystal layer can be compensated, and an appropriate display state can be obtained. No liquid crystal device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a device configuration of a first embodiment of the liquid crystal display device of the present invention. FIG. 2 is a diagram showing a configuration of a liquid crystal unit. FIG. 3 is a diagram showing a configuration of a scan electrode drive circuit. FIG. 4 is a block diagram showing a configuration of a voltage waveform correction circuit (correction circuit). FIG. 5 is a diagram showing a configuration of a power supply circuit. FIG. 6 is a perspective view of a liquid crystal panel showing an example of display contents. FIGS. 7 (a) to 7 (g) are waveform diagrams of voltages applied to the liquid crystal panel when the display of FIG. 6 is performed. FIG. 8 is a diagram showing a device configuration of a fourth embodiment of the liquid crystal display device of the present invention. FIG. 9 is a diagram showing a configuration of the liquid crystal unit. FIG. 10 is a block diagram showing a configuration of a correction circuit. FIG. 11 is a diagram showing a configuration of a power supply circuit. FIG. 12 is a perspective view of a liquid crystal panel showing an example of another display content. FIG. 13 is a perspective view of a liquid crystal panel showing still another example of display contents. FIG. 14 is a perspective view of a liquid crystal panel showing an example of display contents in a conventional technique. FIGS. 15 (a) to 15 (c) are diagrams showing voltage waveforms actually applied to the liquid crystal panel when the display of FIG. 14 is performed. FIG. 16 is a perspective view of a liquid crystal panel showing an example of another display content. FIG. 17 is a perspective view of a liquid crystal panel showing still another example of display contents. 101, 801 Liquid crystal unit 102 Control signal 103 Data signal 104, 804 Voltage waveform correction circuit (correction circuit) 105, 805 Power supply circuit 106, 806 Y power supply 107 X power supply 108 …… A circuit that creates a clock signal synchronized with the signal LP 109 …… Correction signal 110 …… Clock signal

Claims (2)

(57) [Claims] 1. A scanning electrode group is formed on one of a pair of substrates sandwiching a liquid crystal layer, and a signal electrode group is formed on the other substrate, and a scanning voltage waveform is applied to the scanning electrode group. Means, a means for applying a signal voltage waveform to the signal electrode group, and the scanning with a correction voltage for compensating for a shift in an effective voltage applied to the liquid crystal layer which occurs when a voltage level of the signal voltage waveform changes. A liquid crystal device having a means for superimposing the correction voltage on a voltage waveform, wherein the correction voltage is varied according to a distance from an end on the side where the voltage waveform is applied to the signal electrode to the selected scanning electrode. A liquid crystal device comprising: 2. A scanning electrode group is formed on one of a pair of substrates sandwiching a liquid crystal layer, and a signal electrode group is formed on the other substrate. A scanning voltage waveform is applied to the scanning electrode group. Applying a signal voltage waveform to the signal electrode group, and superimposing on the scanning voltage waveform a correction voltage for compensating for a shift in an effective voltage applied to the liquid crystal layer that occurs when a voltage level of the signal voltage waveform changes. A driving method of the liquid crystal device, wherein the correction voltage is changed according to a distance from an end on a side where a voltage waveform is applied to the signal electrode to the selected scanning electrode. A method for driving a liquid crystal device, comprising applying a voltage to a liquid crystal layer.