JP2864238B2 - ATM cell generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM used for testing an ATM transmission apparatus or an ATM network.
The present invention relates to a technique for generating a cell data string as many patterns with a limited memory capacity in a cell generator.

[0002]

2. Description of the Related Art In an ATM transmission apparatus or ATM network, data of a predetermined bit length (for example, 53 bytes) composed of transmission address information and transmission data information is defined as one cell data, and communication is performed in units of this cell data. Is going.

Conventionally, an ATM cell generator 10 shown in FIG. 5 is used to perform such an error test of a transmission device or a network.

The ATM cell generator 10 is provided with a cell memory 11 and a traffic memory 12. The cell memory 11 has the cell data Ds of the type desired to be output by the cell data writing means 13 a of the setting unit 13.
(1) to Ds (N) are head addresses A (1), respectively.
ＡA (N) to 53 bytes.

In the traffic memory 12, the head address of any cell data among the cell data stored in the cell memory 11 is set to 0 in the order of output by the pattern data writing means 13 b of the setting unit 13. Addresses from address to n-1 are written. Note that the traffic memory 12 is written with flag data F for indicating whether or not the cell data at the head address is the end of a series of cell data strings together with the head address of the cell data. In this example, one piece of flag data represents the end of a series of cell data strings.

The control unit 15 receives an instruction to output cell data from the cell data output instructing means 13 c of the setting unit 13 in a state where the data has been written to the cell memory 11 and the traffic memory 12 by the setting unit 13, and The cell data is sequentially read from the cell memory 11 in the order according to the data stored in the memory 12 and output.

[0007] The control unit 15 includes the traffic memory 1
A first address counter 16 for designating a read address for cell 2, a second address counter 17 for designating a read address for cell memory 11, and first and second address counters 16 and 17 are controlled. It is configured by the controller 18.

When the controller 18 receives an instruction to output cell data from the cell data output instructing means 13c as shown in FIG. 6A, the first address counter as shown in FIG. The data A (1) of address 0 of the traffic memory 12 is read out by resetting the data A16, and the data A (1) is preset in the second address counter 17 as shown in FIG. The second address counter 17 is incremented by one. Therefore, A (1), A (1) +1,.
(1) An address is specified up to +52, and cell data Ds (1) is output from the cell memory 11 as shown in FIG. Before the output of the second address counter 17 reaches A (1) +52, the first address counter 16 is incremented by one, and
The address data A (4) is read out and the cell data Ds
When the output of (1) is completed, the data A (4) is preset in the second address counter 17, and the second address counter 17 increases by one from A (4) in the same manner as described above. Cell data Ds (4) is output.

Hereinafter, similarly, the traffic memory 1
2 are sequentially output, and when the n-th data A (3) is read out, the traffic memory 12 outputs the data from the traffic memory 12 as shown in FIG. The flag data F of 1 is output. When receiving the flag data F, the controller 18 presets the data A (3) output at that time to the second address counter 17 and stores the data A (3) in the cell data Ds.
While (3) is being output, the first preset counter 16 is reset, the data A (1) at address 0 of the traffic memory 12 is read again, and the cell data string output so far is repeated. Output.

Therefore, the ATM cell generator 10 repeatedly outputs n continuous cell data corresponding to the n data stored in the traffic memory 12, respectively.

[0011]

However, in such a conventional ATM cell generator 10, since the maximum repetition pattern length R can be obtained only for the number of addresses in the traffic memory 12, the data of the data actually transmitted is not obtained. The only way to perform a test using various types of cell data is to increase the capacity of the traffic memory.

For example, when a traffic memory having an address space of 17 bits is used, the maximum repetition pattern length R is 13,1072 cells. An expensive memory having an address space of 24 bits or more, which is 7 bits larger, must be used, and the increase in the address space increases the size of the device.

An object of the present invention is to provide an ATM cell generator which solves this problem and can increase the maximum repetition pattern length with a limited memory capacity.

[0014]

To achieve the above object, an ATM cell generator according to the present invention comprises a cell memory (21) in which cell data is stored in advance and a cell memory (21) stored in the cell memory. A traffic memory (2) in which data for designating the data output order is stored in advance.
2) and a control unit (25) for sequentially reading data stored in the traffic memory and outputting cell data corresponding to the read data from the cell memory.
Wherein the traffic memory has a sequence information area and a plurality of pattern information areas, and in each of the pattern information areas, a cell memory address of cell data is stored in advance in the output order. In the sequence information area, a plurality of traffic memory addresses for designating a plurality of the pattern information areas are stored in advance, and the control unit is configured to control a traffic memory address stored in the sequence information area of the traffic memory. Are read in a predetermined order, the cell memory addresses stored in the pattern information area specified by the read traffic memory addresses are sequentially read, and the cell data specified by the read cell memory addresses are read from the cell memory. Configuration to output sequentially It has been.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an ATM cell generator 20 according to one embodiment.

The ATM cell generator 20 includes a cell memory 21, a traffic memory 22, a control unit 25 and a C memory.
It is configured by a setting unit 23 composed of a PU.

The cell memory 21 stores 5 bits from each of the start addresses A (1) to A (N) by the setting unit 23 in advance.
Arbitrary cell data Ds (1) to Ds in the range of 3 bytes
(N) are respectively written.

The traffic memory 22 has a sequence information area 22a having a start address of B (1) (address 0).
, And the start addresses are B (2), B (3),.
B (M + 1) and is divided into a pattern information region 22b ₁ ~22b _M plurality (M number) which, in each pattern information region 22b ₁ ~22b _M, as shown previously in Figure 2 by the setting unit 23 Cell memory addresses A of up to m arbitrary cell data are stored in the output order.

On the other hand, in the sequence information area 22a, as shown in FIG. 2, head addresses B of up to m pattern information areas are stored in advance by the setting unit 23 in an arbitrary permutation combination. In the following description, a set of address data stored in each of the pattern information areas 22b _{1 to} 22b _M is referred to as pattern data Dp (1) to Dp, respectively.
(M), and a set of address data stored in the sequence information area 22a is called sequence data Dsq.

The sequence data Dsq and the pattern data Dp (1) to Dp (1)
In p (M), for example, the flag data Fa for designating the last pattern data of one cycle of the cell data string output by the ATM cell generator 20 with 1, and the sequence area 22
Each pattern information area 22b _{1 to} 22b _M designated by a
The flag data Fb which designates the last cell data of 1 by 1 is stored.

The setting section 23 is a cell data writing means 2 for writing arbitrary cell data to the cell memory 21.
And 3a, the pattern data writing means 23b for writing an arbitrary pattern data in each pattern information region 22b ₁ ~22b _M traffic memory 22, for writing an arbitrary sequence data in the sequence information area 22a of the traffic memory 22 Sequence data writing means 23c and control unit 2 for starting and stopping output of cell data
5 is provided.

When the control section 25 receives an output start instruction from the setting section 23, the control section 25 reads the sequence data Dsq in the sequence information area 22a of the traffic memory 22 from the beginning, and reads the pattern data Dp of the address specified by the data. Are read in order from the beginning, and the cell data at the address specified by the data is read from the cell memory 21.
The operation of reading data from is repeated.

The control unit 25, as shown in FIG.
First address counter 2 for specifying an address of sequence information area 22a of traffic memory 22
6. Pattern information area 22b of traffic memory 22
Any _{one of the} outputs of the second address counter 27 for designating the address of _{1 to} 22b _M , the third address counter 28 for designating the address of the cell memory 21, and the first and second address counters 26 and 27 Data selector 29 and first to third address counters 26 to 28 for selectively outputting one of them to traffic memory 22.
And a controller 30 for controlling the data selector 29.

FIG. 3 is a flowchart showing the processing procedure of the controller 30. Hereinafter, the operation of the ATM cell generator 20 will be described with reference to this flowchart.

The cell data Ds and the pattern data Dp
In the state where the sequence data Dsq is stored as shown in FIGS. 1 and 2, when the start of cell data output is instructed from the setting unit 23 as shown in FIG. As shown in (d) to (f) of FIG. 4, the first to third address counters 26 to 28 are reset, and the data selector 29 is connected to the first address counter 26 (S1 to S3). Therefore, the traffic memory 22
, The address B (1) is designated, and the first data B (2) of the sequence data Dsq and the flag data Fa having this address as the start address are read (S).
4).

Then, the flag data Fa is latched, the first data B (2) is preset in the second address counter 27 as shown in FIG. 4E, and the data selector 29 is set in the second address counter 27. (S5 to S7).

For this reason, the address B (2) is designated in the traffic memory 22, and the first data A of the pattern data Dp (1) having the address B (2) as the head address.
(1) and the flag data Fb of 0 are read (S
8).

Then, the flag data Fb is latched, and the first data A (1) is preset in the third address counter 28 as shown in FIG.
Address A (1) is designated for No. 1 (S9 to S1)
0).

Here, a clock pulse of a predetermined cycle is given to the third address counter 28, and the cell data Ds (1) stored in the address A (1) to A (1) +52 of the cell memory 21 is stored. ) Is started (S11).

Next, while the reading of one cell is being performed, it is determined whether or not both of the flag data Fa and Fb are “1”. It is determined whether or not it is the last cell data of the pattern data. If it is not the last cell data, the count value of the second address counter 27 is incremented by 1 from B (2) as shown in FIG. Increase the traffic memory 2
2 to the second data A of the current pattern data Dp (1)
(3) and the flag data Fb are read out, the flag data Fb is latched, and the process waits until the output of the currently output cell data is completed (S12 to S17).

When the output of the cell data is completed, the process returns to step S10, where the second data A (3) is preset in the third address counter 28, and the cell memory 2
The output of the cell data Ds (3) stored with the address A (3) of 1 as the head address is started. In addition,
If output stop is instructed from the setting unit 23 while waiting for the end of cell data output, the process returns to step S1 and waits for the next output instruction (S18).

By repeating the processes S10 to S18, the cell memory 21 outputs the cell data Ds (1) of each address specified by the pattern data Dp (1) as shown in FIG. , Ds (3), ..., Ds
(12) will be output in order.

During the output of the last data (m-th data) A (12) of the pattern data Dp (1),
The count value of the first address counter 26 is incremented by 1, and the data selector 29 sets the first address counter 26
(S19-S20). Therefore, the second data B (4) of the sequence data Dsq and the flag data Fa are read out, the flag data Fa is latched, and the data B (4) is preset in the second address counter 27. The selector 29 is switched to the second address counter 27 side, and the process proceeds to step S15, where the pattern data Dp stored in the traffic memory 22 with the address B (4) as the leading address.
The first data A (11) of (3) is read, and following the cell data Ds (12) currently being output, the address A (1) is read.
The cell data Ds (11) stored in the cell memory 21 is output with 1) as the start address (S21 to S21).
24).

Therefore, as shown in FIG. 4G, the pattern data Dp (1) is output from the cell memory 21.
Pattern data Dp following the cell data string specified in
Cell data Ds (11), Ds specified in (3)
(4),..., Ds (2) are output. Similarly, pattern data specified by the sequence data Dsq is sequentially selected, and specified by the selected pattern data. Cell data is output.

Then, the last data B (3) of the sequence data Dsq is read out together with one flag data Fa, and the pattern data Dp (2) of the traffic memory 22 specified by the data B (3) is read out. Of the last data A (5) and 1 flag data Fb are read out,
When the cell data Ds (5) having the address A (5) as the leading address is being output, the process proceeds to step S20 after the first address counter 26 is reset (S25).

For this reason, the series of cell data output up to that point is repeatedly output. Although the above example describes a case where the flag data Fb of “1” is not set in the pattern information area 22b ₁ , the flag data Fb may be set to “1”.

[0037] Here, if both the m number of addresses of the sequence information area 22a and the number of addresses of each pattern information region 22b ₁ ~22b _M, maximum repetition pattern length R 'cell data using the traffic memory 22 m ^{There are two} cells.

For example, when m = 8192, the maximum repetition pattern length R 'is 67, 108, 864 cells.
The maximum repetition pattern length R of cell data of the conventional device using the same capacity traffic memory is much longer than R = 131,072 cells.

In comparison with the general formula, the maximum repetition pattern length (capacity of the traffic memory 22) of the conventional device is m × (1 + M), whereas the maximum repetition pattern length R 'of the ATM cell generator 20 is as follows. Is m × m, so that when m> 1 + M, the maximum repetition pattern length R ′ of the ATM cell generator 20 is longer than the maximum repetition pattern length R of the conventional device using the same capacity of traffic memory.

In the above embodiment, the number of addresses in the sequence information area 22a and the number of
2b ₁ ~22b _M had together with m the number of addresses of may have different number of addresses in sequence information area 22a to the address number of each pattern information region 22b _{1 ~22b M,} Each pattern information area 22b ₁
The number of addresses of ２２22b _M may be different.

[0041]

As described above, the ATM cell generator according to the present invention divides the traffic memory into a plurality of pattern information areas and a sequence information area, and the plurality of pattern information areas each have a cell memory address of cell data. A plurality of traffic memory addresses for designating a plurality of pattern information areas are stored in advance in the sequence information area, and a plurality of traffic memory addresses stored in the sequence information area of the traffic memory are stored in the sequence information area. Are read in a predetermined order, the cell memory addresses stored in the pattern information area specified by the read traffic memory addresses are sequentially read, and the cell data specified by the read cell memory addresses are sequentially read from the cell memory. Configured to output To have.

Therefore, even if the capacity of the traffic memory is small, the maximum repetition pattern length of the cell data can be significantly increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a memory area and an example of data storage according to an embodiment;

FIG. 3 is a flowchart illustrating a processing procedure of a main part of the embodiment;

FIG. 4 is a timing chart for explaining the operation of the embodiment;

FIG. 5 is a block diagram showing the configuration of a conventional device.

FIG. 6 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

Reference Signs List 20 ATM cell generator 21 Cell memory 22 Traffic memory 22a Sequence information area 22b _{1 to} 22b _M pattern information area 23 Setting unit 25 Control unit 26 to 28 Address counter 29 Data selector 30 Controller

Claims (1)

(57) [Claims] 1. A cell memory in which cell data is stored in advance, and a traffic memory in which data for designating an output order of the cell data stored in the cell memory is stored in advance. An ATM cell generator comprising: a controller for sequentially reading data stored in the traffic memory and outputting cell data corresponding to the read data from the cell memory; Has a sequence information area and a plurality of pattern information areas, and the cell information addresses of the cell data are stored in advance in the respective pattern information areas in the output order, and the pattern information area is stored in the sequence information area. A plurality of traffic memory addresses for specifying a plurality are stored in advance, and the control Reads the traffic memory addresses stored in the sequence information area of the traffic memory in a predetermined order, sequentially reads the cell memory addresses stored in the pattern information area specified by the read traffic memory addresses, An ATM cell generator configured to sequentially output cell data designated by each read cell memory address from the cell memory.