JP2863284B2 - Thermal head array control circuit - Google Patents

Thermal head array control circuit

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Publication number
JP2863284B2
JP2863284B2 JP22438690A JP22438690A JP2863284B2 JP 2863284 B2 JP2863284 B2 JP 2863284B2 JP 22438690 A JP22438690 A JP 22438690A JP 22438690 A JP22438690 A JP 22438690A JP 2863284 B2 JP2863284 B2 JP 2863284B2
Authority
JP
Japan
Prior art keywords
phase
power supply
heating
printing
recording elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22438690A
Other languages
Japanese (ja)
Other versions
JPH04107160A (en
Inventor
武 豊澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GURAFUTETSUKU KK
Original Assignee
GURAFUTETSUKU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GURAFUTETSUKU KK filed Critical GURAFUTETSUKU KK
Priority to JP22438690A priority Critical patent/JP2863284B2/en
Publication of JPH04107160A publication Critical patent/JPH04107160A/en
Application granted granted Critical
Publication of JP2863284B2 publication Critical patent/JP2863284B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 [産業上の利用分野] この発明は感熱記録装置に使用するサーマルヘッドア
レイの制御回路に関するものである。
Description: TECHNICAL FIELD The present invention relates to a control circuit for a thermal head array used in a thermal recording apparatus.

[従来の技術] 第1図はサーマルヘッドアレイの構成を示す接続図
で、図において、(1)は電源、(2)はA相電源、
(3)はB相電源、(41),(42),(43)はそれぞれ
逆流阻止用ダイオード、(5)は発熱抵抗体、(61),
(62),(63),(64)はそれぞれ接地用スイッチで、
これらのスイッチはその制御回路と共にICで構成されて
いるが、第1図ではその機能を表すためスイッチとして
示す。(71),(72),(73)はそれぞれ電源側リード
導体、(81),(82),(83),(84)はそれぞれ接地
側リード導体である。
[Prior Art] FIG. 1 is a connection diagram showing a configuration of a thermal head array, in which (1) is a power supply, (2) is an A-phase power supply,
(3) is a B-phase power supply, (41), (42), and (43) are backflow prevention diodes, (5) is a heating resistor, (61),
(62), (63) and (64) are grounding switches, respectively.
These switches are constituted by ICs together with their control circuits, but are shown as switches in FIG. 1 to represent their functions. (71), (72) and (73) are power supply side lead conductors, and (81), (82), (83) and (84) are ground side lead conductors.

また、図中i,j,k,l,m,nで示す部分は、発熱抵抗体
(5)の各部で、それぞれ1個のサーマルヘッドを構成
する。
In the drawing, portions indicated by i, j, k, l, m, and n are the respective portions of the heating resistor (5), each constituting one thermal head.

たとえば、jで示すサーマルヘッドを加熱する場合
は、A相電源(2)に電源(1)を接続し、スイッチ
(62)を閉接することにより、リード導体(71)−(8
2)に電流が流れてサーマルヘッドjが加熱される。
For example, when heating the thermal head indicated by j, the power supply (1) is connected to the A-phase power supply (2), and the switch (62) is closed to connect the lead conductors (71)-(8
The current flows in 2), and the thermal head j is heated.

第3図はサーマルヘッドアレイの加熱制御を示す動作
タイムチャートである。第1図においてスイッチ(6
1),(62),(63),(64)で示す制御回路ICには、
シフトレジスタ,ラッチ,ドライバが含まれており、シ
フトレジスタにはスイッチの開閉に対応する論理のビッ
トパターンを有する信号が配列され、ラッチはロード信
号の入力時点のシフトレジスタのビットパターンをラッ
チし、ドライバは対応するラッチのビット論理が「1」
である場合に接続されている接地側リード導体をストロ
ーブ信号で定められる時間接地する。
FIG. 3 is an operation time chart showing the heating control of the thermal head array. In FIG. 1, the switch (6
1), (62), (63), (64)
The shift register includes a shift register, a latch, and a driver. A signal having a logical bit pattern corresponding to opening and closing of a switch is arranged in the shift register. The latch latches a bit pattern of the shift register at the time of input of the load signal. In the driver, the bit logic of the corresponding latch is "1"
In this case, the connected ground-side lead conductor is grounded for a time determined by the strobe signal.

第3図に示すクロックは、データをシフトレジスタ内
に配列するためのクロック信号であり、データのうちA
はA相電源印加時に接地すべきスイッチのデータを、B
はB相電源印加時に接地すべきスイッチのデータを示
す。ラッチa,ラッチbはそれぞれロード信号の入力時点
を示し、ストローブa,ストローブbはそれぞれラッチa,
ラッチbに対応するストローブ信号を示す。
The clock shown in FIG. 3 is a clock signal for arranging data in the shift register.
Is the data of the switch to be grounded when the A-phase power is applied,
Indicates data of a switch to be grounded when the B-phase power is applied. Latches a and b indicate the load signal input times, respectively, and strobe a and strobe b indicate the latches a and b, respectively.
7 shows a strobe signal corresponding to the latch b.

ラッチaで示すような制御を行うと、A相電源の印加
が終わってからのちB相電源の印加が開始されるまでの
時間(t3)−(t5)(以下AB相間時間という)がラッチ
bで示すAB相間時間(t10)−(t11)より短くなる。AB
相間時間が短いとA相電源で加熱されたサーマルヘッド
の部分の温度が十分に低下していないうちに、その隣の
サーマルヘッドがB相電源で加熱されることになる。こ
のような場合は加熱経歴を考慮して加熱時間を加減し、
どのような加熱経歴を持ったサーマルヘッドにより熱記
録される点の大きさも、同一の大きさになるように制御
しなければならない。
When the control as shown by the latch a is performed, the time (t3)-(t5) (hereinafter referred to as the AB-phase time) from the end of the application of the A-phase power to the start of the application of the B-phase power is determined by the latch b. Is shorter than the AB interphase time (t10)-(t11). AB
If the inter-phase time is short, the adjacent thermal head is heated by the B-phase power supply before the temperature of the portion of the thermal head heated by the A-phase power supply is not sufficiently lowered. In such a case, the heating time is adjusted in consideration of the heating history,
The size of the points thermally recorded by the thermal head having any heating history must be controlled to have the same size.

然しながら、AB相間時間を大きくすると総合的に印字
の速度を低下させることとなる。これに対しB相電源印
加時点から次のA相電源印加時点までの間には、シフト
レジスタのデータを更新するための時間が入るので加熱
経歴としてはAB相間時間ほど考慮しなくてもよい。
However, increasing the AB interphase time will generally decrease the printing speed. On the other hand, a time for updating the data of the shift register is inserted between the time of applying the B-phase power and the time of applying the next A-phase power, so that the heating history does not need to be considered as much as the time between the AB phases.

この発明は、加熱経歴を考慮して加熱時間を制御する
制御回路に関するものであるが、制御回路そのものは従
来の回路を用いるので、その説明は省略し、加熱経歴と
加熱時間をどのように関係付けるかについて説明する。
The present invention relates to a control circuit for controlling a heating time in consideration of a heating history. However, since the control circuit itself uses a conventional circuit, description thereof is omitted, and how the heating history and the heating time are related. It will be described how to attach.

[発明が解決しようとする課題] 上記のような従来のサーマルヘッドアレイの制御回路
は以上のように構成され動作するので、加熱経歴と加熱
時間との関係が複雑すぎて実用的でないという問題点が
あった。
[Problems to be Solved by the Invention] Since the above-described conventional thermal head array control circuit is configured and operates as described above, the relationship between the heating history and the heating time is too complicated to be practical. was there.

この発明はかかる課題を解決するためになされたもの
で、比較的簡単で実用的な加熱経歴と加熱時間との関係
を導入したサーマルヘッドアレイの制御回路を得ること
を目的としている。
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has as its object to obtain a relatively simple and practical control circuit for a thermal head array in which a relationship between a heating history and a heating time is introduced.

[課題を解決するための手段] この発明に係わるサーマルヘッドアレイの制御回路
は、A相電源印加時の影響はその直後のB相電源印加時
まで残るが、B相電源印加時の影響はその次のA相電源
印加時までは残らないとし、かつ互いに隣接するサーマ
ルヘッドだけが相互に影響を与え、それよりも離れてい
るサーマルヘッドは相互に影響を与えないとして、加熱
経歴と加熱時間との関係を簡単化することとした。
[Means for Solving the Problems] In the control circuit of the thermal head array according to the present invention, the influence when the A-phase power is applied remains until immediately after the B-phase power is applied. The heating history and the heating time are assumed to not remain until the next A-phase power application, and that only the thermal heads adjacent to each other affect each other, and the thermal heads farther away do not affect each other. I decided to simplify the relationship.

[作用] 加熱経歴を5段階に分け、各段階に対し適当な加熱時
間は実験により設定する。
[Action] The heating history is divided into five stages, and an appropriate heating time for each stage is set by experiments.

[実施例] 以下、この発明の実施例を図面を用いて説明する。第
2図は第1の例における加熱経歴の各段階を示す説明図
で、図において(62),(63),j,k,l,mは、第1図の同
一符号と同一部分を示し、各列に記入される「1」はス
イッチの閉、すなわちサーマルヘッドの通電を意味し、
「0」はスイッチの開を意味する。
Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is an explanatory diagram showing each stage of the heating history in the first example. In the figure, (62), (63), j, k, l, and m indicate the same parts as those in FIG. , "1" written in each row means that the switch is closed, that is, the thermal head is energized,
"0" means that the switch is open.

(イ)〜(チ)の各区画の上段はA相電源印加、下段
はその直後のB相電源印加を示す。(リ)〜(ル)はA
相電源印加でその前のB相電源印加は加熱経歴として無
視される場合を示す。
The upper part of each section (a) to (h) shows application of the A-phase power, and the lower part shows application of the B-phase power immediately thereafter. (R) to (R) are A
In this case, the application of the phase B power before the application of the phase power is ignored as the heating history.

(イ)の場合は同時に加熱されるk,lが相互に影響
し、かつ直前のA相電源印加の影響によりjがkに、m
がlに影響する。この場合はスイッチ(62),(63)共
に、A相およびB相で閉である。(ロ)ではスイッチ
(62)がA相およびB相で閉、スイッチ(63)がA相で
開、B相で閉となり、(ハ)ではスイッチ(63)がA相
およびB相で閉、スイッチ(62)がA相で開、B相で閉
となる。(ニ)では同時に通電されるk,lだけが相互影
響し、A相電源印加のときは隣接サーマルヘッドは加熱
されない。(ホ)と(ヘ)とではA相電源印加時の隣接
サーマルヘッドの影響だけが存在し、(ト)と(チ)で
は影響するサーマルヘッドは存在しない。一方、A相電
源印加時には(リ)の場合だけ同時に通電されるi,jの
サーマルヘッドが相互に影響する他は(ヌ)、(ル)の
場合には相互影響がない。
In the case of (a), k and l heated simultaneously affect each other, and j becomes k and m
Affects l. In this case, both the switches (62) and (63) are closed in the A phase and the B phase. In (b), the switch (62) is closed in A and B phases, the switch (63) is open in A phase and closed in B phase, and in (c), the switch (63) is closed in A and B phases. The switch (62) opens in phase A and closes in phase B. In (d), only the currents k and l that are energized at the same time affect each other, and when the A-phase power is applied, the adjacent thermal head is not heated. In (e) and (f), there is only the influence of the adjacent thermal head when the A-phase power is applied, and in (g) and (h), there is no such thermal head. On the other hand, when the A-phase power is applied, the thermal heads i and j that are simultaneously energized only in the case of (i) affect each other (nu) and in the case of (ru), there is no mutual effect.

また、第2図について加熱経歴から言えば、(ロ)=
(ハ),(ニ)=(リ),(ホ)=(ヘ),(ト)=
(チ)=(ヌ)=(ル)であるので、(イ)を第1の経
歴,(ロ)を第2の経歴,(ニ)を第3の経歴,(ホ)
を第4の経歴,(ト)を第5の経歴として、各経歴に対
し適当な通電時間を実験的に定め、この定めた通電時間
になるように制御すれば、どのような加熱経歴のサーマ
ルヘッドに対しても適当な熱記録結果を得ることができ
る。
Also, regarding the heating history of FIG. 2, (b) =
(C), (d) = (li), (e) = (he), (g) =
Since (h) = (nu) = (r), (b) is the first career, (b) is the second career, (d) is the third career, (e)
By setting the appropriate energizing time experimentally for each history with the fourth history as the fifth history and the fifth history as the fifth history, and controlling so as to reach the determined energizing time, the thermal history of any heating history can be obtained. Appropriate thermal recording results can also be obtained for the head.

[発明の効果] この発明は以上説明したように、加熱経歴と加熱時間
との関係を簡単化して実用的な制御を行うサーマルヘッ
ドアレイの制御回路を得ることができるという効果があ
る。
[Effects of the Invention] As described above, the present invention has an effect that a control circuit for a thermal head array that performs practical control by simplifying the relationship between the heating history and the heating time can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

第1図はサーマルヘッドアレイの構成を示す接続図、第
2図は第1図における加熱経歴を示す説明図、第3図は
サーマルヘッドアレイの加熱制御を示す動作タイムチャ
ート。 1……電源、2……A相電源、3……B相電源、41,42,
43……それぞれ逆流阻止ダイオード、5……発熱抵抗
体、61,62,63,64……それぞれ接地用スイッチ、71,72,7
3……それぞれ電源側リード導体、81,82,83,84……それ
ぞれ接地側リード導体。 なお、各図中同一符号は同一または相当部分を示すもの
とする。
FIG. 1 is a connection diagram showing a configuration of a thermal head array, FIG. 2 is an explanatory diagram showing a heating history in FIG. 1, and FIG. 3 is an operation time chart showing heating control of the thermal head array. 1 ... power supply, 2 ... A phase power supply, 3 ... B phase power supply, 41, 42,
43: Backflow blocking diodes, 5: Heating resistors, 61, 62, 63, 64: Ground switches, 71, 72, 7 respectively
3. Lead conductors on the power supply side, 81, 82, 83, 84 lead conductors on the ground side. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】直線状の発熱抵抗体、ほぼ等間隔に配列さ
れ上記直線状の発熱抵抗体にそれぞれ接続する複数のA
相電源用リード導体、これらのA相電源用リード導体の
それぞれの間のほぼ中間位置で上記直線状の発熱抵抗体
にそれぞれ接続する複数のB相電源用リード導体、各A
相電源用リード導体と当該A相電源用リード導体に隣接
するB相電源用リード導体のほぼ中間位置で上記直線状
の発熱抵抗体にそれぞれ接続する複数の接地側リード導
体とを基板上に設置し、各A相電源用リード導体と当該
A相電源用リード導体の両側の接地側リード導体とで区
画される直線状の発熱抵抗体の2つの領域をそれぞれ単
一のA相発熱記録素子とし、各B相電源用リード導体と
当該B相電源用リード導体の両側の接地側リード導体と
で区画される直線状の発熱抵抗体の2つの領域をそれぞ
れ単一のB相発熱記録素子として、連続する2つのB相
発熱記録素子の両側にそれぞれA相発熱記録素子が配列
されるよう構成し、各A相電源用リード導体を電源に接
続するとともに指定された接地側リード導体を接地して
各A相電源用リード導体に接続するA相発熱記録素子群
の内指定された記録素子について一括して印字するA相
印字動作と各B相電源用リード導体を電源に接続すると
ともに指定された接地側リード導体を接地して各B相発
熱記録素子群の内指定された記録素子について一括して
印字するB相印字動作とがこの順で行われて全ての発熱
記録素子群についての印字動作が行われるよう構成され
たサーマルヘッドアレイの制御回路であって、上記連続
する2つのB相発熱記録素子を印字させる場合直前のA
相印字動作による当該連続する2つのB相発熱記録素子
の両側のA相発熱記録素子の印字経歴を考慮するよう構
成されたサーマルヘッドアレイの制御回路において、 連続する2つのB相発熱記録素子が同時に印字されると
き、直前のA相印字動作において当該連続する2つのB
相発熱記録素子の両側のA相発熱記録素子がいずれも印
字しているときを第1の経歴とし、 連続する2つのB相発熱記録素子が同時に印字されると
き、直前のA相印字動作において当該連続する2つのB
相発熱記録素子の両側のA相発熱記録素子の内いずれか
が印字しているときを第2の経歴とし、 連続する2つのB相発熱記録素子が同時に印字されると
き、直前のA相印字動作において当該連続する2つのB
相発熱記録素子の両側のA相発熱記録素子のいずれも印
字されていないときを第3の経歴とし、 連続する2つのB相発熱記録素子のいずれか一方が印字
されるとき、直前のA相印字動作において当該連続する
2つのB相発熱記録素子の内印字されるべき記録素子に
隣接するA相発熱記録素子が印字しているときを第4の
経歴とし、 上記第1,第2,第3及び第4のいずれの経歴にも属さない
ものを第5の経歴とし、 上記第5,第4,第3,第2及び第1の経歴順に通電時間が短
くなるよう、上記連続する2つのB相発熱記録素子の印
字動作を行わせるよう構成したことを特徴とするサーマ
ルヘッドアレイの制御回路。
A plurality of linear heating resistors arranged at substantially equal intervals and connected to the linear heating resistors, respectively.
A plurality of B-phase power supply lead conductors respectively connected to the linear heating resistor at a substantially intermediate position between each of the A-phase power supply lead conductors and the A-phase power supply lead conductors;
A plurality of ground-side lead conductors respectively connected to the linear heating resistors are provided on the substrate at a substantially intermediate position between the phase-phase power supply lead conductor and the B-phase power supply lead conductor adjacent to the A-phase power supply lead conductor. The two regions of the linear heating resistor divided by each A-phase power supply lead conductor and the ground-side lead conductors on both sides of the A-phase power supply lead conductor are each used as a single A-phase heat generation recording element. The two regions of the linear heating resistor divided by each B-phase power supply lead conductor and the ground-side lead conductors on both sides of the B-phase power supply lead conductor are each a single B-phase heat generation recording element. An A-phase heating recording element is arranged on both sides of two continuous B-phase heating recording elements. Each of the A-phase power supply lead conductors is connected to a power supply, and a designated ground-side lead conductor is grounded. Lead for each A phase power supply A-phase printing operation for collectively printing the designated recording elements of the group of A-phase heating recording elements connected to the conductors, connecting each B-phase power lead conductor to the power supply and grounding the designated ground-side lead conductor Then, the B-phase printing operation for printing all the designated recording elements of each B-phase heating recording element group collectively is performed in this order, and the printing operation for all the heating recording element groups is performed. A control circuit of the thermal head array, which is used immediately before printing the two consecutive B-phase heating recording elements.
In a control circuit of a thermal head array configured to consider the printing history of the A-phase heating recording elements on both sides of the two consecutive B-phase heating recording elements by the phase printing operation, two continuous B-phase heating recording elements are provided. When printing is performed at the same time, the two consecutive B
When both the A-phase heating recording elements on both sides of the phase-heating recording element are printing, the first history is used, and when two consecutive B-phase heating recording elements are printed simultaneously, in the immediately preceding A-phase printing operation, The two consecutive B's
When one of the A-phase heating recording elements on both sides of the phase-heating recording element is printing, the second history is used. When two consecutive B-phase heating recording elements are printed simultaneously, the immediately preceding A-phase printing is performed. In operation, the two consecutive B's
When none of the A-phase heating recording elements on both sides of the phase heating recording element is printed, the third history is used. When one of two continuous B-phase heating recording elements is printed, the immediately preceding A-phase heating recording element is printed. In the printing operation, when the A-phase heating recording element adjacent to the recording element to be printed out of the two consecutive B-phase heating recording elements is printing, the fourth history is defined as the fourth career. The one that does not belong to any of the third and fourth careers is referred to as a fifth career, and the two successive ones described above are arranged in the order of the fifth, fourth, third, second, and first careers so as to shorten the energization time. A control circuit for a thermal head array, wherein the control circuit is configured to perform a printing operation of a B-phase heating recording element.
JP22438690A 1990-08-28 1990-08-28 Thermal head array control circuit Expired - Lifetime JP2863284B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22438690A JP2863284B2 (en) 1990-08-28 1990-08-28 Thermal head array control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22438690A JP2863284B2 (en) 1990-08-28 1990-08-28 Thermal head array control circuit

Publications (2)

Publication Number Publication Date
JPH04107160A JPH04107160A (en) 1992-04-08
JP2863284B2 true JP2863284B2 (en) 1999-03-03

Family

ID=16812938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22438690A Expired - Lifetime JP2863284B2 (en) 1990-08-28 1990-08-28 Thermal head array control circuit

Country Status (1)

Country Link
JP (1) JP2863284B2 (en)

Also Published As

Publication number Publication date
JPH04107160A (en) 1992-04-08

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