JP2862936B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a highly integrated semiconductor memory device having a memory cell structure including a so-called PSD transistor and a stacked capacitor. The present invention relates to a manufacturing method for improving a structure.

[Prior Art] As one of semiconductor storage devices, there is a so-called DRAM (Dynamic Random Access Memory) capable of randomly inputting and outputting storage information. The DRAM includes a memory cell array serving as a storage area for storing a large amount of storage information, and a peripheral circuit for performing a predetermined input / output operation on the memory cell array. The memory cell array is further configured by arranging a plurality of memory cells corresponding to the minimum storage unit. A memory cell basically includes one capacitor and one transfer gate transistor connected thereto. Then, in the operation, it is determined whether a predetermined charge is accumulated in the capacitor,
The stored information is processed in accordance with the data "0" and "1".

FIG. 7 is a partial plan structure diagram of a conventional DRAM memory cell array. FIG. 8 is a section line VIII-VI in FIG.
FIG. 9 is a cross-sectional structural view from the II direction, and FIG. 9 is a cross-sectional structural view from the cutting line IX-IX direction in FIG. Referring to FIGS. 7 to 9, a conventional DRAM memory cell includes a so-called LOCOS isolation film 2 in a predetermined region on a main surface of a semiconductor substrate 1. A channel stopper 3 of the same conductivity type as the semiconductor substrate 1 is formed below the LOCOS isolation film 2. On the main surface of the semiconductor substrate 1 surrounded by the LOCOS isolation film 2, one transfer gate transistor 10 and one capacitor 20 forming a memory cell are formed.

The transfer gate transistor 10 includes a pair of n-type impurity regions 13 and 13 formed on the surface of the semiconductor substrate 1,
Semiconductor substrate 1 located between a pair of n-type impurity regions 13
A gate electrode (word line) 11a is formed on the surface via a gate insulating film 12. The periphery of the gate electrode 11a is covered with the insulating layer 14. A word line 11b is formed above the LOCOS isolation film 2.

Capacitor 20 is connected to one n-type impurity region 13,
One end of the lower electrode (storage) is mounted on the upper portion of the gate electrode 11a via the insulating layer 14, and the other end is mounted on the upper portion of the word line 11b formed on the surface of the LOCOS isolation film 2 via the insulating layer 14. A node 21, a dielectric layer 22 formed on the surface thereof, and an upper electrode (cell plate) 23 further covering the surface.

The transfer gate transistor 10 and the capacitor 20 are electrically connected by connecting the lower electrode 21 of the capacitor 20 to one n-type impurity region 13 of the transfer gate transistor 10 via the capacitor contact 6.

[Problems to be Solved by the Invention] Such a conventional DRAM memory cell structure has the following problems in achieving high integration. First, a LOCOS isolation film 2 is used as an insulation isolation structure between memory cells.
Is used. The LOCOS isolation film 2 is a method for selectively forming a thick thermal oxide film at a predetermined position on the surface of the silicon substrate 1 using a so-called LOCOS method. And this LOCOS separation membrane 2
Has a part called a bird's beak at its end,
This invades the element formation region on the surface of the semiconductor substrate 1 and has a problem that the effective element formation area on the surface of the silicon substrate 1 is reduced. Further, a channel stopper 3 is formed in a lower region of the LOCOS isolation film 2. The channel stopper 3 is formed of ap ⁺ impurity region into which boron (B) having a concentration higher than the substrate concentration of the p-type semiconductor substrate 1 is introduced. Then, it functions to prevent the inversion layer from being formed in the lower region of the LOCOS isolation film 2. However, the channel stopper layer is thermally diffused and spread around the channel stopper layer by a high temperature (950 ° C.) thermal oxidation process for forming a LOCOS film. When this seeps into the channel region 17 of the transfer gate transistor 10 as shown in FIG. 9, for example, a so-called narrow channel effect occurs in which the channel width Lc is effectively narrowed. The narrow channel effect refers to a phenomenon in which the effective substrate concentration increases due to the diffusion of the channel stopper 3 into the channel region, and the threshold voltage of the transistor increases. In particular, since the channel stopper 3 is made of boron (B) having a large thermal diffusion coefficient, there is a face that it is difficult to avoid the occurrence of the narrow channel effect.

Further, n of the conventional transfer gate transistor 10
The diffusion width of the type impurity region 13 is set so that the contact portion 6 with the capacitor or the bit line contact 5 is formed.
The diffusion width is formed with a margin in advance so that a predetermined contact area can be secured. Therefore, it has a weakness against soft errors. Here, the soft error will be described. In the DRAM, a soft error occurs in two modes. One is a memory cell mode and the other is a bit line mode. In the memory cell mode, when the high-level voltage corresponding to “1” is held in the memory cell capacitor, noise charges generated by α particles flow into the storage capacitor and the high-level signal charges become “0”. This is a soft error mode caused by changing to a corresponding low-level signal. FIG. 11 is a schematic sectional view of a memory cell for explaining the soft error. Referring to FIG. 11, in a conventional memory cell structure, an n-type semiconductor layer having a charge storage layer formed on a substrate is provided.
When the high-level voltage is written to the charge storage layer, a thick depletion layer 18 is formed. When electrons, which are minority carriers generated by the α-particles 27, flow into the thick depletion layer 18, the written high-level voltage is inverted to a low-level voltage. That is, inversion from “1” to “0” occurs.

The bit line mode occurs when electrons generated by the α-particles 27 flow into the n-type impurity region 13 connected to the bit line 25. FIG. 10 is an equivalent circuit diagram of the memory cell array. Referring to FIGS. 10 and 11, the bit line is in a floating state from when a word line for a specific memory cell is selected until when sense amplifier 40 is operated. However, during this time, the signal voltage stored in the memory cell or the dummy cell remains read on the bit line. Therefore, at this time, when the electrons generated by the α particles flow into the bit line, the potential of the bit line changes. The signal voltage read from the memory cell becomes extremely small after reading due to capacitance division by the storage capacitance and the bit line capacitance. Therefore, when the electrons generated by the α particles flow, the signal is easily inverted. This inverted signal is then amplified by the sense amplifier 40 and detected as an erroneous signal. Such soft errors can be caused by the conventional DRAM.
Since the n-type impurity regions 13 of the memory cell have a relatively large surface area, electrons generated by the α-particles easily flow in, and the probability of occurrence of a soft error is high.

On the other hand, the inventors have proposed an isolation structure in which an insulating layer is buried between conductive layers for source / drain electrodes as an isolation structure capable of reducing an isolation region. This is "DEEP SUBMICRON
DEVICE ISOLATION WITH BURIED INSULATOR BETWEEN SO
URCE / DRAIN POLYSILICON (BIPS) ": IEDM88, P96 ~ 99, M.
Shown in Shimizu et al. 12A to 12E are cross-sectional views showing manufacturing steps in which the above-described isolation structure is applied to a PSD transistor isolation structure. Referring to FIG. 12A, an insulating layer 16 having a predetermined opening region is formed on the surface of semiconductor substrate 1. Further, a polycrystalline silicon layer 15a and an insulating layer 16a are sequentially formed on the surface of the semiconductor substrate 1.

Next, referring to FIG. 12B, insulating layer 16a and polycrystalline silicon layer 15a are patterned into a predetermined shape. Thereby, an opening region for element isolation is formed in the polycrystalline silicon layer 15a. Then, boron (B) ions are ion-implanted into the surface of the semiconductor substrate 1 using the patterned insulating layer 16a and the polycrystalline silicon layer 15a as a mask.

Further, referring to FIG. 12C, heat treatment is performed to thermally diffuse the n-type impurities introduced into polycrystalline silicon layer 15a to the surface of semiconductor substrate 1. With this process, n-type impurity regions 13 and 13 serving as source / drain regions of the transistor are formed. Thereafter, an insulating layer 4a such as a silicon oxide film is deposited on the surface of the semiconductor substrate 1. Then, a resist 26 is applied on the surface to flatten the surface.

Further, referring to FIG. 12D, the resist 26 and the insulating layer 4a are etched back to form a buried separation layer 4 in a predetermined separation region.

Thereafter, referring to FIG. 12E, a predetermined region of the polycrystalline silicon layer 15a is opened, a gate insulating film 12 is formed, and then a polycrystalline silicon layer is formed on the entire surface of the semiconductor substrate 1 and patterned into a predetermined shape. I do. As a result, the gate electrode 11a is formed.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-described problems, and a method of manufacturing a semiconductor memory device having a highly integrated memory cell structure that does not cause a narrow channel effect or a soft error is provided. The purpose is to provide.

[Means for Solving the Problems] The invention according to claim 1 is a transistor including a conductive layer connected to an impurity region formed in a semiconductor substrate;
This is a method for manufacturing a semiconductor memory device including a capacitor connected to a conductive layer. And the following manufacturing process is provided.

First, a first insulating layer is formed on a main surface of a semiconductor substrate, and a predetermined region is opened. Next, the first surface is formed on the entire surface of the semiconductor substrate.
A conductive layer is formed. Then, a gate opening is formed in a predetermined region of the first conductive layer. Further, a second conductive layer and a second insulating layer are formed on the surface of the first conductive layer and in the gate opening. Further, the second conductive layer and the second insulating layer are patterned into a predetermined shape to form a gate electrode of the transistor. Further, a third insulating layer is formed on the side wall of the gate electrode. Further, impurities are introduced into the first conductive layer, and the impurities contained in the first conductive layer are diffused into the main surface of the semiconductor substrate. Thereafter, a lower electrode layer of the capacitor is formed on the surface of the first conductive layer and on the surfaces of the second and third insulating layers. Further, a dielectric layer is formed on the surface of the lower electrode layer. Further, an upper electrode layer is formed on the surface of the dielectric layer.

The invention according to claim 2 is a method for manufacturing a semiconductor memory device including a transistor having a conductive layer connected to an impurity region formed in a semiconductor substrate, and a capacitor connected to the conductive layer. It has a process.

First, a first insulating layer is formed on a main surface of a semiconductor substrate, and a predetermined region is opened. Next, the first surface is formed on the entire surface of the semiconductor substrate.
A conductive layer is formed. Further, a separation opening is formed in a predetermined region of the first conductive layer. Then, an insulating layer for isolation is formed on the surface of the first conductive layer and inside the opening. And
The isolation insulating layer is etched back and the isolation insulating layer is buried inside the isolation opening. Thereafter, a gate opening is formed in a predetermined region of the first conductive layer. Further, a second conductive layer and a second insulating layer are formed on the surface of the first conductive layer and in the gate opening. Further, the second conductive layer and the second insulating layer are patterned into a predetermined shape to form a gate electrode of the transistor. Further, a third insulating layer is formed on the side wall of the gate electrode. After that, an impurity is introduced into the first conductive layer, and the impurity contained in the first conductive layer is diffused into the main surface of the semiconductor substrate. Then, the lower electrode layer of the capacitor is formed on the surface of the first conductive layer and on the surfaces of the second and third insulating layers. Further, a dielectric layer is formed on the surface of the lower electrode layer. Further, an upper electrode layer is formed on the surface of the dielectric layer.

[Operation] In the semiconductor memory device manufactured according to the first aspect of the present invention, the impurity region of the transfer gate transistor and the first electrode layer of the capacitor can be connected via the conductive layer. Since the impurity region is formed by thermally diffusing the impurity from the conductive layer, there is no occurrence of a positioning error of the mutual connection position. Therefore, the diffusion width of the impurity region can be reduced, and the transistor structure can be miniaturized.

In the semiconductor memory device manufactured according to the second aspect of the present invention, it is possible to form a structure in which a buried insulating layer is formed between adjacent memory cells to insulate and isolate each other. Therefore, the width of the separation region does not increase during the manufacturing process, and a fine separation structure can be realized.

According to the method for manufacturing a semiconductor memory device according to the first and second aspects, it is possible to manufacture a semiconductor memory device having a highly integrated memory cell structure using a conventionally known technique.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a partial plan view of a memory cell array of a DRAM according to an embodiment of the present invention. Also, FIG.
FIG. 3 is a sectional structural view taken along a section line II-II in the figure, and FIG. 3 is a sectional structural view taken along a section line III-III in the same manner. Referring to FIG. 1 to FIG. 3, the memory cell includes one transfer gate transistor 10 and one capacitor 20. The transfer gate transistor 10 has a so-called PSD transistor structure. The feature of this transistor structure is that it has source / drain electrode layers 15 and 15 made of polycrystalline silicon on the surface of the p-type semiconductor substrate 1. Source / drain electrode layers 15, 15 are partially connected to the surface of p-type silicon substrate 1, and n-type impurity regions 13, 13 are formed on the surface of p-type silicon substrate 1 along the connection surface. P located between a pair of n-type impurity regions 13 and 13
A gate electrode (word line) 11a is formed in a region on the surface of the silicon substrate 1 with a gate insulating film 12 interposed therebetween. The gate electrode 11a made of polycrystalline silicon has a cross-sectional shape in which both ends of the gate electrode 11a run over the source / drain electrode layers 15, 15. In regions other than the connection region between the source / drain electrode layers 15 and 15 and the n-type impurity regions 13 and 13,
The source / drain electrode layers 15 extend on the surface of the p-type silicon substrate 1 via an insulating layer 16. Gate electrode 11a
And an insulating layer on the surface of the source / drain electrode layers 15 and 15
Covered with 14. In the insulating layer 14, the contact 6 of the capacitor is formed. And capacitor 20
The lower electrode 21 is formed on the surface of the insulating layer 14 and is connected to one side of the source / drain electrode layer 15 via the contact portion 6. On the surface of the lower electrode 21, a dielectric layer 22 made of a nitride film, an oxide film, or the like is formed. Further, the surface of the dielectric layer 22 is covered with the upper electrode 23. On one surface of the source / drain electrode layer 15, a word line 11b whose periphery is covered with an insulating layer 14 is formed. Further, a bit line (not shown) is connected to the other side of the source / drain electrode layer 15. The insulation isolation between adjacent memory cells is constituted by a buried isolation layer 4 in which an oxide film or the like is embedded between the source / drain electrode layers 15. This separation layer 4 is formed at a low temperature as described later.
It is formed using a CVD method. And the embedded separation layer 4
Is defined by the width of the opening formed in the source / drain electrode layer 15. Therefore, the formation of a bird's beak unlike the LOCOS isolation film 2 does not occur, so that the isolation region can be miniaturized. The n-type impurity regions 13 of the transfer gate transistor 10 are formed to have a fine diffusion width by using a part of the source / drain electrode 15. Therefore, in response to a soft error, for example, electrons generated in the substrate by the α-particles are suppressed from entering the n-type impurity region 13, and the occurrence of the soft error is reduced. In addition, the lower p of the buried isolation layer 4
On the surface of the type semiconductor substrate 1, a channel stopper 3 composed of a p ⁺ impurity region having a higher concentration than the substrate is formed. However, since the buried isolation layer 4 is formed by a low-temperature process, the channel stopper 3 is prevented from seeping into the channel region 17. Therefore, the occurrence of the narrow channel effect can also be suppressed.

FIG. 4 is a schematic plan view of a memory cell array according to the present invention, and FIG. 5 is a schematic plan view of a conventional memory cell array. The features of the present invention can be understood with reference to these drawings. If the arrangement intervals and the occupied areas of the capacitors 10 are set to be equal, the active region width Lw of the transfer gate transistor covered with the buried isolation layer 4 according to the present invention shown in FIG. Conventional
It is clear that the active region is formed to be larger than the width Lw of the active region covered by the LOCOS isolation film 2. In other words, if the area of the active region of the transfer gate transistor is set as in the conventional case, the width of the isolation region between adjacent memory cells can be reduced as compared with the conventional case. This allows DRAM
The high integration of the memory cell array can be realized.

Next, a method of manufacturing the DRAM memory cell array of the present invention shown in FIG. 2 will be described. Figures 6A to 6K
The figure is a manufacturing process sectional view showing the sectional structure of the memory cell shown in FIG. 2 according to its manufacturing process.

First, referring to FIG. 6A, CV is applied to the surface of p-type silicon substrate 1.
An insulating layer 16a such as a silicon oxide film is deposited by using the D method.

Next, referring to FIG. 6B, a predetermined region of insulating layer 16a is selectively removed by etching, and then a polycrystalline silicon layer 15a is deposited to a thickness of about 1000 to 5000 ° by using a CVD method.

Further, referring to FIG. 6C, a resist pattern 30 is formed on the polycrystalline silicon layer 15a.
Polysilicon layer 15a and insulating layer 16a using 30 as a mask
Is removed by etching. By this etching, an opening to be an isolation region is formed at a predetermined position in the polycrystalline silicon layer 15a. Further, 1 × boron ions are applied to the surface of the p-type silicon substrate 1 using the resist pattern 30 or the like as a mask.
Ion implantation is performed at about 10 ¹² to 1 × 10 ¹⁴ / cm ² . The channel stopper 3 is formed by this ion implantation.

Further, referring to FIG. 6D, after removing the resist pattern 30, a silicon oxide film 4a is deposited at a low temperature of 850 ° C. or lower by using a CVD method.

Further, referring to FIG. 6E, oxide film 4a is etched back to form buried isolation layer 4 in the isolation opening in polycrystalline silicon layer 15a. The end point of the etch back may be determined in a state where oxide film 4a is slightly left on the surface of polycrystalline silicon layer 15a.

Further, referring to FIG. 6F, after an insulating layer 33 is formed on the surface of the polycrystalline silicon layer 15a and the buried isolation layer 4, the insulating layer 33 and the polycrystalline silicon layer 15a are subjected to photolithography and etching. An opening is formed in a predetermined region by using the same. Then, impurity ions 32 for adjusting the threshold voltage of the transfer gate transistor are ion-implanted into the surface of the p-type silicon substrate 1 exposed inside the opening.

Further, as shown in FIG. 6G, a gate insulating film 12 having a thickness of about 50 to 250 ° is formed inside the opening provided in the polycrystalline silicon layer 15 by using a thermal oxidation method. Thereafter, the doped polysilicon layer into which the impurities are introduced by using the CVD method is
Then, an insulating layer 14a is deposited on the surface. Then, the insulating layer 14a and the doped polysilicon layer are patterned into a predetermined shape by using a photolithography method and an etching method to form a gate electrode 11a and a word line 11b.

Further, referring to FIG. 6I, after an insulating film is deposited over the entire surface of p-type silicon substrate 1, anisotropic etching is performed to leave an insulating layer only on the side walls of gate electrode 11a and word line 11b. Thereby, the periphery of the gate electrode 11a and the word line 11b is covered with the insulating layer 14. Thereafter, impurity ions 34 such as phosphorus (P) or arsenic (As) are implanted into the polycrystalline silicon layer 15.

Further, referring to FIG. 6J, the temperature is 850 to 950 ° C., 30 minutes to
A heat treatment is performed for about 2 hours to thermally diffuse the impurity ions introduced into the polycrystalline silicon layer 15 to the surface of the p-type silicon substrate 1. As a result, the transfer gate transistor n
Formed impurity regions 13 are formed. Then, after depositing a polycrystalline silicon layer on the entire surface, it is patterned into a predetermined shape. Thereby, the lower electrode 21 of the capacitor is formed.

Further, referring to FIG. 6K, a nitride film 22 is formed on the entire surface of p-type silicon substrate 1 to a thickness of about 50 to 200 °. Further, a polycrystalline silicon layer 23 is formed on the
Is formed. Then, after covering the surface of the semiconductor substrate 1 with a thick interlayer insulating layer, a contact hole is formed at a predetermined position, and the polysilicon layer 15 is formed through the contact hole.
Is formed (not shown).

In the above manufacturing method, the diffusion width of the n-type impurity regions 13 of the transfer gate transistor 10 is determined by the contact area between the source / drain electrode layer 15 and the p-type semiconductor substrate 1. The positional relationship between the two is determined without using an alignment process such as mask alignment. Therefore, the diffusion width of the n-type impurity region 13 can be formed finer than the conventional one. Furthermore, the embedded separation layer 4
Is formed by a process at a lower temperature than the separation film 2 by the conventional LOCOS method. Therefore, the diffusion of boron ions constituting the channel stopper 3 can be suppressed to a minute area. Therefore, a narrow channel effect caused by the channel stopper seeping into the channel region of the transistor can be suppressed.

In the above embodiment, an example using a p-type semiconductor substrate has been described. However, the present invention can be applied to a device using an n-type semiconductor substrate.

[Effects of the Invention] As described above, by using the method for manufacturing a semiconductor memory device according to the present invention, a so-called PSD transistor having a conductive layer for an impurity region formed on a semiconductor substrate as a transfer gate transistor By employing a structure and forming a buried isolation layer in which the conductive layers are buried with an insulating film as an element isolation structure, high integration of a semiconductor memory device can be realized through miniaturization of an element isolation region. . Further, by forming the impurity region using the conductive layer used for the transfer gate transistor, soft error resistance can be improved.

[Brief description of the drawings]

FIG. 1 is a partial plan view of a memory cell array of a DRAM according to an embodiment of the present invention. FIG. 2 is a sectional view taken along a line II-II in FIG. 1, and FIG. 3 is a sectional view taken along a line III-III in FIG. FIG. FIG. 4 is a schematic plan view of the memory cell array shown in FIG. 1, and FIG. 5 is a plan view of a conventional DRAM memory cell corresponding to FIG. It is a schematic diagram. Figure 6A,
6B, 6C, 6D, 6E, 6F, 6G,
FIG. 6H, FIG. 6I, FIG. 6J, and FIG. 6K are manufacturing process sectional views sequentially showing the manufacturing process of the memory cell shown in FIG. FIG. 7 is a partial plan structure diagram of a conventional DRAM memory cell array. FIG. 8 is a sectional view taken along the line VIII- in FIG.
FIG. 9 is a cross-sectional structural view from a direction along VIII, and FIG.
FIG. 9 is a cross-sectional structure view of the same taken along a cutting line IX-IX. FIG. 10 is an equivalent circuit diagram of the memory cell array.
FIG. 11 is a sectional structural view for explaining a soft error phenomenon of the memory cell shown in FIG. Fig. 12A, 12B
FIG. 12, FIG. 12C, FIG. 12D, and FIG. 12E are manufacturing process cross-sectional views sequentially showing the manufacturing process of a conventional semiconductor device having a buried isolation layer. In the figure, 1 is a semiconductor substrate, 3 is a channel stopper,
4 is a buried isolation layer, 10 is a transfer gate transistor, 11a and 11b are gate electrodes (word lines), 12 is a gate insulating film, 13 is an n-type impurity region, 15 is a source / drain electrode layer, 20 is a capacitor, 21 Is a lower electrode, 22 is a dielectric film, 23
Indicates an upper electrode. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device, comprising: a transistor having a conductive layer connected to an impurity region formed in a semiconductor substrate; and a capacitor connected to the conductive layer. Forming a first insulating layer on the main surface and opening a predetermined region; forming a first conductive layer on the entire surface of the semiconductor substrate; opening a predetermined region of the first conductive layer Forming a second conductive layer and a second insulating layer on the surface of the first conductive layer and in the opening; and forming the second conductive layer and the second insulating layer in a predetermined shape. Forming a gate electrode of the transistor; forming a third insulating layer on sidewalls of the gate electrode; introducing an impurity into the first conductive layer; Impurities contained inside the layer Diffusing the capacitor into a main surface of the semiconductor substrate; forming a lower electrode layer of the capacitor on the surface of the first conductive layer and on the surfaces of the second and third insulating layers; A method for manufacturing a semiconductor memory device, comprising: a step of forming a dielectric layer on a surface; and a step of forming an upper electrode layer on a surface of the dielectric layer. 2. A method of manufacturing a semiconductor memory device, comprising: a transistor having a conductive layer connected to an impurity region formed in a semiconductor substrate; and a capacitor connected to the conductive layer. Forming a first insulating layer on the main surface and opening a predetermined region; forming a first conductive layer over the entire surface of the semiconductor substrate; separating opening in a predetermined region of the first conductive layer Forming a portion; forming a separation insulating layer on the surface of the first conductive layer and inside the opening; and etching back the separation insulating layer to form the separation inside the separation opening. Embedding an insulating layer for isolation; forming a gate opening in a predetermined region of the first conductive layer; and forming a second conductive layer on a surface of the first conductive layer and in the gate opening. Forming a second insulating layer; Patterning a second conductive layer and the second insulating layer into a predetermined shape to form a gate electrode of the transistor; forming a third insulating layer on sidewalls of the gate electrode; Introducing an impurity into the inside of the semiconductor substrate; diffusing an impurity contained in the first conductive layer into a main surface of the semiconductor substrate; on the surface of the first conductive layer and the second and third insulation layers; Forming a lower electrode layer of the capacitor on the surface of the layer; forming a dielectric layer on the surface of the lower electrode layer; and forming an upper electrode layer on the surface of the dielectric layer. A method for manufacturing a semiconductor memory device, comprising: