JP2862112B2 - High performance bus system and on-chip transceiver module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission channel, and more particularly to a high-speed multi-drop bus system.

[0002]

2. Description of the Related Art It is well known to use a multi-drop bus system for data transmission. The conventional multi-drop bus system has a bus structure in which a plurality of drivers and receivers are connected. One example of a conventional bus system is disclosed in U.S. Pat. No. 4,596,940. According to this patent specification, the system consists of a differential bus,
Both ends 20, 21 are terminated with a resistance equivalent to the characteristic impedance of the bus. Neither side of the differential bus is directly connected to the active power supply voltage Vcc or Vee via a passive element. Instead, each side of the bus will sink when current flows out of one side (sink).
It is driven by one of the plurality of drivers so that current flows into the other side (source).

[0003] One of the problems in the above-mentioned US patents is a problem with other conventional bus systems. US Patent No. 45
Conventional bus structures, including the 96940 bus structure, are susceptible to common mode noise and switching noise and therefore cannot be used in high speed systems where overall system performance is limited by noise. This problem is addressed by US Pat.
This is due to the fact that both sides of the bus of No. 40 and other conventional buses are driven by true differential current sink drivers. In this type of driver, current sinking and sourcing occurs simultaneously on each side of the bus. Such simultaneous sinking and sourcing requires simultaneous switching on both sides of the bus, which introduces noise into the system. A similar problem arises in conventional unbalanced (single-ended) bus designs, including the proposed future bus concept, due to the large simultaneous switching currents.

[0004] In the conventional multi-drop bus system, noise also occurs when the bus ends are not sufficient. In particular, conventional buses are terminated at both ends with resistors equivalent to the characteristic impedance of the bus. This type of termination is referred to as an "odd mode" termination. According to the end of this form,
The "common mode" signals directed to this bus "ring" for an excessive amount of time, causing problems with signal integrity, EMI and common mode range.

At present, conventional bus systems are designed for relatively low to medium speed applications. As new digital systems are developed, they are expected to achieve better performance than existing (ie, conventional) systems at the lowest cost. This “performance” includes characteristics such as speed, function, and reliability. There is an increasing demand for digital systems that exhibit high availability and high reliability. This requires a fault-tolerant, hot-pluggable bus (ie, a bus that supports live insertion of adapter cards).

[0006] There is a well-known trend toward higher data rates in digital systems. Higher data rates require higher clock frequencies and faster signal transitions. One way to keep the clock speed as low as possible while improving the effective throughput of the digital system is to increase the bus width, i.e., to send many bits in parallel. Bus widths exceeding 100 bits are not uncommon. Clock speeds are still increasing with wider bus widths.

[0007]

The bus system (ie, the bus and its associated drivers and receivers) must be carefully designed to meet a set of requirements resulting from improved performance, functionality and cost. These requirements present several challenges that the bus system must simultaneously and optimally solve:

[0008] 1. The speed bit transfer must be completed within one clock cycle time. That is, one data bit must be transmitted from the input of the transmit driver to the intended output of the receiver via the bus within one clock cycle.

Therefore, there is a problem of "time budget" that must be satisfied, including the following items.

Propagation delay of driver circuit Propagation delay of signal passing through the bus through connector Connector settling time of reflection Propagation delay of receiver circuit The design clock cycle of the present invention is 25 ns. This is an ambitious goal given the physical length of the bus and the number of card slots.

2. Noise In addition to the noise problem described above, if the noise margin is excessive or inappropriate, data integrity issues can cause performance degradation. This is because the clock speed must be reduced in order to avoid data integrity problems. There are several types of noise that can occur in a bus system:

[0012] Coupling noise that occurs when a signal on one conductor in a bus induces unwanted signals on an adjacent conductor on that bus. Switching noise caused when current pulses resulting from multiple bits changing state at the same time induce unwanted signals on the power or ground conductors, which in turn induce erroneous data signals at the output of the driver or receiver. EMI generated when the bus system emits abnormal radiation in a certain frequency band or excessively responds to ambient electromagnetic radiation
/ EMC noise. . -Reflection noise that occurs when reflections due to bus impedance mismatches distort the data signal at the input of the receiver.
Impedance mismatch occurs at the end of the bus due to improper termination, but also at card slots.

3. Power consumption The power consumption of the driver must be minimized for the following reasons. -To maximize the achievable mounting density. -To minimize the cost of power supplied to the bus system.・ To maximize reliability. -To allow components to cool to a reasonable operating temperature;

At the same time, the driver must be able to drive a bus impedance of about 15 to 20Ω. This drive capability is necessary because the time budgets described above may not allow the use of reflections from the bus termination to generate the proper signal at the receiver input.

4. Mounting Density Drivers and receivers must be mounted at an optimum density. If the density is too high, problems of coupling noise (due to long signal lines), switching noise and power consumption are exacerbated. Low density increases both component and manufacturing costs, while reducing system reliability.

5. Fault Tolerance and Hot Pluggability Driver and receiver circuits must be designed so that they can be inserted into an active bus without disturbing ongoing data transfers. Furthermore, if a power failure occurs on a particular adapter card, the driver and receiver on that card must not load the bus, since that card can no longer function.

6. Self Diagnostic Capability The transceiver must support operation in "wrap" mode for diagnostics. In lap mode, the driver and receiver are activated simultaneously. Thus, the card can read data from the bus while simultaneously outputting data to the bus. This confirms the functionality of the transceiver.

None of the conventional bus systems solves the above problems simultaneously and in an optimal manner.

Furthermore, conventional circuit components used in bus design are not suitable. Several types of conventional components were considered, but were abandoned because it proved difficult to meet system requirements. The types of circuits that can be used have been divided into three broad categories: open collectors, including TTL and future bus, push-pull, and emitter follower ECL. Generally, conventional usable components have been eliminated for the following reasons.

1. The inability to drive the current required to switch the bus incidentally (especially ECL requires an output voltage swing of about 800 mV, and the driver is generally limited to 25 mA, less than the required 53 mA).

2. Desired logic functions without using multiple packages and thereby excessive stub capacitance (especially separate T
TTL input and TTL output and separate drive and receive clocks).

3. Large output pin capacitance and therefore large backplane impedance variation.

4. Improper delay performance (including Futurebus).

5. Simultaneous switching noise (especially 100
Future bus with mA driver).

6. Coupling noise with large signal swings and uncontrolled, unspecified edge speeds (especially TTL).

7. High parts cost, especially Futurebus parts cost about 54 yen (US $ 0.60) per bit, total bus driver cost about 6030 per card
(US $ 67) (Target cost is about 450
0 yen (US $ 50)).

8. Low output impedance causing active driver signal reflection. This is true for all circuit types except for current sources / sinks described below.

[0028] Other subtle problems have arisen in the initial investigation of various circuit types, including:

The standard ECL gate does not completely shut off when disabled. This improves switching speed, but limits the ability to "dot" the output due to the finite quiescent current. Unexpected effects occur due to current sharing between circuits, which significantly affects delay performance.

The future bus requires a large current voltage regulator for a 2 volt terminated power supply that can handle large fast transient current fluctuations when the driver is switched, but evidence that such a circuit exists There is no.

From the above, it is an object of the present invention to provide a bus system with higher efficiency and higher performance than previously possible.

[0032]

In order to achieve the above object, a bus system according to the present invention includes a relatively low impedance multidrop transmission medium (bus) and a plurality of hybrid transceivers connected thereto.

In particular, the low impedance bus includes a plurality of conductors, each having a value selected to terminate both odd (differential) mode and even (common) mode signals on the bus. Terminate each end with a resistor.

[0034] The hybrid transceiver includes a driver and a receiver. The receiver is a differential comparator receiver biased to a known output voltage level. This bias causes the output of the receiver to assume some preferred state when there is no input signal.

Similarly, the driver includes a pseudo-differential current sink comprised of a current steering current sink that sinks a predetermined amount of current from either side of the differential bus. When current is sinked from one side of the bus, the other side is turned off. Data is pipelined to the driver and from the receiver by a double latch mechanism.

Two non-overlapping clock signals ensure proper staging of data to the driver and from the receiver. These clock signals can be operatively coupled such that data passes through the latch circuit. Separate "enable" signals control the driver and receiver. A wrap mode in which the driver output is sent to its receiver is achieved by activating these enable signals simultaneously.

[0037]

FIG. 1 is a diagram showing the overall configuration of a bus system according to the present invention. This bus system is a communication wire BUS
Wide (100 bits) indicated by Q and -BUSQ
Includes differential bus. In the drawings, the inversion (-) is indicated by a superscript bar. This bus is terminated to a given terminal voltage level (VT) via impedances Z1 and Z2. The impedances Z1 and Z2 are chosen to terminate both odd and even propagated signal modes. In particular,
The value of resistor RO is set to half the odd mode impedance of the bus. The series circuit of the two parallel resistors RO and RE is chosen equal to the even mode impedance of the bus. Thus, the odd mode signals and even mode signals propagating through the bus system are properly terminated without signal reflection on the bus system.

A plurality of connectors 10, 12,..., N are connected to a plurality of selected locations along the bus. These connectors form a multidrop point to which transceivers 10 ', 1' (described in detail below), respectively.
2 ', 14',... N 'are connected. The transceiver can be connected using an appropriate commercially available connector. The details of these connectors are not described here because they are well known, but Dupont Metral
) Or a connector such as AMP HDI.

In FIG. 1, each transceiver has a driver D. The driver D receives a signal at its input terminal and outputs it to the bus for transmission to another transceiver connected to the bus. The receiver R in each transceiver package receives a signal from the bus and sends it to its output. This signal is then sent to the device (not shown) to which the transceiver is connected on the bus. For testing, an output signal from a driver in one transceiver to the bus can be received by a receiver in the same transceiver. This wraparound feature allows the transceiver to be tested for its operability before being connected to the bus.

FIG. 2 is a block diagram of a transceiver according to the present invention. Each transceiver has the same internal configuration, so the following description applies to any transceiver shown in FIG. The transceiver of FIG. 2 illustrates a single bit data path. In view of the foregoing problems, a packaging density of 5 bits per package appears to be optimal. 3 and 4 are block diagrams of modules having this preferred bit density. This module comprises five single bit transceivers SB1, SB2, SB3, SB4 and SB interconnected to a common control logic block 32.
5 is included. Details of the single bit and control logic blocks are described below. Control logic block 32 receives (buffers) clock signals -C1 and -C2 and control signals DOE and ROE and converts them to differential logic level signals for driving a single bit transceiver. The package chosen as optimal is a 28-pin plastic chip carrier (PCC) surface mount package to minimize trace length and lead inductance.
Other packaging densities may be desirable within the scope of the present invention, depending on the application.

In FIG. 2, the small black rectangular pads shown at the ends of each line indicate the input / output contacts or nodes of the chip (similarly in FIGS. 3 and 4). Data input signal DR-IN and receiver output signal RCV-OUT
Is a standard transistor-to-transistor logic (TTL) level in this embodiment. Clock signal -C1,-
C2, the driver output enable signal DOE and the receiver output enable signal ROE are at a positive emic combination logic (PECL) level in this embodiment. These voltage levels are approximately 3.2 volts for logic "0" and 4.1 volts for logic "1". Other levels can be used for all inputs and outputs, depending on the application. The relationship between the above signals and the functions they service will now be described.

As mentioned above, each transceiver includes a driver section and a receiver section. The receiver section includes a receiver (RCV) 16 having an input connected to the -BUSQ side and the BUSQ side of the bus. An output terminal of the receiver 16 is connected to a latch device 18 including latches L3 and L4. The latch device 18 transfers the data from the receiver 16 by pipeline to the signal conversion circuit CV2. When activated by the signal ROE, the signal conversion circuit CV2 outputs the differential ECL input signal to the line RCV-.
Convert to unbalanced termination TTL output signal on OUT and level shift. The signal conversion circuit CV2 may be a commercially available one, and converts a balanced termination signal into an unbalanced termination signal. For example, a suitable module is one bit of Motorola MCIOH350.

Similarly, receiver 16 is a differential input / differential output voltage comparator similar in function to National Semiconductor LM360.

In FIG. 2, drive data is provided to the chip on the DR-IN line using the TTL signal level. This data is converted into differential data by the signal conversion circuit CV1 and applied to the latch L1. The falling edge of the signal on the C1DI line clocks this data to the input of latch L1, and the falling edge of the signal on the C2DI line clocks it to the input of latch L2. Latch L
2 provides the data to the input of driver 20. The driver 20 (details will be described later) uses a differential bus (-BUSQ and B
USQ) is a custom designed circuit that provides the proper interface.

The same applies to the path of the received signal from the bus.
Receiver 16 is a differential comparator to which a small amount of input offset voltage is applied to keep its output in a known state when there is no signal on the bus. The received output signal is applied to the input of latch L3. This latch is
At the falling edge of C1RI, the received data is latched and applied to the input of latch L4. Similarly, data is clocked at the input of the conversion circuit CV2 at the falling edge of the -C2RI signal. Conversion circuit CV2 converts the ECL differential signal to a TTL unbalanced termination output on pin RCV-OUT. The circuit architecture used here keeps the data as differential (ECL) as possible on the chip. This technology provides the highest speed, lowest power, and minimizes noise emissions to other circuits (both on-chip and off-chip). Means are also provided for simultaneously disabling all drivers and / or receivers on the chip. The receiver is disabled by the signal on line ROEI, thereby turning off the output stage of the conversion circuit CV2 (high impedance output) so that neither the up level nor the down level is active. The driver is similarly turned off by the DOE signal line. P
GMA control circuit 15 (see FIG. 8) is a custom circuit (described in detail below), which sets the controller reference current for all five drivers on the chip. DOE
The signal line is used as an input to the control circuit 15 to turn off (or turn on) the reference current. Thus, these drivers are disabled simultaneously when the DOE line goes inactive. In this embodiment, the inactivity of the DOE line is the ECL down level. To minimize on-chip delay, the two clock signals -C1 and -C2 and the enable signals ROE and DOE are used as differential signals on the chip.

FIG. 8 is a diagram showing a functional relationship between the PGMA control circuit 15 and the driver 20. Driver 20 includes a current source 24 '. The current source 24 'is connected to each side of the differential bus -BUSQ and BUSQ by individually activatable switches SW26' and SW28 '.
When enabled by a signal on the output enable signal line (DOE), the PGMA control circuit 15 provides a fixed amount of current ISRC that is sunk from the side of the bus connected to the current source 24 'through one of the switches. Is set. Therefore, by using this pseudo differential switch and control circuit, current is sinked only from one side of the bus without disturbing the other side.

FIG. 6 shows details of the driver 20. Similar elements in FIGS. 6 and 8 are indicated by the same symbols or numbers. This circuit includes differential switches 26 'and 2 respectively.
8 'includes a current source 24' interconnected to BUSQ and -BUSQ. The differential switch 26 'has a resistor RIA,
Transistors Q3, is connected to the IN-side and supply V _CCD and V _EED of the input differential signals by the resistors RB1 and R1. The emitter of transistor Q3 is connected by transistor Q4 to voltage node V20 (described in detail below) and to power supply V _EED . Similarly, the differential switch 28 'is connected to the resistor R4
A, the transistor Q8, are connected to INN side and the power source V _CCD and V _EED of the differential input signal by the resistor RB2 and R4. The emitter of the transistor Q8 is the transistor Q8.
9 and the resistor R3, the voltage node V20 and the power supply V _EED
Connected to.

In FIG. 6, the differential switches 26 ', 2'
8 'is a differential transistor pair Q5, Q5A, Q6, Q6A
including. The collectors of these transistors are bus (BU)
SQ, -BUSQ). Driver is DO
When activated via the E line (FIG. 3), a reference voltage (VIPGM) is provided by a PGMA control circuit 15 (described in detail below). Then, a certain amount of current IS
RC is set up at the collectors of transistors Q7 and Q7A. In this embodiment, the magnitude of the current ISRC flowing through the collector electrodes of the transistors Q7 and Q7A is about 16 mA, respectively. Other current ratios can be drawn from current source 24 'within the scope of the present invention. The driver output current is switched to the BUSQ or -BUSQ node on either side of the bus depending on the input data that appears differentially at the circuit inputs (IN and INN). IN and INN
The upper input signal is level-shifted by a resistor string composed of resistors R1, R1A, R4 and R4A and applied to the bases of transistors Q3 and Q8, respectively. Transistors Q3 and Q8 buffer this input signal and provide it to the bases of transistors Q5 and Q6, respectively. As a result, the differential input voltages (IN, INN) are given to the transistors Q5, Q5A, Q6, and Q6A functioning as current switching devices. Schottky diodes D1 and D2 are connected between each side of the bus to limit maximum signal swing and somewhat attenuate noise that may be coupled into the bus. Resistors RB1, RB2 and RS provide high frequency compensation during switching transitions. Transistors Q4 and Q9 and resistor R2
And R3 provide a small bias current for transistors Q3 and Q8 as a buffer device. This bias current is derived from the voltage at node V20.

Preferably, V20 is a reference voltage provided by an on-chip bandgap reference circuit. This circuit is functionally a National Semiconductor LN
Similar to 113 and LN185 reference diode devices.

FIG. 7 shows details of the PGMA control circuit 15. The function of the PGMA control circuit 15 is to set the controller reference current for all (five) drivers on the chip. The PGMA control circuit 15 generates a reference current generator 30 (Q3 ', V2
0, R14). The reference current generator 30 includes elements Q2 ', R9, Q8' and R1
0 connected to the current mirror. This current mirror is connected by a current gain circuit 34 to the collector electrode of reference transistor Q5 '. The base of the transistor Q5 'is connected to a signal line VIP for setting a reference current of the driver.
Connected to GM. The emitter electrode of the reference transistor Q5 'is connected to elements Q7', Q9 ', Q10', D11, R1 '.
And a high-speed turn-on / off circuit formed by R7 '.

For proper operation, the circuit elements of FIG.
Tightly matched with the circuit elements of This matching allows the correct amount of current to flow on either side of the differential bus. In this embodiment, the reference current is given by the bandgap voltage of the node V20. Transistors Q2 'and Q8' and resistors R9 and R10 form a gain-2 current mirror. This produces a current of about 2 mA at the collector of transistor Q8 '. Elements Q1 ', Q4', R8, R1
2, R3 and R11 are used to provide additional current gain for PNP current mirror elements Q2 'and Q8'. Circuits 32 and 34 are used to compensate for the relatively low beta (β) of lateral PNP transistors Q2 'and Q8'. A 2 mA current flowing through the collector electrode of transistor Q8 'is supplied to reference transistor Q5'. The exact voltage drop occurs at resistor R4, which connects the emitter of transistor Q5 'to voltage source V _EED . Therefore, the base of the transistor Q5 (node VIP)
GM) is a reference node for setting up a reference current for each of the five drivers in the transceiver module.

As mentioned above, the elements of FIG. 7 are closely matched with the elements of FIG. 6 to facilitate the desired operation of the circuit.
Therefore, in each driver, the resistance R4 is equal to the ratio (16).
0Ω / 40Ω) are transistors Q7 and Q7A (FIG. 6)
Are matched with the resistors R2A and R2B (FIG. 6) so as to quadruple the current of the emitters of FIG. Further, the transistor Q7
And Q7A (FIG. 6) are also set to be four times that of transistor Q5 (FIG. 6) to improve the accuracy of the current source. Therefore, the differential drive circuits (Q5, Q5A, Q5
6. The total current to the emitter of Q6A) is 16 mA.
As mentioned above, these values are only examples and do not limit the scope of the present invention.

Further, in FIG. 7, the transistor Q6 is
It is used as a buffer transistor (current gain) to minimize the loading effect of multiple drivers on a single reference circuit. Resistors R6 and R13 together with capacitor C1 provide frequency compensation for this reference circuit. DOE
The signal (FIG. 3) is transmitted by the control logic block 32 to the differential signal V.
It is converted to EN and VENI (FIG. 7). These differential signals VEN and VENI are applied to resistors R1 'and R7'. As a result, substantially equal currents are set in transistors Q9 'and Q10'. Since transistor Q10 'is diode-connected, the collector voltage of transistor Q9' has a value one diode drop higher than the reference point set by the anode of Schottky diode D11. This means that the base of transistor Q7 '
It means that the transistor Q7 'is quickly turned on or off (ie, turned on or off) within a voltage range required to turn on or off the transistor Q7 very quickly. Transistor Q7 ', when turned on by a drop in VEN and a concomitant rise in VENI, shunts the reference current set by the current mirror to D11. As a result, current is removed from the reference circuit formed by elements Q5 'and R4, thereby causing the reference node VI
The voltage of the PGM drops. Therefore, all five drivers on the chip are turned off. Capacitor C2
Is used to promote the discharge of the collector node of transistor Q7 'to speed up the operation of this circuit. Resistor R5 is used as a bleeder resistor to further promote its discharge when node VIPGM is disabled.

[0054]

The advantages of the device described above are as follows.

1) Maximum insensitivity to noise from other signal lines and reduced loop area for EMI radiation.

2) The ability of the unbalanced termination ECL to operate at half the required signal swing, and E
Mitigation of the problem of MI and coupling noise (since the important amount for reception given a certain noise margin is the relative difference between signal level and reference). Since the second signal line acts as a reference in the differential line, its required signal swing may be half that of the unbalanced termination line.

3) The conventional voltage comparator can be used as a receiver having an optimum noise margin unaffected by fluctuations in the card power supply voltage (since no reference voltage is required).

4) Since only the collector of the transistor is connected to the bus, the device capacity can be minimized. The use of a low current drive level (16 mA in this case) allows the use of small devices and lower collector-substrate capacitance values. This reduces stub capacity and minimizes bus impedance variations due to additional card loading.

5) Current mode output provides high output impedance. This has the following two advantages over a voltage-driven circuit configuration.

A) Signals transmitted on the bus are free of reflections from impedance mismatches that may be present in the case of voltage mode drivers that appear to be very low impedance from the bus.

B) Current mode drivers are inherently hot-pluggable because they only drain or flow current when enabled.

6) The power supply and ground current during signal transmission are constant, and simultaneous switching noise is eliminated except during the enabling and disabling of the driver. This feature significantly reduces both system noise and EMI.

7) Constant termination current when enabled. This is important because the terminating resistors to be placed on each card that can be inserted into the end slots of the backplane are powered by the DC-DC converter on the replacement (control) card. Thus, the requirement of large transient currents, which depends on the data on the termination impedance, causes serious noise problems, if any.

8) By mounting 5 bits on one chip, it is possible to achieve a compromise between increasing the packing density and reducing the stub length between the bus and the transceiver.

9) Separate driver and receiver enable inputs allow "wraparound" operation for diagnostics.

10) Protection of the bus against card failure (the bus can still function if the power supply or components on the card fail).

Thus, according to the present invention, a bus system with higher efficiency and higher performance than the conventional bus system can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a low impedance multi-drop bus according to the present invention.

FIG. 2 is a block diagram of a transceiver according to the present invention.

FIG. 3 is a block diagram of a first part of the transceiver module according to the present invention.

FIG. 4 is a block diagram of a second part of the transceiver module according to the present invention.

FIG. 5 is a diagram showing an interconnection relationship between FIGS. 3 and 4;

FIG. 6 is a circuit diagram showing an internal configuration of a driver.

FIG. 7 is a circuit diagram of a circuit that enables a driver to operate.

FIG. 8 is a functional diagram showing a relationship between a driver and a controller.

[Explanation of symbols]

 Z1, Z2 terminal impedance 10, 12, 14, N connector 14 reference current generator 10 ', 12', 14 ', N' transceiver 15 PGMA control circuit 16 receiver 18 latch device 20 driver 22 latch device 24 'current source 26' , 28 'switch 32 control logic block

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Robert, Joseph, Christopher North Carolina, United States, Chapel, Hill, Emory, Drive, 713 (72) Inventor Donald, Joseph, Dakosta, North Carolina, United States, Raleigh, Colony, Court, 7704 (72) Inventors Joseph, Curtis, Deepen Block, Raleigh, North Carolina, U.S.A., Stagwood, Drive, 4121 (72) Inventor Philip, Russell, Epley, R., North Carolina, Raleigh, Medfield, Rd. , 1714 (56) References JP-A-63-1211 (JP, A) JP-A-56-158554 (JP, A) JP-A-2-278594 (JP, A) JP-A-62-11322 (JP, A) JP-A-62-128 (JP, A) JP-A-55-5615 (JP, U)

Claims (2)

(57) [Claims] An on-chip transceiver module connected to the differential bus via a connector, wherein the on-chip transceiver module unbalances data to be output to the differential bus. First signal conversion means for receiving a signal from the outside of the chip and converting the signal into a differential data signal; a pair of differential switches, one of which is turned on and the other is turned off in response to the differential data signal; A differential driver including a current source for sinking a fixed amount of current from one side of the differential bus without disturbing the other side via the differential switch, and a differential signal from the differential bus. A second signal conversion means for converting the differential signal received by the differential receiver into an unbalanced termination signal and outputting the same to the outside of the chip; A high performance bus system, comprising: means for converting an external enable signal into a differential enable signal; and means for operating the differential driver in response to the differential enable signal. 2. An on-chip transceiver module used with a multi-drop differential bus, wherein data to be output to the differential bus is received from outside the chip in the form of an unbalanced termination signal and converted into a differential data signal. A pair of differential switches, one of which is turned on and the other is turned off in response to the differential data signal, and one side of the differential bus via the turned on differential switch. A differential driver including a current source for sinking a certain amount of current from the other side without disturbing the other side; a differential receiver receiving a differential signal from the differential bus; and a differential receiver receiving the differential signal. Second signal conversion means for converting the dynamic signal into an unbalanced termination signal and outputting the signal to the outside of the chip; and converting an enable signal from outside the chip to a differential enable signal. On-chip transceiver module, comprising: a means, a means for operating the differential driver in response to the differential enable signals.