CA2178846C - High speed bus transceiver with fault tolerant design for hot pluggable applications - Google Patents

Abstract

A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

Description

.

HIGH SPEED BUS TR~ 1 Vl~ll WITH FAULT TOLERA~iT DESIGN
FOR HOT pT.IIll~.AP~T.I~ APPLICATIONS
1. Field of the Iny~ntf on The present invention relates to data transmission channels in general and in particular to high speed multi-dropped bus sys tems .

2. Prior ~rt The use of multi-drop bus systems for transmitting data is well known in the prior art. A conventional multi-drop bus system consists of a bus structure to which a plurality of drivers and receivers are connected. An example of a prior art bus system is set forth in US Patent 4,596,940. According to the patent, the system consists of a differential bus with sides 20 and 21 terminating, at both ends, in a resistance which is equivalent to the characteristic i c~ n~e of the differential bu~. Neither side of the differential bus is coupled directly to either Vcc or Vee of the active supply voltage by passive components. Instead, each side of the bus is actively driven by one of a plurality of drivers so that as current is sinked from one side of the bus current is sourced into the other side.
One of the problems which plagues the above-referenced US
patent is typical of the problems experienced in other prior art bus systems. The prior art bus structure, including the bus structure in US Patent 4,596,940 is vulnerable to common mode and switching noises and as such cannot be used in high speed systems where noise limits overall system performance. The problem stems from the fact that a truly dif ferential current sink driver drives both sides of the bus of US Patent 4,596,940 and like prior art. With this type of driver, current is simultaneously sinked and sourced from opposite sides of the bus. The simultaneou~ly sinking and sourcing of current requires simultaneous switching of both sides of the bus which can introduce noise into the system. Similar problems are encountered in single-ended bus designs in prior art, including a proposed Future Bus concept, due to large simultaneous switching 5 currents.
Poorly or inadequately terminated buses is another source of noise in prior art multi-drop bus systems. In particular, the prior art buses are terminated at both ends with resistors whose value equals the characteristic impedance of the bus. This type 10 of termination is referred to as "odd-mode" termination. This type of termination leads to a situation where "common-mode"
signals induced in the bus "ring" for excessive periods of time, causing problems with signal integrity, EMI and common-mode range .
Viewed from current perspective, the prior art bus systems are designed for relatively low to moderate speed applications.
As new digital systems are developed, they are expected to achieve superior performance to existing (i.e., prior art) systems at the lowest possible cost. The term "performance"
embraces characteristics such as speed, function and reliability.
There is a growing demand for digital systems that exhibit high availability and high reliability. This creates a need for buses that are fault-tolerant and hot-pluggable (i.e., buses that support the live insertion of adapter cards ) .
There is a well-known trend in digital systems toward ever-faster data rates. Increased data rates require higher clock rates and faster slgnal transitions; factors that necessitate examination of the transmission-line nature of buses. One method to keep clock rates as low as possible while still improving effective throughput of a digltal system ls to make buses wide, i . e ., buses comprised of many bits in parallel . Bus widths in excess of 100 bits are not uncommon. Even as buses grow wider, clock rates are still increasing.

RA9-91-019s 3 Bus systems ( i . e ., buses and their associated drivers and receivers) must be carefully designed to meet the complete set of requirements that result from ~ ~Jve~ performance, functlon and cost. This set of requirements poses a set of problems that must S be solved simultaneously and optimally by the bus system.
Specifically, the following problems must be solved slmultaneously and optimally:
l. Speed An entire bit transfer must occur within the time of a single clock cycle. In other words, a data bit must propagate from the input of the transmitting driver across the bus to the output of the intended receiver within a clock period. Thus, there is a "time budget" that must be met that includes:
. driver circuit propagation delay6, signal propagation delay through connectors and across the bus, settling time for reflections, receiver circuit propagation delays.
The clock period to which this invention is designed is 25 ns. It should be noted that this is an aggressive target for a large physical bus length and the number of card slots .
2. Noise In addition to the noise problem alluded to above, excessive noise or inadequate noise margin can lead to performance problems through data integrity problems or through a need to reduce the clock rate to avoid data integrity problems.
There are potentially several types of noise in a bus system:
Coupled noise occurs when a signal on a conductor in the bus induces an undesired signal on a neighboring conductor 2 i 78846 on the bus.
Switching noise occurs when current pulses resulting from multiple bits changing ~tates simultaneously can induce undesired signals on power and/or ground which can, in turn, induce erroneous data signals on driver or receiver outputs.
EMI/EMC noise occurs when the bus system either radiates unacceptably in certain frequency bands or is unacceptably sensitive to ambient electromagnetic radiation.
Reflection noise occurs when reflections arising from impedance mismatches on the bus distort the data signals at the inputs to the receivers. Impedance mismatches can occur at card slots, as well as at the ends of the bus due to improper termination.

3. Power Consumption Power dissipated in the drivers must be kept to a minimum f or several reasons:
to maximize the achievable packaging density, to minimize the cost of power that must be supplied to the bus system, to maximize reliability, . to allow for cooling the components to a reasonable operating temperature.
At the same time, the drivers must be capable of driving the bus impedance, which can be as low as 15-20 ohms. This drive capacity is necessary because often the time budget does not allow for relying on reflections from the bus termination to create adequate signal at the receiver inputs. This type of requirement is called "incident switching. "

4. Packaging Density Drivers and receLver~ must be packagable at some optlmum density. Too dense, and problems with coupled noise (due to long signal line lengths), switching noise, and power dissipation will be exacerbated. Not dense enough, and costs (both parts and manufacturing) are driven up while system reliability is degraded.

5. Fault-Tolerance and Hot-Pluggability The driver and receiver circuits must be designed so that they can be inserted into a live bus without disrupting data transfers that may be in progress. Furthermore, should power fail on a particular adapter card, the drivers and receivers on that card must not load the bus so that it can no longer function.

6. Self-Diagnostic Capability The transceiver must support operation in "wrap" mode for diagnostic purposes. In wrap mode, drivers and receivers are simultaneously active and enabled. Thus, the card can drive data onto the bus while simultaneously reading data from the bus. In this way, the functionality of the transceiver may be ascertained.
None of the prior art bus systems simultaneously and optimally solves the problems stated above.
In addition, the prior art circuit type or components used in bus design were not acceptable. Several types of prior art components were considered, but were eliminated as the difficulty in satisfying the system requirements became clear. The available circuit types fell into three general categories: Open Collector, including TTL and Future Bus; Push-Pull, and Emitter Follower ECL. In general, the available parts were eliminated ~t 2 ~ 788~6 RA9-91-019s 6 due to:
1. inability to drive the current necessary to incidentally switch the bus (especially ECL, which requires an output voltage swing of about 800 mV, yet drivers are typically limited to 25 mA, less than the 53 mA required), 2. lack of the desired logical function (specifically the separate TTL inputs and outputs and separate drive and receive clocks ) without using multiple packages and the resulting excessive stub capacitance, 10 3. high output pin capacltance and resulting large backplane Lmpedance variation, 4 . inadequate delay performance ( including the Future Bus proposal ) 5 . simultaneous switchi~g noise ( especially the Future Bus proposal, with its 100 mA drivers), 6. coupled noise concerns with large signal swings and uncontrolled, unspecified edge rates (especially TTL) 7. high component cost, in particular, the Future sus proposal parts considered cost as much as $0.60 per bit, for a total bus driver cost of $67 per card (versus a $50 cost ob~ective), 8. low output impedance, resulting in signal reflections off the active driver. This is true of all circuit types except the current source/sink disclosed hereinafter.
other subtle concerns were raised during the initial investigation of the various circuit types, including:
Standard ECL gates do not fully cut of f, even when disabled .
This is to improve switching speed, but also limits the ability to "dot" outputs together due to the finite quiescent current . Unexpected ef fects can result due to current sharing between circuits that can drastically affect delay perf ormance .

~, 2~78846 The ~uture Bus proposal require~ a high current voltage regulator for the 2 volt termination supply that can handle the large, fast transient current variatlons ( zero to temperatures ln 5 nsec for 100 blts ) when the drlvers switch. There is no evidence that such a circuit exists.
SIIMMARY OF Tll~ JNVEI~TION
It is therefore a general ob~ect of the present inventlon to provlde a more efficient hlgh performance bus system than was 10 heretofore possible.
This and other desirable ob~ectives are contained in the present lnvention in which the bus system includes a relatively low impedance multidrop transmission medium (bus) and a plurality of hybrid transceivers connected thereto.
IS In particular, the low impedance bus includes a plurality of conductors terminated at each end by resistors whose values are selected to terminate both the odd (differential) and even (common) mode slgnals on the bus.
The hybrid transceiver includes a driver and a receiver.
The receiver is a dif ferential comparator receiver biased to a known output voltage level. The biasing causes the receiver output to a~sume a preferred state in the absence of an input signal .
Likewise, the driver includes a pseudo-differential current sink comprised of a current-steering current sink which sinks a predet~rm~ nP~I amount of current from one side or the other of the differential bus. When current is sinked from one side of the bus, the other side is turned of f . A double latch ~ h~n pipelines data into the driver and out of the receiver.
Two non-overlapping clock signals insure proper staging of the data into the driver and out of the receiver but may be tied in the active state to allow data to pass through the latch circuits. Separate "enable" signals control the driver and the ~ 21 78846 receiver. Wrap mode, whereln the output of a driver i8 fed into its receiver, is achieved by simultaneously activating the enable signals .
The foregoing features and advantages of the invention will S be more fully described in the Arrl -nying drawings.
RRTF:F ~F~ RTPTION nF ~HF DRAWINI~
Fig. 1 represents a schematic of the low impedance multi-drop bus according to the teachings of the present invention.
Figs. lA, lB and lC show a block diagram of the hybrid transceiver according to the teachings of the present invention.
Fig. 2 shows a block diagram of one-bit of the hybrid transceiver to the t~A~h~n~ of the present invention.
Fig. 3 shows a circuit schematic of the driver circuit.
Fig. 4 shows a circuit schematic of the circuit which enables the driver circuit.
Fig. 5 shows a functional representation of the driver circuit and controller.
DE'l'ATT.~n DE!::f'RTPTInN OF 'I'T~ ~K~ MpiollIMF~NT
Fig. 1 is a schematic representation of the bus system according to the t~eArh~n~ of the present invention. The bus system includes a wide (one-hundred bits) differential bus represented by communication wires BUSQ and BUSQ. The bus is 25 terminated by impedances Zl and Z2 to selected t~rm~n.ql voltage levels (VT). The impedance Zl and Z2 are selected such that both the odd and even propagation signal modes are terminated. In particular, the value of resistors R0 is set to a value of one-half the odd-mode impedance of the bus. The serles combination 30 of resistor RE with the parallel combination of two resistors R0 is chosen to equal the even mode impedance of the bus. Thus, odd mode and even mode signals propagating in the bus system are adequately terminated without signal reflection on the bus ~ 2178846 system .
A plurality of connectors 10, 12, ... N are connected at selected points along the length of the bus. The connectors form multi-drop points to which a plurality of transceivers (details to be given hereinafter) 10 ', 12 ', 14 ' . . .N' are connected.
Several known types of off-the-shelf connectors can be used to attach the transceivers. Because these connectors are well known, component details will not be given here.
Still referring to Figure 1, each of the transceivers is provided with a driver circuit arrangement (D) which accepts a signal on its input t~rm~n~l and places it on the bus for transmission to another transceiver connected to the bus. The receiver (R) in each transceiver package receives signals from the bus and delivers it to its output which is subsequently delivered to the device (not shown) which the transceiver attaches to the bus. For test purposes, a driver, in a transceiver module, can output signals on the bus and the signals are received at the input of the receiver. This wrap-around feature allows a transceiver to test its operability before it is connected into the bus.
Fig. 2 shows a block diagram of the transceiver according to the teachings of the present invention. It is worthwhile noting, at this point, that the transceivers are identical; therefore, the description to be given hereinafter is the same for each tr~nsceiver. The transceiver shown in Fig. 2 represents the data path for a single bit. For the particular problems posed above, a packaging density of f ive bits per package has been deemed optimal. Turning to Figs. lA and lB for the moment, a block diagram of a module with the preferred bit density is shown. The module includes five single bit transceivers (SBl, SB2, SB3, SB4 and SB5) interconnected to a common control logic block 32 (Com Ctrl L B). The details of the single bits and the control logic block will be given subsequently. Suffice it to say that the ~ 2 ~ 78846 control logic block 32 receives buffers and converts clock signals (C1 and C2) and control signals (DOE and ROE) to dif ferential logic level signals which are distributed to drive the single bit transceivers. The package chosen as optimal is a 5 28 pin plastic chip carrier (PCC) surface-mount package, to minimize wlring length and lead inductance. Depending upon application, other packaging densities may be deemed desirable without departing from the t~Arh i n~s of the present invention.
Still referring to Fig. 2, the rectangular pads connected to 10 each line represent input and output contact points or nodes for the chip. The data input signal (DR_IN) and receiver output (RCV OUT) are industry standard transistor-transistor logic (TTL) levels in the preferred embodiment. The clock signals (C1) and ( C2 ), driver output enable ( DOE ) and receiver output enable ( ROE ) 15 are positive emitter-coupled logic (PECL) levels in the preferred embodiment . These voltage levels are approximately 3 . 2 volts for logic "0" and 4.1 volts for logic "1". Depending on application, other levels for all inputs and outputs may be deemed desirable without departing from the tP~hin~c of the present invention.
20 The relationship of the named signals and the function which they serve will be described subsequently.
As stated previously, each transceiver includes a driver section and a receiver section. The receiver section includes a receiver (RCV 16) having its inputs connected to sides BUSQ and 25 BUSQ of the bus. The output of receiver 16 is connected to latching means 18 which is formed from latches L3 and L4. The latching means 18 pipeline data from receiver 16 into signal converter circuit means CV2. When activated by the signal ROE, CV2 converts and level shifts differential ECL input signals into 30 a single-ended TTL output signal on the line labeled RCV_OUT.
The signal converter circuit CV2 is an off-the-shelf circuit arrangement which converts a double-ended signal into a single-ended one. For example, an appropriate module is one bit of a 2 ~ 78846 Motorola MC 10H350.
Likewise recelver 16 ls a dlfferential lnput, dlfferentlal output voltage comparator, slmilar in function to National S eml c onduc tor LM3 6 0 .
Still referring to Figure 2, drlve data is presented to the chip at the DR_IN line uslng transistor-to-translstor loglc (TTL) signal levels. The data ls converted to dlfferentlal data via converter circuit means CVl and presented to latch clrcuit Ll.
The falling edge of the ClDl line clocks thls data to the input of latch Ll. The falling edge of the C2Dl line clocks thls data to the lnput of latch L2 whlch, ln turn, presents the data to the lnput of driver circuit 20. The driver circuit 20 (details to be given hereinafter) is a custom deslgned clrcuit which provides the proper Interface to the dlfferentlal bus (BUSQ and BUSQ).
The path for the recelve signal from the bus Is slmllar.
The recelver clrcult 16 is a dlfferentlal comparator wlth a small amount of input offset voltage applied in order to guarantee a known state at lts output during the time that no signals are present on the bus. The received output signal Is applled to the Input of latch L4. Thls latch Is clocked by the Cl clock such that the falllng edge of ClRI presents the recelved data to the Input of latch L3. Similarly, the falling edge of C2RI clocks data to the Input of the converter clrcult ( CV2 ) . The converter clrcuit CV2 converts the emltter coupled loglc (ECL) differential slgnal to the TTL single-ended output on pin labeled RCV_OUT. It should be noted that the circuit architecture employed malntalns the data In differentlal (ECL~ form as much as posslble on the chlp. Thls technlque provldes maximum speed, minlmum power and mlnlmizes noise radiatlon to other clrcuits ( both on and of f -chip). The means is also provlded to slmultaneously inhiblt all drlvers and/or recelvers on the chlp. The receivers are disabled vla the slgnal on the line labeled ROEI. Dlsabllng turns off the output stages of CV2 such that neither up nor down level is ~ 2178~46 active (high impedance output). The drivers are similarly turned of f via the DOE signal line. The control circuit 15 is a custom circuit (details to be given hereinafter) which set the controller reference current for all five drivers on the chip.
5 The DOE signal line is used as an input to the control circuit 15 in order to turn off (or on) the reference current. Thus, the drivers can be simultaneously disabled when the DOE line goes inactive. In the preferred embodiment, the inactive state for DOE is an ECL downlevel. In order to minimize on chip delays, 10 the two clock signals Cl and C2 and enable signals ROE and DOE
are carried as differential signals on the chip.
Figure 5 shows a functional representation of the control circuit 15 and driver circuit 20. The driver circuit 20 includes a current source 24 ' coupled by individually activatable switches 15 SW26 ' and SW28 ' to respective sides of the differential bus (BUSQ, BUSQ). When enabled via a signal on the output enabled signal line (DOE), the control circuit 15 sets a fixed amount of current ISRC which is sinked from the side of the bus that is coupled to the current source via one of the switches.
20 Therefore, by using the pseudo differential switch and control circuit, current is sinked from only one side of the bus while the other side remains undisturbed.
Figure 3 shows a detailed schematic for the driver circuit 20. Similar components in Figures 3 and 5 are labeled with the 25 same alpha numeric characters and/or numerals. The circuit includes current source 24 ' interconnected to BUSQ and BUSQ by differential switches 26' and 28', respectively. The differential switch 26 ' is coupled by RlA, device Q3, RBl and Rl to side IN of an input differential signal and to power supply 30 rails VccD and VEED. The emitter of device Q3 is coupled by device Q4 to voltage node V20 (details to be given hereinafter) and power supply rail VEED. Likewise, the differential switch 28 ' is coupled by R4A device Q8, RB2 and R4 to side INN of the differential input signal and power supply rails VEED and VccD.
The emitter of device Q8 is coupled through device Q9 and R3 to voltage node V20 and power supply rail VEED.
Still referring to Figure 3, the differential switches 26' and 28 ' include differential pairs Q5, Q5A, Q6 and Q6A. The collectors of the devices are connected directly to the bus (BUSQ
and BUSQ). A reference voltage (VIpGM) is supplied by the control circuit 15 (details to be given hereinafter) when the drivers are to be activated via the DOE line ( Figure 5 ) . A f ixed amount of current ISRc is then set up in the collectors of devices Q7 and Q7A respectively. In the preferred embodiment of this invention, ISRc is approximately 16 milliamps through the collector electrode of Q7 and Q7A respectively. It should be noted that other ratios of current can be drawn by current source 24 ' without deviating from the spirit and scope of the present invention. The driver output current is switched to either node on the BUSQ or BUSQ side of the bus by the input data which appears differentially at the circuit inputs (IN and INN). The resistor strings consisting of R1, RlA, R4 and R4A provide level shifting for the input signal which appears at the bases of Q3 and Q8 respectively. The devices Q3 and Q8 buffer the input signal and deliver them to the base of devices Q5 and Q6 respectively. The differential input voltage (IN, INN) is then applied to the current switching devices Q5 and Q5A and Q6 and Q6A. The Schottky diodes Dl and D2 are connected across the bus in order to limit the maximum signal swing and provide some attenuation for noise that may be coupled to the bus. Resistors RB1, RB2 and RS provide high frequency compensation during the switching transients. Devices Q4, Q9, R2 and R3 provide a small bias current for buffer devices Q3 and Q8. The bias current is derived from the voltage at node V20.
Preferably, V20 is a reference voltage supplied by an on-chip band gap reference circuit. The circuit is similar in .
RAg-91-019B 14 function to the National Semlconductor LN113 and LN185 reference diode devices.
Figure 4 shows a electrical schematic for the control circuit 15. The function of the control circuit 15 is to set the 5 controller reference current for all (five) drivers on the chip.
The control circuit 15 includes a reference current generator 30 (Q3', V20, Rl4) for generating a reference current. The reference current generator 30 is coupled by current gain circuit arrangement 32 to a current mirror formed by devices Q2 ', R9, Q8 ' 10 and R10. The current mirror is coupled by current gain circuit arrangement 34 to the collector electrode of reference connected device Q5 ' . The base of device Q5 ' is connected to signal lLne labeled VIpGM which sets up reference current in the drivers.
The collecter electrode of reference device Q5 ' is connected 15 through a rapid turn-on turn-off circuit formed from devices Q7 ', Q9', Q10', D11, R1' and R7'.
Still referring to Figure 4 for proper operation, the circuit elements in Figure 4 are closely matched with the circuit component of Figure 3. This match insures that an accurate 20 amount of current is sourced from either side of the differential bus. In the preferred embodiment of this invention, a reference current of approximately one milliamp is set up in Q3' collector via the on-chip band-gap voltage at node V20 . Devices Q2 ', Q8 ', and resistors R9 and R10 provide a current mirror with a gain of 25 2. This means that approximately two milliamps are available at the Q8' collector. Devices Ql', Q4', R8, R12, R3 and R11 are used to provide additional current gain for the PNP current mirror devices (Q2 ' and Q8 ' ) . It should be noted that circuit means 32 and 34 are used to compensate for the relatively low 30 Betas of the lateral PNP devices Q2 ' and Q8 ' . The 2 milliamp provided at Q8 collector electrode is applied to the reference connected device Q5 ' . A precise voltage drop is set up across R4 which interconnects the emitter of Q5 ' to voltage supply rail VEED. The base of Q5 ' (node VIp ) therefore becomes a reference node used to set up the current references in each of the five driver circuits in a transceiver module.
As stated previously, components in Figure 4 are closely 5 matched with components in Figure 3 to enhance the desirable operation of the described circuit. To this end, the resistor R4 is matched to the resistors R2A and R2B (Figure 3) in each of the driver circuits such that the ratios ( 160 ohms/40 ohm) produce a 4 times increase in current in the emitters of Q7 and Q7A ( Figure 10 3). In addition, devices Q7 and Q7A (Figure 3) are also ratioed by a factor of 4 relative to device Q5 (Figure 3) in order to improve accuracy of the current source. Therefore, the total current into the emitters of the differential drive devices Q5, Q5A, Q6, and Q6A is 16 milliamps. As stated previously, these 15 figures are mere exemplary and should not limit the scope of this invention .
Still referring to Figure 4, the device Q6' is used as a buffer transistor (current gain) for the reference circuit to minimize loading ef fects of the multiple driver circuits on the 20 single reference circuit. Resistors R6 and R13 along with capacitor Cl provide frequency compensation for the reference circuit. The DOE signal (Figure lA) is converted via Com Ctrl LB
32A (Figure lA) to differential signal VEN and VEN1 (Figure 4).
This differential signal VEN and VEN1 are applied to resistors 25 Rl ' and R7 ' . As a result, nearly identical current is set up in devices Q9 ' and Q10 ' . Since device Q10 ' is diode connected, the voltage at the collector electrode of device Q9 ' tends to stay at one diode drop above the reference point established by the anode of Schottky diode Dll. This means, in turn, that the base of Q7' 30 can be rapidly raised or lowered (that is, turned on or off) through the voltage range necessary to either turn Q7 ' on or off very quickly. When Q7 ' is turned on via lowering of VEN and the simultaneous raising of VENl, Q7' shunts the reference current 2 ~ 78846 RAg-gl-Olgs 16 setup by the current mirror into Q7 ' and Dll. This action removes the current from the reference clrcult formed by device Q5 ' and R4 which cause reference node VIpGM to drop in voltage, thereby turning off all five drlvers on the chlp. The capacltor 5 C2 ls used to enhance the dlscharge of Q7 ' collector node, ef fectively speeding up the circuit. R5 is used as a bleeder resistor to further enhance the discharge of node VIpGM when lt ls going to the dlsenabled state.
Among the advantages offered by the dlsclosed device are l) maximum immunity to noise coupled from other signal lines, and reduced loop area for EMI radiation generation;
2 ) capability to operate at one-half the signal swing required for even single-ended ECL, further reducing EMI and coupled nolse problems, since the important quantity for receptlon given a constant noise margin is the relative dlfference between the slgnal levels and the reference. The signal swing for differential lines need be only half that of single ended lines since the second signal line serves as a ref erence .
3 ) A conventional voltage comparator can be used as a receive circuit, with optimum noise margin unaffected by variations in the card power supply voltage ( since no reference vo l tage i s requ i red ) .
4) The circuit offers the lowest device capacitance of the circuits examined since the circuit presents only a single transistor collector to the bus. Use of a reasonably small current drive level (in this case, 16 milliamp) would allow the use of small devices, resulting in a low value of collector to substrate capacitance. This would, in turn, provide a low stub capacitance and minimi~e bus impedance variation with additlonal card loadlng.
5 ) Current mode output providing high output impedance.
This has two advantages over a voltage drive clrcult arrangement;

~ 2 1 78846 RA9-91-019s 17 namely, a) signals traveling on the bus do not reflect off the impedance mismatch seen at the driving circuit a~ would be the case with the voltage mode driver which looks to the bus as a 5 very low i, ~-n~e.
b) a current mode driver is inherently hot pluggable since current is only sourced or slnked when the driver circuit Ls enabled. De~igning a voltage mode driver to mee~ the hot plug requirement would be a ma~or challenge.
6 ) Constant power supply and ground current during slgnal tran~mission, eliminating simultaneous switching noise except during enabling and disenabling of the drivers. This feature ~ignificantly reduces both system noise and EMI.
7 ) Constant termination current when enabled. This is 15 significant since the terminating resistors are to be located on separate cards pluggable into the end slots of the backplane but supplied by DC to DC converters on the interchange (control) cards. Therefore, large data-dependent transient current requirements for the terminators were expected to cause 20 signiflcant noise problems were they to exist.
8 ) Packaging five bitg to a chip provides an optimum tradeoff between maximizing packaging density and minimizing stub lengths between the bus and the transceivers.

9 ) Separate driver and receiver enable inputs permit "wrap-25 around" operation for diagnostic purposes.

10) Inherent card failure protection of the bus (if an on-card power supply or component fails, the bus can still f unction ) .
While there has been described a preferred embodlment of the 30 present invention, variatlons and modifications in that embodiment may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims shall be construed to include both the ~ 2 1 78846 RA9-91-019s 18 preferred emoodiment and all such variation~ and modlfication~ as ~all within the ~pirit and ~cope of the invention.

Claims (15)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An improved transceiver for use with a multidrop pseudo-differential bus comprising:
a first circuit means for receiving a single ended signal representative of data bits; said first circuit means level shifting and converting the signal into differential signals;
a second latch circuit means responsive to the differential signals and clock signals to pipeline data bits;
a differential driver circuit for receiving the bits, said differential driver circuit responsive to a control signal to activate or deactivate its output on said pseudo-differential bus;
a third circuit means for receiving an enabling single ended signal and converting it into enabling differential signals; and a fourth circuit means for receiving the enabling differential signals and generating the control signal which causes a fixed amount of current to be sinked from said pseudo-differential bus.

2. The improved transceiver of Claim 1 further including a receiving circuit means with differential inputs for coupling to outputs of the differential driver;
a fifth circuit means responsive to a set of clock signals for pipelining data outputted from the receiving circuit; and a sixth circuit means for receiving dif ferential data signals from the fifth circuit means and converting said differential data signal into a single ended TTL level signal.

3. The improved transceiver of Claim 2 wherein the second and sixth circuit means includes;
a pair of series connected polarity-hold latches; and a pair of non-overlapping clock signals for gating data into selected ones of the pair of series connected polarity-hold latches.

4. The improved transceiver of Claim 3 wherein the differential driver circuit includes:
a voltage supply node for supplying power;
a referenced node;
a differential circuit arrangement for sinking current from each side of the differential bus; said differential circuit arrangement having a first node coupled to one side of the differential bus, a second node coupled to another side of the differential bus, a third node, a fourth node and a fifth node;
a current source interconnecting the fifth node to the reference node;
compensation circuit means for providing high frequency compensation during switching, connected to the nodes 3 and 4;
a first amplifying device coupled to the compensation circuit means;
a second amplifying device coupled to the compensation circuit means;
a seventh circuit means for providing level shifting to a differential signal connected to the first amplifying device;
an eighth circuit means for providing level shifting to said differential signal connected to the second amplifying means.

5. The improved transceiver of Claim 4 further including a ninth circuit means for providing bias current, interconnecting the first amplifying device and second amplifying device to the reference node.

6. The improved transceiver of Claim 5 further including a control means for activating/deactivating the differential device.

7. The improved transceiver of Claim 4 wherein the differential circuit arrangement includes multiple parallel connected bipolar devices and multiple parallel connected bipolar devices, with the emitter electrode of the bipolar devices connected to node 5, the collector electrodes of the first pair connected to the node 1, the base electrodes of the first pair connected to the node 3, the collector electrode of the second pair connected to node 2, and the base electrode of the second pair connected to the node 4.

8. The improved transceiver of Claim 7 wherein the current source includes multiple bipolar transistors connected in parallel with a collector electrode of each transistor connected to the node 5, a base electrode of each transistor connected to a control node;
a first resistive means interconnecting an emitter electrode of one of the transistors in the third pair to the reference node; and a second resistive means interconnecting an emitter electrode of another of the transistors in the third pair to the reference node.

9. The improved transceiver of Claim 8 wherein the compensation circuit means includes:
a first resistor interconnecting the node 3 to node 4;
a second resistor connected to node 3; and a third resistor connected to node 4.

10. The improved transceiver of Claim 9 wherein the first amplifying device includes a bipolar transistor having an emitter electrode coupled to the second resistor, a base electrode and a collector electrode connected to the voltage supply node.

11. The improved transceiver of Claim 10 wherein the second amplifying device includes a bipolar transistor having an emitter electrode connected to the third resistor, a base electrode and a collector electrode connected to the voltage supply node.

12. The improved transceiver of Claim 11 wherein the seventh circuit means includes a pair of resistors connected in sries and interconnecting an input node to the reference node;
said pair of resistors including a node intermediate said resistors and connected to a base electrode of the first amplifying device.

13. The improved transceiver of Claim 12 wherein the eighth circuit means includes a pair of resistors connected in series and interconnecting another input node to the reference node;
said pair of resistors including a node posltloned intermediate said resistors and connected to a base electrode of the second amplifying device.

14. The improved transceiver of Claim 13 wherein the ninth circuit means includes a first transistor device having a collector electrode connected to the second resistor, an emitter electrode and a base electrode;
a resistor connecting the emitter electrode to reference node;
a second transistor device having a base electrode connected to the base electrode of the first transistor;
a collector electrode connected to the third resistor and an emitter electrode; and a resistor interconnecting the emitter electrode of the second transistor to the reference node.

15. The improved transceiver of Claim 14 wherein the control means includes a first means for generating a desired reference current;
a second means coupled to the first means; said second means mirroring and amplifying the reference current;
a third circuit means for generating a precise reference current interconnecting the second means to the reference node;
and a fourth circuit means coupling the third circuit means to the reference node and input nodes of bipolar enabling signals;
said fourth circuit means responding to the bipolar enabling signals to provide a rapid turn-on or turn-off to the third circuit means.