JP2857020B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a vertical overflow drain structure for suppressing blooming and a method of manufacturing the same.

[0002]

2. Description of the Related Art A solid-state image pickup device has an upper limit in the amount of charge that can be handled by each pixel, regardless of whether it is a CCD type or a MOS type. Overflow blooming phenomenon occurs. Therefore, in order to suppress such a blooming phenomenon, it has been proposed to provide an overflow drain for absorbing a charge exceeding a threshold in a light receiving unit of the solid-state imaging device.
At present, a vertical overflow drain structure that does not lower the aperture ratio of a pixel is often used.

FIG. 7 shows the vertical overflow drain structure in an interline transfer type CCD image pickup device. This diagram schematically illustrates the structure of one pixel, in which the vertical axis indicates the depth direction of the element substrate, and the horizontal axis indicates the direction orthogonal to the transfer direction in the vertical transfer unit. Also, this CCD imaging device is of a conductive type using electrons as signal charges.

This CCD image pickup device is formed on an n-type semiconductor substrate 1, and a well layer 2 made of a p-type semiconductor is formed on the semiconductor substrate 1. In a part of the upper layer of the well layer 2, n for receiving light of one pixel is provided.
A light receiving section 3 made of a type semiconductor is formed, and an upper layer of the light receiving section 3 is covered with a high-concentration p-type high-concentration p-type semiconductor layer 4. The high-concentration p-type semiconductor layer 4 is
Is connected to a channel stop region 5 for partitioning between adjacent pixels formed on one side of the channel stop region. On the other side of the light receiving section 3, a buried channel type transfer section 7 made of an n-type semiconductor is formed via a transfer region 6 formed by a p-type well layer 2. The transfer region 6 is a region for controlling conduction between the light receiving unit 3 and the transfer unit 7 by a potential barrier, and the potential of the transfer unit 7 is controlled by an electrode formed thereover via an insulating layer (not shown). 8 is controlled.

The semiconductor substrate 1 is applied with a positive and sufficiently high voltage which is reversely biased with respect to a channel stop potential (ground potential, ie, 0 V).
When a large amount of electrons are accumulated in the light receiving section 3 due to the incidence of excessive light, the overflowed electrons flow out of the potential barrier formed by the well layer 2 to the reverse-biased semiconductor substrate 1. Accordingly, the blooming phenomenon can be suppressed.

Here, C in the BB section of FIG.
FIG. 8 shows the impurity concentration distribution of the CD imaging device. This impurity concentration is approximated by a step concentration for simplicity.
That is, the semiconductor substrate 1 has an impurity concentration N1, the well layer 2 has a thickness d2 and an impurity concentration N2, and the light receiving portion 3 has a thickness d2.
3. The impurity concentration is N3, and the high concentration p-type semiconductor layer 4 has a thickness d4 and an impurity concentration N4.

Then, the maximum potential of the light receiving section 3 is set to V
A, the potential barrier from the light receiving section 3 to the semiconductor substrate 1 is VB, the potential barrier from the semiconductor substrate 1 to the light receiving section 3 is VC , the boundary with the well layer 2 and the high-concentration p-type half.
Assuming that the distances from the boundary with the conductor layer 4 to the maximum potential position of the light receiving section 3 are a and b, respectively, the relationship of Equation 1 is obtained.

[0008]

(Equation 1)

The substrate voltage Vsub applied to the semiconductor substrate 1 is expressed by the following equation (2).

[0010]

(Equation 2)

In the above-mentioned CCD image pickup device, each impurity concentration and the thickness of the layer are set to values of Expressions 3 and 4,

[0012]

(Equation 3)

[0013]

(Equation 4)

An example in which each voltage at the time of depletion is represented by Formula 5 will be described with reference to FIG.

[0015]

(Equation 5)

At the time of depletion, the substrate voltage Vsub becomes 10 V according to the above equation (2). As shown in the figure, the potential barrier VB from the light receiving section 3 to the semiconductor substrate 1 and the potential barrier VC from the semiconductor substrate 1 to the light receiving section 3 are reduced. Is an appropriate value, so that electrons can be stored in the light receiving section 3.

Also, while the substrate voltage Vsub remains, electrons accumulate in the light receiving portion 3 up to the charge QS, and when the potential barrier VB drops to VB0, the electrons flow into the semiconductor substrate 1 as an overflow current IOF. However, this can suppress the blooming phenomenon. The potential barrier VB0 is about 0.5 V in the case of a silicon semiconductor device, and is a distance a,
Assuming that each value of b is a0 and b0, the charge QS indicating the saturation signal level is expressed by the following equation (6).

[0018]

(Equation 6)

The maximum potential VA, potential barrier VB, substrate voltage V
When each value of sub and the charge QS is obtained, it becomes as shown in Expression 7.

[0020]

(Equation 7)

This is the state at the time of overflow shown in FIG.

Further, when the substrate voltage Vsub of the semiconductor substrate 1 is increased in a state where electrons are not accumulated in the light receiving section 3, the potential barrier VB is reduced. When the potential barrier VB becomes zero, the potential distribution of the CCD image sensor monotonically increases in the depth direction.
The electrons are not accumulated in the light receiving section 3 but are all discharged to the semiconductor substrate 1. Therefore, the substrate voltage Vsub
Can be used as an electronic shutter function for controlling the effective accumulation time in the light receiving unit 3 by setting a higher voltage. In this case, the distances a and b are respectively represented by the following Expression 8.

[0023]

(Equation 8)

The values of the maximum potential VA and the potential barrier VC are obtained from the above equation (1), and these are respectively calculated as VA
Assuming that S and VCS, the substrate voltage Vsub is expressed by Equation 9.

[0025]

(Equation 9)

Further, when the values of the maximum potential VA, potential barrier VC and substrate voltage Vsub of the light receiving portion 3 are obtained based on the above example, the values are as shown in Expression 10.

[0027]

(Equation 10)

This is the state at the time of shutter shown in FIG.

As a result, in the vertical overflow drain structure shown in FIG. 7, the substrate voltage Vsub of the semiconductor substrate 1 needs to be 10 V at normal time and 28.53 V at the time of shutter, so that an extremely high voltage needs to be applied. Since such a high voltage imposes a heavy burden on a drive circuit of a solid-state imaging device, proposals have been made to lower the substrate voltage Vsub (Japanese Patent Laid-Open No. Sho 62-24).
666).

FIG. 10 shows a vertical overflow drain structure capable of lowering the substrate voltage Vsub. Here, the well layer 2 in the n-type semiconductor substrate 1 is
A first region 10 having a higher impurity concentration is formed in an upper layer portion in contact with. The first region 10 is formed in a range located below the light receiving unit 3 in the horizontal direction.

When the first region 10 is formed in the semiconductor substrate 1 in this manner, as shown in FIG. 11, the impurity concentration of the portion of the semiconductor substrate 1 in contact with the well layer 2 increases to N10. Then, in the above examples of Equations 3 to 5,
Assuming that the impurity concentration N10 is a value shown in Equation 11,

[0032]

[Equation 11]

The maximum potential VA, potential barrier VC, and substrate voltage V of the light receiving section 3 at the time of overflow.
The sub and the charge QS take the values shown in Expression 12, and

[0034]

(Equation 12)

The maximum potential VA, potential barrier VC, and substrate voltage Vsub of the light receiving section 3 at the time of the shutter are the respective values shown in Expression 13.

[0036]

(Equation 13)

FIG. 12 shows the potential distribution of the CCD image pickup device in the cross section taken along the line CC of FIG. As shown in the figure, the potential distribution at the time of overflow and at the time of shutter is such that at the time of overflow, the overflow current I _of flows out to the semiconductor substrate 1 and at the time of shutter,
All the electrons accumulated in the light receiving section 3 can be discharged to the semiconductor substrate 1, and the substrate voltage V _{sub in} each case can be discharged.
Can be greatly reduced.

[0038]

However, in the above example, the maximum potential VA, the potential barrier VB, the potential barrier VC and the substrate voltage Vsub of the light receiving section 3 at the time of depletion where electrons are not accumulated in the light receiving section 3 are described.
Is obtained, each value shown in Expression 14 is obtained.

[0039]

[Equation 14]

Accordingly, in this state, the maximum potential VA is higher than the substrate voltage Vsub, and the potential barrier VC is only 0.20 V. Therefore, it is clear from the potential distribution at the time of depletion shown in FIG. Then, the phenomenon of charge injection from the semiconductor substrate 1 to the light receiving section 3 occurs.

For this reason, the conventional vertical overflow drain structure shown in FIG. 10 is not practical unless the substrate voltage Vsub is higher than the above example, and the substrate voltage Vsub is greatly reduced. Therefore, the effect of reducing the load on the drive circuit of the solid-state imaging device cannot be sufficiently obtained. Further, in this case, there is a problem that the potential barrier VB becomes extremely small, and the light receiving unit 3 can hardly accumulate signal charges.

In view of the above circumstances, the present invention provides a high-concentration first region in a semiconductor substrate and a high-concentration second region also in a well layer, so that depletion occurs even when the substrate voltage is significantly reduced. It is an object of the present invention to provide a solid-state imaging device in which a charge injection phenomenon does not sometimes occur.

[0043]

The present invention according to claim 1 is provided.
Solid-state imaging device is mounted on one conductive type semiconductor substrate
A well layer of a conductive type semiconductor is formed,
Part of the upper layer of the well layer is made of a semiconductor of one conductivity type.
In a solid-state imaging device having a light receiving section, the semiconductor substrate
At least at a position below the light receiving portion of the upper layer portion of the plate,
Forming a first region of one conductivity type having a higher concentration than the semiconductor substrate;
Forming and contacting the semiconductor substrate in the well layer.
At an upper position covering at least the first region of the lower layer portion,
Upper position covering the other conductivity type having a higher concentration than the well layer
A second region of the other conductivity type having a higher concentration than the well layer.
Is formed. Claims
2. The solid-state imaging device according to item 2 above,
That a high-concentration semiconductor layer of the other conductivity type is formed
The solid-state imaging device according to claim 1, wherein
You. The solid-state imaging device according to the present invention described in claim 3 is
The first region is in contact with the well layer on the semiconductor substrate
Characterized by being formed as follows.
A solid-state imaging device according to claim 2. Claim 4
The solid-state imaging device according to the aspect of the present invention,
The second region is formed over the entire pixel region.
The solid according to any one of claims 1 to 3, wherein
An imaging device.

The solid-state imaging device according to the fifth aspect of the present invention.
The method of manufacturing the device, wherein the higher concentration than the semiconductor substrate
A first region of one conductivity type and a higher concentration than the well layer;
And the second region of the other conductivity type with high energy.
Formed by an ion implantation method using
The solid-state imaging device according to any one of claims 1 to 4,
It is a manufacturing method of an apparatus.

[0045]

The first conductivity type of one conductivity type having a higher concentration than the semiconductor substrate.
The region can suppress the extension of the depletion layer toward the substrate when a reverse bias substrate voltage is applied to the semiconductor substrate. Therefore, by forming the first region, the substrate voltage (absolute value) during the normal operation and the shutter operation can be reduced.

In the second region of the other conductivity type having a higher concentration than that of the well layer, the voltage (absolute value) of the light-receiving portion is increased when the substrate voltage is significantly reduced by the first region. In this case, the potential barrier from the semiconductor substrate to the light receiving portion can be prevented from lowering. Therefore, by the formation of the second region, even when the charges (electrons or holes) in the light receiving portion are emptied and the voltage rises, the phenomenon of charge injection from the semiconductor substrate to the light receiving portion can be prevented. .

Therefore, according to the first aspect of the present invention, even if the first region is formed to reduce the load on the driving circuit of the solid-state imaging device and the substrate voltage is greatly reduced, This makes it possible to prevent the injection phenomenon from occurring from the semiconductor substrate when the electric charge in the light receiving portion becomes empty.

According to the fifth aspect of the present invention, in the solid-state imaging device, high-energy ion implantation is performed to form the high-concentration first and second regions in a deep region away from the surface of the semiconductor element. Since the method is used, the productivity can be improved as compared with the case where the well layer is formed on the semiconductor substrate by the epitaxial method.

[0049]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 3 show one embodiment of the present invention. FIG. 1 is a partial vertical sectional view of a CCD image pickup device, and FIG. 2 shows an impurity concentration distribution in an AA section of FIG. FIG. 3 and FIG. 3 are diagrams showing the potential distribution in the AA section of FIG. Note that components having the same functions as those of the conventional example shown in FIGS. 7 to 12 are denoted by the same reference numerals, and description thereof will be omitted. The impurity concentration in FIG. 2 is approximated by a step concentration for simplicity.

In this embodiment, an interline transfer type CC
4 shows a vertical overflow drain structure in a D imaging device. Also, this CCD imaging device is of a conductive type using electrons as signal charges. The present invention is not limited to this interline transfer type CCD image pickup device, but can be applied to a frame transfer type or linear transfer type CCD image pickup device having a vertical overflow drain structure. Further, if the conductivity type is changed, the present invention can be applied to a CCD imaging device that uses holes as signal charges.

A well layer 2 made of a p-type semiconductor is formed on an n-type semiconductor substrate 1, and a light-receiving portion 3 made of an n-type semiconductor is formed on a part of the upper layer. The structure covered with the high-concentration p-type semiconductor layer 4 is the same as that of the conventional example shown in FIG. The configuration in which the first region 10 made of a high-concentration n-type semiconductor is formed at a position below the light receiving section 3 in the upper layer portion of the n-type semiconductor substrate 1 is the same as the conventional example of FIG.

In the CCD image pickup device of this embodiment, a second region 20 having a higher impurity concentration is formed in a lower layer portion of the p-type well layer 2 in contact with the semiconductor substrate 1. This second region 20 is formed in the first region of the semiconductor substrate 1.
It is formed in a range below the light receiving portion 3 as in the region 10, but is preferably slightly wider in the horizontal direction than the first region 10 as shown in the figure.

In the CCD image pickup device having the above-described structure, the high-concentration first region 10 is formed on the semiconductor substrate 1 and the high-concentration second region 20 is formed on the well layer 2, as shown in FIG. In addition, the impurity concentration of the portion of the semiconductor substrate 1 in contact with the well layer 2 increases to N10, and the impurity concentration of the portion of the well layer 2 in contact with the semiconductor substrate 1 increases to N20. Therefore, the maximum potential VA of the light receiving unit 3 remains as shown in the above equation 1, but the potential barrier VB and the potential barrier VC differ depending on the position of the distance a to the maximum potential position of the light receiving unit 3. That is, the maximum potential VA has the relationship of Expression 15,

[0055]

(Equation 15)

The potential barrier VB and the potential barrier VC have the relationship of Expression 16 or Expression 17 depending on the condition of the distance a.

[0057]

(Equation 16)

[0058]

[Equation 17]

Here, at the time of overflow, the potential barrier VB becomes VB0 (= 0.5 V).
For the sake of simplicity, if the distance a is given by the following equation 18,

[0060]

(Equation 18)

The distance a0 at the time of overflow and the depth d2 of the well layer 2 are represented by Expression 19.

[0062]

[Equation 19]

The potential barrier VC at this time is
Is VC0, the depth d20 of the second region 20 is expressed by Expression 20.

[0064]

(Equation 20)

Assuming that the maximum potential VA is VA0, the distance b is expressed by Expression 21.

[0066]

(Equation 21)

Then, the charge QS (saturation signal amount) at the time of overflow is expressed by Expression 22.

[0068]

(Equation 22)

The potential barrier VC at the time of depletion
Is defined as VC1 (0.5V <VC1 <VC0).
Since this corresponds to the condition of the distance a in
Expression 23

[0070]

(Equation 23)

The potential barrier VB at the time of depletion, VB1, is obtained from Equations 17 and 23. Therefore, the maximum potential VA is expressed by Expression 24,

[0072]

(Equation 24)

From this, the distance b is obtained from the above equation (15).
Assuming that this is b1, the thickness d3 of the light receiving section 3 is expressed by Expression 25.

[0074]

(Equation 25)

Further, at the time of shuttering, since the distance a becomes zero, the distance b coincides with the thickness d3 of the light receiving section 3, and the substrate voltage Vsub at this time is expressed by Expression 26.

[0076]

(Equation 26)

Then, the condition of the impurity concentration shown in the equation (3) is applied, and the impurity concentrations N10 and N20 of the first region 10 and the second region 20 are set to the values of the expression 27, respectively.

[0078]

[Equation 27]

Assuming that each potential at the time of overflow is the value of Equation 28,

[0080]

[Equation 28]

The distances a0 and b0 and the thickness d2 of the well layer 2
And the thickness d20 of the second region 20 is a value shown in Expression 29.

[0082]

(Equation 29)

If the potential barrier VC1 at the time of depletion is 1.0 V, each potential and the distances a1, b1
And the thickness d3 of the light receiving section 3 is a value shown in Expression 30.

[0084]

[Equation 30]

Further, the charge QS at the time of overflow and the substrate voltage Vsub at the time of shutter have the values shown in Expression 31.

[0086]

(Equation 31)

As a result, a vertical overflow drain structure under the above conditions can be sufficiently formed, and the potential distribution in this case is as shown in FIG. That is, the substrate voltage Vsub is 3.5 V during the normal operation and 10.66 V during the shutter operation, and can be greatly reduced as compared with the conventional example shown in FIGS. The light receiving unit 3
Is completely depleted, its maximum potential V
A1 is 4.71 V, which is lower than the substrate voltage Vsub of 3.5 V. However, the potential barrier VC1 from the semiconductor substrate 1 to the light receiving section 3 is 1.0 V, which is sufficiently large, so that electrons The injection phenomenon can be prevented. Further, the charge QS (saturation signal amount) at the time of overflow is also expressed by Equation (3).
It becomes the value shown in FIG. 1 and a sufficient amount can be secured.

In FIG. 2, it is desirable that the thickness d10 of the n-type high concentration first region 10 be as follows. That is, when a reverse bias voltage is applied between the substrate 1 and the p-type well layer 2, the end of the depletion layer extending from the junction interface to the substrate 1 is at least in the lower region of the light receiving section 3. 1
That is, the state is to remain in the area 10. This depletion layer extends most during the shutter. Therefore, the thickness d
10 is defined as in the following Expression 32.

[0089]

(Equation 32)

FIG. 4 shows another embodiment of the present invention, and is a partial longitudinal sectional view of a CCD image pickup device. Components having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, the second
The region 20 not only covers the first region 10 of the semiconductor substrate 1 but also extends in the horizontal direction over the entire pixel region.

According to the above configuration, since the potential distribution of the CCD image pickup device is the same as that of FIG. 2, the same effect as in the first embodiment can be obtained. In addition, in the case of the present embodiment, since the second region 20 is also formed below the transfer section 7, it is possible to surely prevent the phenomenon of charge injection from the semiconductor grave 1 into the transfer section 7. Will be able to do it .

FIG. 5 shows still another embodiment of the present invention, and is a partial longitudinal sectional view of a CCD image pickup device. The same reference numerals are given to components having the same functions as those of the first and second embodiments shown in FIGS. 1 and 4 and description thereof is omitted.

In the present embodiment, the second
The region 20 is formed so as to extend horizontally in the entire pixel region, and the first region 10 formed in the semiconductor substrate 1 is also formed so as to extend horizontally in the entire pixel region.

Also in the case of the above configuration, since the potential distribution of the CCD image sensor becomes the same as that of FIG. 2, the same effect as that of the first embodiment can be obtained. Also, the second region 20
By selecting the formation conditions, the phenomenon of charge injection from the semiconductor substrate 1 to the transfer section 7 can be prevented, as in the second embodiment. In the present embodiment, when the pixel size is further reduced, the second region 20
In addition to the first region 10, it is not necessary to consider the spread in the lateral direction, so that the first region 10 and the second region 20 can be easily formed.

The first region 10 and the second region 20 in each of the above embodiments are formed as regions having a high impurity concentration at a deep position away from the surface of the CCD image pickup device.
In order to form such a region, as shown in the above-mentioned JP-A-62-24666, the semiconductor substrate 1 is formed.
A method of forming the well layer 2 thereon by epitaxial growth can be used. However, in each of the above embodiments, an ion implantation method using high energy is used.

In the ion implantation method using high energy, the average implantation depth RP, the standard deviation σP, and the implantation energy E at the time of boron and phosphorus ion implantation have a relationship represented by the following equation (33). Edition (McGrow-Hil
l, 1988) from Chapter 8.)

[0098]

[Equation 33]

Therefore, the first region 1 in each of the above embodiments is used.
In the case where phosphorus is used to form 0, if the implantation energy E is 2.12 MeV, the average implantation depth RP is 2.40.
μm, and the standard deviation σP becomes 0.35 μm, so that phosphorus is implanted at a high concentration in a region of 2.05 μm to 2.75 μm in depth. When boron is used to form the second region 20, the implantation energy E is set to 1.01 MeV.
Then, the average implantation depth RP is 1.85 μm, the standard deviation σP is 0.14 μm, and the depth is 1.71 μm.
Boron is implanted at a high concentration in a region of about 1.99 μm. If the thickness d4 of the high-concentration p-type semiconductor layer 4 is 0.24 μm, the first region 10 has a thickness of 2.00 μm.
The second region 20 is formed at a depth of about 2.81 μm.
Since it is formed at a depth of 1.67 μm to 2.00 μm, the result substantially matches the result of the ion implantation using phosphorus and boron. It can be seen that this is a very suitable method for forming the second region 20.

It should be noted that ion implantation with high energy
The technique used for manufacturing a CD imaging device is a conventionally known technique (for example, “Nikkei Microdevice”, published by Nikkei BP, December 1991, pp. 99-103). However, conventionally, this high energy ion implantation is used for the purpose of improving the uniformity in the depth direction and suppressing the lateral diffusion, and the first ion implantation for improving the potential distribution as in each of the above embodiments is performed. There is no example used for forming the region 10 and the second region 20.

According to the present invention, after the accumulation of electrons in the light receiving section reaches the saturation signal level, the amount of stored signal increases with the increase in the amount of received light. This can be achieved for the following reasons.

In the element having the conventional structure, the overflow current IOF is increased by increasing the amount of received light.
As the potential barrier VB from the semiconductor substrate 1 to the semiconductor substrate 1 decreases, the potential barrier VC from the semiconductor substrate 1 to the light receiving section 3 also increases greatly. That is, since the maximum potential VA of the light receiving unit 3 is significantly reduced, the amount of signal accumulated in the light receiving unit 3 is greatly increased.

On the other hand, in the present invention, the potential barrier V
Even if B is reduced, the increase in the potential barrier VC is small. That is, since the potential VA slightly decreases, an increase in the signal amount accumulated in the light receiving unit 3 is suppressed to a low level.

FIG. 6 shows the relationship between the amount of received light and the amount of signal accumulated in the light receiving section 3. In the element having the conventional structure shown in FIG. 3B, the signal amount increases remarkably even after the accumulated signal amount reaches the saturation signal level QSO at the light reception amount PO with respect to the increase in the light reception amount. And the maximum allowable signal amount QSM is reached. On the other hand, in the device of the present invention shown by (A) in the figure, after the accumulated signal amount reaches the saturation signal level QSO at the received light amount PO with respect to the increase in the received light amount, the increase in the signal amount is suppressed low. , And finally reaches the maximum allowable signal amount QSM with the light reception amount PA (PA> PB). That is, according to the present invention, the maximum allowable light amount of the element can be greatly increased from PB to PA.

[0105]

As is apparent from the above description, according to the present invention, the phenomenon of injection from the semiconductor substrate when the substrate voltage is reduced can be prevented, and the substrate voltage is greatly reduced to enable solid-state imaging. The load on the drive circuit of the device can be sufficiently reduced. Further, by using an ion implantation method with high energy, the productivity of the solid-state imaging device can be improved.

Further, according to the present invention, the maximum allowable light amount of the element can be greatly increased.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, in which a CCD is used.
FIG. 3 is a partial vertical cross-sectional view of the imaging device.

FIG. 2, showing an embodiment of the present invention, is a diagram illustrating an impurity concentration distribution in a cross section taken along line AA of FIG. 1;

FIG. 3, showing an example of the present invention, is a diagram showing a potential distribution in the AA cross section of FIG. 1;

FIG. 4 shows another embodiment of the present invention, in which CC
FIG. 3 is a partial vertical sectional view of a D imaging device.

FIG. 5 is a partial longitudinal sectional view of a CCD image pickup device, showing still another embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the amount of received light and the amount of signal accumulated in a light receiving unit in the CCD image pickup device of the present invention.

FIG. 7 shows a conventional example, and is a partial longitudinal sectional view of a CCD image pickup device.

8 is a view showing a conventional example, and is a view showing an impurity concentration distribution in a BB section of FIG. 7; FIG.

9 shows a conventional example and is a diagram showing a potential distribution in a BB section of FIG. 7. FIG.

FIG. 10 shows a conventional example and is a partial longitudinal sectional view of a CCD image pickup device.

FIG. 11 shows a conventional example, and is a sectional view taken along the line CC of FIG.
FIG. 4 is a diagram showing an impurity concentration distribution in a cross section.

FIG. 12 shows a conventional example, and shows CC in FIG.
It is a figure showing the potential distribution in a section.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 10 1st area | region 2 well layer 20 2nd area 3 Light-receiving part 4 High concentration p-type semiconductor layer

Claims (5)

(57) [Claims] A well layer made of a semiconductor of the other conductivity type is formed on a semiconductor substrate of one conductivity type, and a light receiving portion made of a semiconductor of one conductivity type is formed in a part of an upper layer of the well layer. in the solid-state imaging device, said at least below the light receiving portion of the upper layer portion that put on a semiconductor substrate, with than the semiconductor substrate to form a first region of one conductivity type high concentration, the well layer A solid-state imaging device, wherein a second region of the other conductivity type having a higher concentration than the well layer is formed at a position above a lower layer portion in contact with the semiconductor substrate and at least covering the first region. 2. A high-concentration other conductive layer on the light receiving section.
Wherein a semiconductor layer of a mold is formed.
Item 2. The solid-state imaging device according to Item 1. (3) The first region is located on the semiconductor substrate.
Characterized by being formed so as to be in contact with the L layer.
The solid-state imaging device according to claim 1 or 2, wherein (4) The first region and the second region are pixel regions.
2. The method according to claim 1, wherein the first region is formed over the entire area.
The solid-state imaging device according to claim 3. (5) The one having a higher concentration than the semiconductor substrate
A first region of a conductivity type of
The second region of the other conductivity type is made to have a high energy.
Characterized by being formed by an ion implantation method,
The solid-state imaging device according to claim 1.
Manufacturing method.