JP2856184B2 - Test signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generating circuit, and more particularly to a test signal generating circuit for generating a high-speed test pattern signal to be input to a circuit under test, which is indispensable in a high-speed operation test of a Josephson circuit. About.

[0002] Compared to existing semiconductor integrated circuits, the Josephson circuit has a feature of faster switching,
Operation is possible at a high clock frequency of about z to 10 GHz. When performing a high-speed operation test of such a Josephson circuit, a 1-bit or multi-bit high-speed test signal pattern must be input to the Josephson circuit, which is the circuit under test. Normally, the operation test of the Josephson circuit is
A test pattern signal is input to a Josephson circuit using a commercially available semiconductor pulse pattern generator, and the output of the Josephson circuit is monitored by an oscilloscope. However, this method is sufficient for an operation test using a low-frequency clock, but the following problem occurs in an operation test using a high-frequency clock in the GHz range.

The first problem is that some commercially available semiconductor high-frequency pulse pattern generators have an operating frequency exceeding 1 GHz, but they are very expensive, and further high-speed operation tests are required. No pulse pattern generator exists. That is, when conducting an operation test of a Josephson integrated circuit, it is necessary to input a high-speed signal of several tens of bits. However, such a pulse pattern generator operating on a multi-channel and at a clock frequency of about 10 GHz is required. Does not exist.

[0004] The second problem is that it is difficult to adjust a cable length to reduce a delay time difference caused by propagating a high-speed signal supplied to a Josephson circuit for an operation test through a long cable, and it is difficult to perform multiplexing. A malfunction due to reflection or the like occurs. That is, since the Josephson circuit operates in a special environment of liquid helium temperature, it is operated by putting the chip in a refrigerator or a dewar containing liquid helium, so that the chip equipped with the Josephson circuit has room temperature. A signal is input from the unit through a cable of about 1 m. When a signal is input to the chip through such a long cable, the difference in propagation delay time between the signals due to a slight difference in the length of each cable becomes more pronounced at higher frequencies.

In order to perform an operation test of the Josephson circuit, it is necessary to adjust the length of each cable so that the delay time difference between the signals is as small as possible.
In the case of 0 GHz, this delay time difference is several picoseconds to 10
It must be adjusted with picosecond accuracy. One picosecond is about 0.1 m in terms of cable length.
m. It is technically difficult to adjust for such slight differences in length for each input signal cable, especially through Josephson integrated circuits that require tens of bits of input through such long cables and room temperature components. When a high-speed input signal is supplied from a computer, it is very difficult to adjust the length of the cable.

Further, while propagating through such a long cable, the input signal is distorted in waveform due to impedance mismatch at a connector portion or the like, causes multiple reflections, and is superimposed on the signal and input to the chip. As a result, there is also a problem that a malfunction of the circuit is caused. Further, there is a problem that crosstalk between high-speed signals at a portion such as a connection portion between a chip and a package causes crosstalk noise to be superimposed on a signal and input to a circuit to be measured, thereby causing a malfunction.

As described above, the Josephson circuit has an excellent performance of operating at a very high speed as compared with the conventional semiconductor circuit, and has a property of operating in a special environment of liquid helium temperature. The high-speed operation test in which the test signal is generated by the tester cannot perform the high-speed operation test in the maximum performance region of the Josephson circuit. Therefore, it is necessary to develop a test signal generation circuit that replaces a semiconductor pulse pattern generator.

[0008]

2. Description of the Related Art As a high-speed test signal generation circuit in consideration of the above-mentioned problem, a known document (Extended Abstracts of 1989 International Superconductivity Electronics Conference (ISEC'89), pp. 401-406) is known. Has proposed a test signal generation circuit using a ROM (read only memory). FIG. 5A is a circuit diagram of an example of the conventional test signal generation circuit, and FIG. 5B is a diagram showing a change in the output test signal of FIG. In this example, the configuration of a 3-bit test signal generation circuit is shown for convenience of description, but an arbitrary number of bits can be configured in principle. The conventional test signal generation circuit shown in FIG. 1 includes a ROM array 18 and a ROM corresponding to data "1".
Cell 19, ROM cell 20 corresponding to data "0", latch gate 21, shift register 22, OR gate 2
3, an external signal input terminal 24, a power supply input terminal 25 of a test signal generation circuit, a first bit test signal output terminal 2
6, a test signal output terminal 27 for the second bit, a test signal output terminal 28 for the third bit, a word line 29, and a bit line 30.

The test pattern signal includes a ROM cell 20 corresponding to data "0" and a ROM cell corresponding to data "1".
The data is written in the ROM array 18 depending on the arrangement of the cells 19. This test signal generation circuit is configured using a Josephson device, and is fabricated on the same chip as the Josephson circuit that is the circuit to be measured. When performing a complete operation test of the circuit under test, that is, an operation test for all input patterns, the ROM array 18 has n bits 2 bits.
^{It has n} words. Here, n is the number of bits of the input signal of the circuit under test. Since FIG. 5A shows a 3-bit test signal generation circuit, the ROM array 18 has a 3-bit 8-word configuration.

Next, the operation of the conventional circuit will be described. A high frequency power supply current synchronized with the clock of the circuit under test is supplied from a power supply input terminal 25 of the test signal generation circuit. In this state, “1” is output from the external input terminal 24 in a single shot or also every eight clocks synchronized with the clock of the circuit under test.
When an external input signal having the following pattern is input, the external input signal is transferred by the shift register 22 to the next-stage latch gate 21 every clock and simultaneously to a different word line 29 of the ROM array every clock. Control current is supplied. Thus, the control current is periodically supplied to each word line 29 once every eight clocks.

When a control current flows through the word line 29, the ROM cell 19 corresponding to the data "1" coupled to the word line 29 switches, and the ROM cell 1
9, test signal output terminals 26, 27, 28
Output a test signal. According to such an operation principle, the output of this circuit is as shown in the table of FIG.

As described above, this conventional test signal generation circuit generates a 3-bit periodic test pattern signal having a period of 8 clocks, and the pattern includes all combinations of the 3-bit signals. Therefore, a complete operation test of the circuit under test can be performed.

In this conventional test signal generation circuit, since the test signal generation circuit is formed on the same chip as the circuit under test, the signal output from the test signal generation circuit passes through the superconducting line on the chip. Input to the circuit under test.
Therefore, by designing the chip layout so that the wiring length of each signal becomes equal, the delay time of each signal can be easily equalized, and the signal waveform is not distorted. Also, since a high-speed signal input from the outside is 1 bit, an expensive high-frequency pulse pattern generator is required.
Any multi-bit test signal generation circuit can be configured simply by aligning the channels.

[0014]

However, the above-mentioned conventional test signal generation circuit has the following problems. First, there is a problem that the signal input from the external signal input terminal 24 must be synchronized with the clock of the circuit under test. Therefore, naturally, a high-speed external input signal is required. Although only one bit is required for the high-speed signal, the input signal must be supplied to the chip in phase with the power supply current, and as the clock frequency increases, multiple reflections and crosstalk at the cable connector will occur. There is still a problem that it becomes noticeable and causes a malfunction of the circuit under test.

Further, the clock frequency of the operation test is limited by the performance of the high-frequency pulse pattern generator, and there is a problem that a high-speed operation test in the maximum performance region of the circuit under test cannot be performed. In the test signal generating circuit shown in FIG. 5, the external input signal only needs to be input once every eight clocks with respect to the operation clock of the circuit under test.
There appears to be an advantage that the clock frequency of the external input signal is reduced, but it is not. The reason is that the signal input from the outside must rise during the activation time of the operation clock of the circuit under test (about 50 picoseconds in the case of 10 GHz). This means that an external input signal having a rise time of several tens of picoseconds or less is required. In other words, a semiconductor high-frequency pulse pattern generator that operates at a clock frequency similar to that of the circuit under test is required. It is necessary.

Second, as the number of bits of the input signal of the circuit under test increases, the bit line 29 and the word line 30 of the ROM array 18 become longer, and the operation time of the ROM increases. If the operation time of the ROM is longer than the operation time of the circuit under test, the test signal generation circuit itself limits the test clock frequency, and the test clock frequency can be increased to the maximum performance area of the circuit under test. Disappears.

Third, since the ROM array 18 is used, there is a problem that the area occupied by the test signal generation circuit is large and the power consumption is large.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a test signal generation circuit that does not require any signal input from a room temperature part, has a shorter operation time than any circuit under test, and does not limit the clock frequency of a high-speed operation test.

It is another object of the present invention to provide a test signal generating circuit which occupies a smaller area and consumes less power than conventional ones.

[0020]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a test signal generating a test signal of a plurality of bits by separately generating a test signal of each bit from a plurality of test signal generators. A generation circuit, wherein each of the plurality of test signal generation units is formed of a single latch gate or a feedback shift register including a plurality of latch gates, and each of the test signal generation units is formed of a latch gate. Are commonly connected to an external high-frequency power supply input terminal, and a signal output terminal of a predetermined one of the latch gates constituting each test signal generator is a 1-bit test signal output terminal. Connected to.

According to the present invention, each of the plurality of test signal generating sections for generating a test signal for each bit is constituted by one or a plurality of latch gates, and the signal input terminal of the latch gate has its own complementary signal. Since the output terminal or the true signal output terminal or the complementary signal output terminal of another latch gate is connected, and the clock terminal of the latch gate is connected to the external high frequency power supply input terminal, no external signal input is required. Instead, a 1-bit test signal that periodically changes in synchronization with a change in the high-frequency power supply input to the clock terminal is supplied to a signal output terminal of a predetermined latch gate (that is, a true signal output terminal or a complementary signal output terminal). ).

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a test signal generating circuit according to the present invention. As shown in the figure, this embodiment comprises test signal generators 1 to 1 for n bits from a test signal generator 1 for the first bit to a test signal generator 1 for the nth bit. Each of the test signal generators 1 to 1 has one test signal output terminal 2 to 2 and one power input terminal 3 to 3, and the power input terminals 3 to 3 are respectively connected to the test signal generating circuit. Are commonly connected to the power input terminal 4 of the power supply.

Each of the test signal generators 1 to 1 has the same configuration. As shown in the circuit diagram of FIG. 2, any one test signal generator 1 has m D-type flip-flops (latch gates). 6 to 6 (where m is 1 or an integer of 2 or more), and the true signal output terminals Q of the latch gates 6 to 6 other than the last stage among the latch gates 6 to 6 are connected to the latch gates 6 to 6 of the next stage. The true signal output terminal Q of the last-stage latch gate 6 is connected to the test signal output terminal 2, and its complementary signal output terminal Q bar is connected to the signal input terminal D of the first-stage latch gate 6. And the clock input terminals C of all the latch gates 6 to 6
Are commonly connected to the power input terminal 4 of the test signal generation circuit via the power input terminal 3 of the latch gate. That is, the test signal generator 1 constitutes a feedback shift register including m latch gates 6 to 6.

Next, the operation of the test signal generator 1 will be described. First, high-frequency power, for example, a high-frequency trapezoidal wave, is supplied from the power input terminal 4 via the power input terminal 3 to each clock terminal of the latch gates 6 to 6 as a clock. As a result, a complementary signal is output from the last-stage latch gate 6 in the first clock. In the next clock, the complementary signal output from the last-stage latch gate 6 is received, and a signal is output from the true signal output terminal Q of the first-stage latch gate 6. In response to this output signal, a signal is output from the signal output terminal Q of the second-stage latch gate 6 at the next clock. According to such an operation principle, an output of "0" that continues m times and an output of "1" that continues m times are alternately output from the true signal output terminal Q of the last-stage latch gate 6. Therefore, the signal S output to the output terminal 2 of the test signal generator 1 is a signal having a cycle of 2m times the clock cycle. This test signal generator 1
No external signal input is required.

In this embodiment, as shown in FIG. 1, n test signal generators 1 for performing the above-described operations are arranged in parallel from 1 to 1. Here, these test signal generators 1, 1,. . . , The number of latch gates constituting the feedback shift register in m is m,
m,. . . , M, the output signals S1 to Sn of the n-bit test signal generation circuit are m, m,. . . , M is a periodic signal having a period twice as long as the least common multiple of m. Therefore, the number of latch gates m, m,. . . , M, various test pattern signals can be generated.

The test signal generating circuit according to the present embodiment
Since no external signal input is required, there is no need to prepare an expensive semiconductor high-frequency pulse pattern generator. Further, since the test signal generation circuit of this embodiment is configured using a Josephson device, it is possible to generate a high-speed test pattern which cannot be realized by a conventional semiconductor device. Also, since the test signal generation circuit can be manufactured on the same chip as the circuit under test,
The test signal does not propagate through long transmission lines, and as a result, there is no signal attenuation or distortion, and it is easy to synchronize the signal with the power supply.

Further, in the test signal generating circuit according to this embodiment, the operating time during one clock is equal to the operating time of one latch gate regardless of the number of bits. Is also short. This is because at least one logic gate or memory cell must be included between latch gates in order to form a circuit having any logic function or memory function. Therefore, by using the test signal generation circuit of this embodiment, it is possible to perform a high-speed operation test up to the maximum performance region of the circuit under test.

Further, according to the test signal generating circuit of this embodiment, since only the power supply device needs to be used as an external device, the measuring system is simplified and the high-speed test can be easily performed. . Since there is no need to input a high-speed signal from a room temperature section through a long cable, there is no problem such as multiple reflection or crosstalk at the connector section.

[0030]

Next, an embodiment of the present invention will be described. FIGS. 3A and 3B are a schematic configuration diagram and a diagram showing output changes of the first embodiment of the present invention, respectively. In the first embodiment shown in FIG. 3A, n = 3 and the k-th bit (k =
1, 2 and 3) are configured to use two latch gates. That is, the first embodiment includes the test signal generators 1 to 1 for three bits from the test signal generator 1 for the first bit to the test signal generator 1 for the third bit. Each of the test signal generators 1 to 1 has one test signal output terminal 2 to
2 and one power input terminal 3 to 3, and each of the power input terminals 3 to 3 is commonly connected to a power input terminal 4 of the test signal generation circuit. The power input terminal 4
For example, a trapezoidal wave having a high frequency up to about 10 GHz is input as a high-frequency power supply.

The test signal generator 1 includes one D-type flip-flop (latch gate) 7. The test signal generator 1 includes two D-type flip-flops (latch gates) 8 and 8. The signal generator 1 includes four D-type flip-flops (latch gates) 9 to 9. The true gate output terminal Q of the latch gate 7 in the test signal generator 1 is connected to the test signal output terminal 2 of the first bit, the complementary signal output terminal Q bar is connected to the signal input terminal D, and The clock input terminal C is connected via the power input terminal 3 to the power input terminal 4 of the test signal generation circuit.

In the test signal generators 1 and 1, 2
Among the four or four latch gates, the true signal output terminal Q of the latch gate other than the last stage is connected to the signal input terminal D of the next stage latch gate, and the true signal output terminal Q of the last stage latch gate is connected to the test signal. Connected to the output terminals 2 and 2, the complementary signal output terminal Q bar is connected to the signal input terminal D of the first-stage latch gate, and the clock input terminals C of all the latch gates are connected to the power input terminals of the latch gates. It is configured to be commonly connected to the power input terminal 4 of the test signal generation circuit via the third and third circuits.

In this embodiment, as can be seen from the description of the above embodiment, the test signal output terminal 2 of the test signal generator 1 of the k-th bit is set to "0" which lasts for two clock inputs. Lasts between the output and the two clock inputs "
1 "output is alternately and repeatedly output. Therefore, in this 3-bit test signal generation circuit, the first, second, and third bits output from the output terminals 2, 2, and 2 are output. Output signals S1, S2 and S3 of FIG.
(B), and as shown by the arrows, the test signal generators 1, 1, and 1 repeat twice at least the least common multiple of the number of latch gates 1, 2, and 4, ie, every eight clock periods. Generate a test signal pattern.

Since this test signal pattern includes all combinations of 3-bit signals, a test signal pattern signal required for a complete operation test of the circuit under test can be generated. This embodiment also has the same effect as the above embodiment. Further, as can be easily understood from a comparison between the present embodiment and the conventional test signal generation circuit, in this embodiment, 3
A total of 7 bits are required to construct a test signal generation circuit for bits.
Latch gates may be used.
Since eight latch gates and a ROM array must be used to form a bit test signal generation circuit, this embodiment has the effect of reducing the area and power consumption as compared with the conventional example.

Next, a second embodiment of the present invention will be described. FIGS. 4A and 4B are a schematic configuration diagram and a diagram showing output changes of a second embodiment of the present invention, respectively. Figure (A)
3A, the same components as those in FIG. 3A are denoted by the same reference numerals. In the second embodiment shown in FIG. 4A, n = 3 and
The test signal generator of the k-th bit (k = 1, 2, 3) has a configuration using P latch gates. Here, P is the k-th prime number.

In the second embodiment, the test signal generator 1 of the first bit to the test signal generator 1 'of the third bit are used.
And test signal generators 1, 1 and 1 'for three bits. The test signal generators 1, 1, and 1 '
Have one test signal output terminals 2 to 2 and one power input terminal 3 to 3, respectively. The power input terminals 3 to 3 are commonly connected to the power input terminal 4 of the test signal generation circuit. ing. Note that a trapezoidal wave of a high frequency up to, for example, about 10 GHz is input to the power input terminal 4 as a high-frequency power.

The test signal generator 1 includes one D-type flip-flop (latch gate) 7, and the test signal generator 1 includes two D-type flip-flops (latch gates) 8 and 8. The signal generator 1 'includes three D-type flip-flops (latch gates) 9 to 9. The test signal generator 1 has the same configuration as that of FIG.

In the test signal generators 1 and 1 ',
Of the two or three latch gates, the true signal output terminal Q of the latch gate other than the last stage is connected to the signal input terminal D of the next stage latch gate, and the true signal output terminal Q of the last stage latch gate is tested. The signal output terminals 2 and 2 are connected to each other, the complementary signal output terminal Q is connected to the signal input terminal D of the first-stage latch gate, and the clock input terminals C of all the latch gates are connected to the power input of the latch gate. Power input terminal 4 of the test signal generation circuit via terminals 3 and 3
Are connected in common.

In this embodiment, as can be understood from the description of the above embodiment, the test signal output terminal 2 of the test signal generator 1 of the k-th bit outputs "0" which continues for P times of clock input. Lasts between output and P clock inputs "
1 "output is alternately and repeatedly output. Therefore, in this 3-bit test signal generation circuit, the first, second, and third bits output from the output terminals 2, 2, and 2 are output. Output signals S1, S2 and S3 of FIG.
(B), the cycle as a 3-bit test signal is determined by the number of latch gates 1 (= P), 2 (= P), and 3 (= P) in each of the test signal generators 1, 1, and 1 ′. ), Ie, 12 clock cycles.

Since this test signal pattern includes all combinations of 3-bit signals, a test signal pattern necessary for a complete operation test of the circuit under test can be generated. This embodiment also has the same effects as the first embodiment. Further, in this embodiment, the test signal generation circuit can be configured with a smaller number of latch gates than in the first embodiment, so that the power consumption and the area occupied by the test signal generation circuit can be further reduced than in the first embodiment. There is also an effect.

It should be noted that the present invention is not limited to the above embodiments and examples, and the true signal output from the true signal output terminal of the latch gate and the complementary signal output from the complementary signal output terminal are different from each other. Since the polarities are simply reversed, for example, of the test signal generators shown in FIGS. 2, 3A and 4A, a test signal generator composed of a feedback shift register May be connected to the 1-bit test signal output terminals 2 and 2 of the final stage latch gates 6, 9 or 9.

Although the above embodiment is an example in which n = 3, it goes without saying that the number of n is not limited to this. In the above embodiment, in order to generate all the patterns, the k-th bit (k = 1 to n) test signal generator of the n-bit test signal generator is set to 2 bits.
However, the present invention is not limited to this, and if it is not necessary to generate all the patterns, for example, the k-th bit may be used. May be configured as a feedback shift register composed of k latch gates.

Further, of the plurality of test signal generators, a test signal generator constituted by a feedback shift register comprising a plurality of latch gates is connected to the other latches except the last one of the plurality of latch gates. A complementary signal output terminal of a desired one of the gates is connected to a signal input terminal of the next-stage latch gate, and a true signal output terminal or a complementary signal output terminal of the last-stage latch gate is a 1-bit test signal output. Terminals, the true signal output terminal of the last-stage latch gate is connected to the signal input terminal of the first-stage latch gate, and each clock terminal of multiple latch gates is commonly connected to an external high-frequency power input terminal. Is also good.

In this case, even in the case of a feedback shift register having the same number of latch gates, the difference is made by making the middle latch gate whose auxiliary signal output terminal is connected to the signal input terminal of the next latch gate different. Since a test signal of a pattern can be generated, at least two test signal generators of the plurality of test signal generators are
It can be constituted by a feedback shift register including the same number of latch gates.

[0045]

As described above, according to the present invention,
The test signal generation unit does not require any signal input from the outside, and a 1-bit test signal that periodically changes in synchronization with a change in the high-frequency power supply input to the clock terminal is supplied to a predetermined latch gate. Because it was configured to be able to output from the signal output terminal of, there is no need to prepare an expensive semiconductor high-frequency pulse pattern generator,
Since the configuration is made using a Josephson device, a high-speed operation test of a circuit under test can be performed by generating a high-speed test pattern that cannot be realized by a conventional semiconductor device.

Further, according to the present invention, a test signal generation circuit can be manufactured on the same chip as the circuit under test, so that the test signal does not propagate through a long transmission line, and as a result, the signal There is no attenuation or distortion, and it is easy to synchronize the signal with the power supply.

Further, according to the present invention, the operating time during one clock is equal to the latch gate 1 regardless of the number of bits.
Since the operation time is equal to the operation time of any circuit under test, it is shorter than the operation time of any circuit under test, and the semiconductor device or test signal generation circuit itself does not limit the clock frequency of the operation test,
High-speed operation tests can be performed up to the maximum performance region of the circuit under test.

Further, according to the present invention, since only a power supply device may be used as an external device, the measurement system is simplified, a high-speed test can be easily performed, and a high-speed signal is input from a room temperature section through a long cable. Therefore, there is no problem such as multiple reflection or crosstalk at the connector.

Further, according to the present invention, the ROM array required in the conventional test signal generation circuit is not required, and the number of latch gates can be reduced, so that the area is smaller than that of the conventional test signal generation circuit. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a test signal generation circuit according to the present invention.

FIG. 2 is a schematic circuit diagram of an embodiment of a test signal generator in FIG.

3A and 3B are a schematic configuration diagram and a diagram showing an output change of the first embodiment of the present invention.

FIG. 4 is a diagram showing a schematic configuration diagram and a change in output of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of an example of a conventional test signal generation circuit and a diagram showing an output change.

[Explanation of symbols]

1, 1, 1 ′ Test signal generating section 2-2 Test signal output terminal 3 -3 Power input terminal of test signal generating section 4 Power input terminal 6 ６ 6, 7, 8, 8, 9 ９ 9 Latch gate ( D-type flip-flop)

Claims (6)

(57) [Claims] 1. A test signal generation circuit for generating a test signal of each bit constituting a test signal of a plurality of bits from a plurality of test signal generation units, respectively. And a feedback shift register including one latch gate or a plurality of latch gates, and a clock terminal of each of the latch gates constituting each test signal generating unit is commonly connected to an external high frequency power supply input terminal. And a test signal generating circuit, wherein a signal output terminal of a predetermined one of the latch gates constituting each of the test signal generating sections is connected to a 1-bit test signal output terminal. 2. A test signal generator comprising a feedback shift register comprising a plurality of latch gates among the plurality of test signal generators, except for a last-stage latch gate among the plurality of latch gates. Connecting the true signal output terminal of the other latch gate to the signal input terminal of the next-stage latch gate, connecting the complementary signal output terminal of the last-stage latch gate to the signal input terminal of the first-stage latch gate,
Connecting a true signal output terminal or a complementary signal output terminal of the last-stage latch gate to the 1-bit test signal output terminal;
A test signal generator configured by connecting one clock terminal of the plurality of latch gates to the external high-frequency power supply input terminal in common;
The complementary signal output terminal of the latch gate is connected back to the signal input terminal, and the true signal output terminal or the complementary signal output terminal is
2. The test signal generating circuit according to claim 1, wherein the test signal generating circuit is connected to a bit test signal output terminal, and a clock terminal is connected to the external high frequency power supply input terminal. 3. The test signal generation circuit according to claim 2, wherein the k-th bit test signal generation unit among the plurality of test signal generation units is constituted by two latch gates. 4. The test signal generator of the k-th bit among the plurality of test signal generators is configured by a number of latch gates equal to the k-th prime number. Test signal generation circuit. 5. A test signal generator comprising a feedback shift register comprising a plurality of latch gates among the plurality of test signal generators, excluding a last-stage latch gate among the plurality of latch gates. A complementary signal output terminal of a desired one of the other latch gates is connected to a signal input terminal of a next-stage latch gate, and a true signal output terminal or a complementary signal output terminal of the last-stage latch gate is connected to the 1st latch gate. Bit test signal output terminal, the true signal output terminal of the last-stage latch gate is connected to the signal input terminal of the first-stage latch gate, and each clock terminal of the plurality of latch gates is connected to the external high-frequency power supply. 2. The test signal generating circuit according to claim 1, wherein the test signal generating circuit is commonly connected to an input terminal. 6. The method according to claim 1, wherein one or more latch gates constituting the plurality of test signal generators are configured using a Josephson device. The test signal generation circuit according to claim 1.