JP2853722B2 - Subband encoding / decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subband encoding / decoding apparatus.

[0002]

2. Description of the Related Art In recent years, a sub-band encoding method has been proposed as an information compression / expansion method. The outline of this method is
On the transmitting side, information signals such as audio signals and video signals are converted into quadrature mirror filters (hereinafter referred to as “QM
F), divided into low and high frequency bands, 2: 1 sub-sampling is performed for each band,
The encoding is performed for each band, and the encoding method includes simple quantization, nonlinear quantization, DPCM, DCT
For example, the method is described in “Image Information Compression” edited by the Institute of Television Engineers of Japan 1991 Ohmsha (hereinafter abbreviated as Document 1). Further, the same encoding may be performed on the low-frequency data after the frequency band division into low frequency and high frequency using QMF and sub-sampling are repeated. Then, the receiving side decodes each band,
The information signal is reproduced using the inverse QMF.

[0003] As described above, the sub-band coding system can divide the band in the frequency band without increasing the entire data amount, and can select an appropriate coding method for each band. This is an encoding method.

On the other hand, filters used for dividing a frequency band are not necessarily limited to QMF. As an example, “New construction method of distortion-free filter in subband division” IEICE Technical Report IE
89-98 (FEB, 1990) (hereinafter abbreviated as Document 2) is known. In addition, it may be configured to repeat frequency band division and sub-sampling a plurality of times. "Study of Sub-band Coding Method" Inoue et al. 1991 6th Image Coding Symposium (PCSJ) 7-2, page 169 (hereinafter abbreviated as reference 3). The present invention relates to an improvement of a filter used for dividing a frequency band. Hereinafter, a conventional example of the subband encoding method will be described in detail.

FIG. 9 is a block diagram of a conventional sub-band division system, FIG. 10 is a block diagram of a transmission side in FIG. 9, and FIG. 11 is a block diagram of a reception side in FIG. Hereinafter, description will be made with reference to the drawings. In the following description, "n" is n = ...-
It is an integer of 2, -1,0,1,2….

In FIG. 9, an input information signal sequence XI (n), which is a digital signal, is supplied to a first digital filter H (z) 1 for extracting low frequency components and a multiplier 2 having a multiplier a. You. This first digital filter H (z)
Is supplied to one input of a subtractor 3 and the signal sequence obtained via a multiplier 2 supplied to the other input is subtracted from the first low-frequency information signal XL1 (n). Thus, a first high-frequency information signal sequence XH1 (n) having a high-frequency component is obtained. Then, the frequency-divided first low-frequency information signal sequence X
L1 (n) and the high-frequency information signal sequence XH1 (n) are supplied to first and second decimators 5 and 4 for performing sub-sampling, respectively.
An output signal sequence from which data is decimated for each sample is converted into first and second output signals through an encoder, a transmission path, and a decoder (not shown).
Are supplied to the interpolators 7 and 6, respectively.

[0007] These first and second interpolators 7 and 6 insert "0" data into the input signal sequence for each sample, and set a sampling rate equal to the input information signal sequence XI (n). The resulting second low-frequency information signal sequence XL2 (n) and the second high-frequency information signal sequence XH2 (n) are supplied to the adder 8, respectively. Then, both inputs are added by the adder 8, and the output signal sequence is supplied to one of the subtracters 10 via the second digital filter G (z) 9. Then, the output signal sequence of the second digital filter G (z) 9 is subtracted from the second low-frequency information signal sequence XL2 (n) supplied to the other input of the subtracter 10, and the output information signal sequence XO ( n).

The condition of so-called perfect reconstruction in which the output information signal sequence XO (n) becomes the same signal sequence as the input information signal sequence XI (n) with a delay of several samples in the above configuration is described in the above-mentioned reference 2. Equation 1 has been derived.

[0009]

(Equation 1) Further, the first and second digital filters H (z), G
The filter coefficient (unit impulse response) of (z) is h
In the digital filter represented by Expression 2 as (n) and g (n), the condition of Expression 1 is Expression 3 and Expression 4.

[0010]

(Equation 2)

[0011]

(Equation 3)

[0012]

(Equation 4) Now, as a practically important example, when a constraint condition that H (z) is a low-pass filter of a phase straight line is provided,
(Z) is a coefficient symmetric FIR filter with an odd number of taps. That is, when the filter order is 2M + 1, H (z)
Is given by Equation 5.

[0013]

(Equation 5) The condition of Equation 3 at this time is Equation 6.

[0014]

(Equation 6) Also, G (z) is the same as in H (z),
Is derived.

[0015]

(Equation 7)

[0016]

(Equation 8) Using the above results and rewriting FIG. 9 with M = 3,
The transmitting side in FIG. 9 is shown in FIG. 10, and the receiving side is shown in FIG.

In FIG. 10, the first digital filter H
(Z) The configuration of 101 to 106 in 1 is a register for delaying data by one sampling period.
-110 are multipliers and input data have coefficients h
(3) and h (1) are multiplied and output. Also, 11
An adder 1 supplies output data obtained by adding the input data to the subtractor 3 and the first decimator 5, respectively.

On the other hand, in FIG. 11, the configuration of 901 to 906 in the second digital filter G (z) 9 is a register for delaying data for one sampling period, and the configuration of 907 to 911 is a multiplier. The input data is multiplied by coefficients g (3), g (1), -1/2 and output. An adder 912 supplies the output data obtained by adding the input data to the subtractor 10.

[0019]

The amplitude frequency characteristic H (wT) of the first digital filter H (z) is expressed by the ideal half band expressed by the following equation 9 even under the constraints of the equation 6. The filter coefficient h (n) can be set so as to be sufficiently close to the amplitude frequency characteristic H '(wT) of the filter. For example, h (n) is expressed by Equation 1 using w (n) as a window function.
It can be represented by 0.

[0020]

(Equation 9)

[0021]

(Equation 10) Therefore, the first low-frequency information signal sequence XL1 (n) in FIG. 9 can be a signal sequence whose band is sufficiently limited and whose phase characteristics are not distorted. Reference 2 describes that better frequency selection characteristics can be obtained with the same number of multiplications as compared with other subband splitting filters such as QMF.

On the other hand, the first high-frequency information signal sequence XH1 (n) has a characteristic H2 (z) of a high-pass filter composed of a multiplier 2 having a multiplier of "2", H (z) and a subtractor 3. ) Is represented by the following equation 11, but cannot be a phase straight line.

[0023]

[Equation 11] In particular, in the configuration of FIG. 10, when the delay amount of the digital filter H (z) is M (when the order of the filter is 2M + 1, the delay amount is M), the first high-frequency information signal sequence XH1
(n) is a signal sequence obtained by delaying the input information signal sequence XI (n) by M sampling timings via H (z) from a signal sequence obtained by multiplying the input information signal sequence XI (n) by a (= 2). Will be the difference.

Here, H (z) has characteristics sufficiently close to those of an ideal half-band filter, and the input information signal sequence XI
Considering the case where (n) has only the frequency components of Expression 12, the first low-frequency information signal sequence XL1 (n) becomes Expression 13.

[0025]

(Equation 12)

[0026]

(Equation 13) Further, the first high-frequency information signal sequence XH1 (n) is represented by Expression 14.

[0027]

[Equation 14] Since XI (nM) is a signal sequence shifted from the input information signal sequence XI (n) by M sampling timings, XI (nM) and XI (n)
Is not necessarily equal to Therefore, the first high-frequency information signal sequence XH1 (n) has a considerable amount of information even under such conditions.

This means that the first high-frequency information signal sequence XH1 (n) and the first low-frequency information signal sequence XL1 (n) obtained by dividing the frequency band in the configurations shown in FIGS. Is disadvantageous when the amount of information is compressed by sub-sampling the output signal sequence and encoding the output signal sequence by any method.

[0029]

SUMMARY OF THE INVENTION The present invention provides the following structure to solve the above problems.

In a sub-band coding apparatus for processing by dividing an input information signal sequence into frequency bands of a low band and a high band,
A first digital filter H (z) that receives the input information signal sequence and outputs a first information signal sequence, a first delay unit that delays the input information signal sequence for a predetermined period, Third digital filter F to which an information signal sequence is input
(Z), subtraction means for outputting a second information signal sequence obtained by subtracting the output signal sequence of the third digital filter from the output signal sequence of the first delay means, and the first information A first decimator for performing subsampling on the signal sequence and a second decimator for performing subsampling on the second information signal sequence, wherein predetermined encoding is performed on output signal sequences of the first and second decimators; A sub-band encoding device for outputting a signal sequence obtained by performing a process, wherein the first digital filter H
(Z) is specified by equations (26) and (27), and the third digital filter F (z) is specified by equations (28) and (29).

According to a first aspect of the present invention, there is provided a sub-band decoding apparatus to which an output signal sequence output from the sub-band encoding apparatus is inputted, the third one corresponding to the first decimator.
A first interpolator that outputs a fourth information signal sequence corresponding to the second decimator, and a second interpolator that outputs a fourth information signal sequence. A second delay means for delaying by the same delay time as the delay time of the means, the third information signal sequence being input, and having the same input / output characteristics as the third digital filter F (z). A fourth digital filter, an adding means for adding and outputting an output signal sequence of the fourth digital filter and the fourth information signal sequence, and a second digital filter having the output signal sequence of the adding means as an input G (z), wherein the output signal sequence of the second digital filter G (z) is subtracted from the output signal sequence of the second delay means to output an output information signal sequence. And the second
Wherein the digital filter G (z) is specified by Expressions 30 and 31.

3. The sub-band encoder according to claim 1, wherein when the input information signal sequence sampled every predetermined time T is input, the first digital filter H (Z) and / or a filter operation of the third digital filter F (z) is performed every 2 · T time.

3. The sub-band decoding apparatus according to claim 2, wherein when outputting an output information signal sequence sampled every predetermined time T, the second digital filter G
Subband decoding characterized in that the filter operation of (z) excluding the filter coefficient g (0) and / or the filter operation of the fourth digital filter F (z) is performed every 2.T time. Device.

[0034]

(First Embodiment) FIG. 1 is a block diagram for explaining an embodiment of a subband encoding / decoding apparatus according to the present invention, and FIG. 2 is an embodiment of a subband encoding / decoding apparatus according to the present invention. FIG. 3 is a block diagram for explaining an embodiment, FIG. 3 is a block diagram for explaining an embodiment of a subband decoding apparatus according to the present invention, and FIG. 4 is a diagram for explaining a filter F (z). . Embodiments will be described below with reference to the drawings. The same components as those in FIGS. 9, 10, and 11 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is different from FIG. 9 in that first and second delay registers 11 and 12 and third and fourth digital filters 13 and 14 having F (z) characteristics are provided. Is a point. Here, Z ^-J indicates that the input signal train is delayed by the J sampling timing. That is, an input information signal sequence XI supplied from a transmission line (not shown)
(n) becomes XI (nJ) via the delay register 11. A digital filter F (z), which will be described later, is a filter for obtaining an approximate value of odd-numbered or even-numbered data removed by the first decimator 5 from the first low-frequency information signal sequence XL1 (n) by interpolation. is there.

The delay time L of the third and fourth digital filters F (z) is equal to the odd sampling timing, similarly to the delay time M of H (z). The delay time J of the first and second delay registers 11 and 12 is J = M +
L should be satisfied. Therefore, J is an even natural number. Since the multiplier 2 merely multiplies the multiplier, the multiplier 2 may be included in the first delay register 11 as a matter of course.

FIG. 2 corresponds to FIG. 10 in which a first delay register 11 and a third digital filter F (z) 13 are added. Here, the order of the H (z) filter is 2M + 1 = 7. Further, F (z) is set to Expression 15, and the order of the filter is set to 2L + 1 = 3. Further, the delay time J of the first delay register 11 is set to J = M + L = 4. However, in FIG. 2, the first delay register 11
Are also used as H (z) registers.

Similarly, FIG. 3 corresponds to FIG. 11, in which a second delay register 12 and a fourth digital filter F (z) 14 are added. In FIG. 3, the second delay register 12 is also used as a register of the fourth digital filter F (z) 14.

In FIG. 2, the first low-frequency information signal sequence XL1 (n) is the same as the conventional example shown in FIG. On the other hand, the first high-frequency information signal sequence XH1 (n) is 1 in 1
The input information signal sequence XI (n) is converted to J (=
4) The output signal sequence of the third digital filter F (z) 13 is subtracted by the subtracter 3 from the signal sequence delayed by the sampling timing. At this time, the delay time from the input to the output of the third digital filter F (z) 13 is equal to J as described above.
Since the output signal sequence (z) is sufficiently close to the first low-frequency information signal sequence XL1 (n), the first high-frequency information signal sequence XH1
(n) is a signal sequence substantially equal to a signal sequence obtained by subtracting the first low-frequency information signal sequence XL1 (n) from the input information signal sequence XI (n) without phase delay. Therefore, the first high-frequency information signal sequence XH1 (n)
Most of the information included in the information has a high-frequency signal component, and the amount of information can be reduced as compared with the related art.

Here, the third and fourth digital filters F
(Z) will be described in detail with reference to FIG. 4. FIG. (A) shows a first low-frequency information signal sequence XL1 (n), and FIG. (B) shows a first decimator 5 with 2: 1 illustrates a part of a signal sequence where sub-sampling is performed to remove odd-numbered signal sequences, and thereafter, 0 data is inserted every other sample by the first interpolator. . The third and fourth digital filters F (z) are for obtaining an approximate signal sequence of the odd-numbered signal sequence in FIG. 6A from the even-numbered signal sequence shown in FIG. Since the first and second digitizers 5 and 4 perform sampling at the same phase, the output of the second digitator is obtained by subtracting the approximate signal sequence of the odd-numbered signal sequence from the corresponding input signal sequence.

Now, assuming that the first digital filter H (z) is an ideal half-band filter, the frequency band of the first low-band information signal sequence XL1 (n) is limited to 1/4 of the sampling rate. Therefore, the first low-frequency information signal sequence XL1
(n) is sub-sampled 2: 1 and the original first low-band information signal sequence XL1 (n) is obtained by using an ideal half-band filter from a signal in which 0 data is inserted every other sample.
Can be completely restored. In other words, the signal shown in FIG. 9C can be completely restored by passing the signal train shown in FIG. 10B through the ideal half-band filter F (z).

As described above, F (z) is an approximation of the ideal half-band filter. Further, when F (z) is represented by Expression 15, the filter coefficient f (n) satisfies Expression 16. For f (n) other than n = 0, for example, w (n)
Is a window function.

[0043]

(Equation 15)

[0044]

(Equation 16)

[0045]

[Equation 17] The reason why f (0) = 0 in Equation 16 is that the first low-frequency information signal sequence XL1 (n) before subsampling at 2: 1 is input as the input of F (z). . In the present embodiment, as the simplest example as shown in FIG. 2, f (1) = f (-1) = 1
/ 2.

Here, a description will be given of the fact that complete reconfiguration is possible in the configurations of FIGS. 1, 2 and 3 as in the prior art.
First, consider the case where F (z) = 1 in FIG. However, in this case, since L cannot be determined, J is a predetermined even number. In such a case, the conditions of the complete reconstruction corresponding to the equation 1 are the same as those of the conventional example, in addition to the first and second delay registers 11,
Since there are 12, Expression 18 is obtained, and when J is an even number, Expression 19 is obtained.

[0047]

(Equation 18)

[0048]

[Equation 19] Therefore, complete reconstruction can be realized by setting the filter coefficients of H (z) and G (z) so as to satisfy Equations 6 and 8 as in the conventional example.

Next, it will be described with reference to FIGS. 2 and 3 that the complete reconstruction is established even when F (z) is not equal to 1. Referring to FIG. 2 on the transmitting side, F (z) in FIG. The first low-frequency information signal sequence XL1 (n) is represented by Expression 20, and matches the conventional example. On the other hand, the first high-frequency information signal sequence XH1 (n) is represented by Expression 21.

[0050]

(Equation 20)

[0051]

(Equation 21) Then, the first low-frequency information signal sequence XL1 (n) and the first high-frequency information signal sequence XH1 (n) are sub-sampled by the first and second decimators 5 and 4 at a ratio of 2: 1. In the first and second interpolators 7 and 6 shown in FIG. 3, "0" data is inserted between the signal trains to produce a second low-frequency information signal train XL2.
(n) becomes the second high-frequency information signal sequence XH2 (n). here,
In the second high band information signal sequence XH2 (n), the inserted "0"
If one of the non-data is XH2 (k),
Equation 22 is derived in the same manner as 1.

[0052]

(Equation 22) XL1 (k) and XL1 (k-2) in Equation 22 are both signal trains XL2
It is obvious that the data is not the inserted "0" data in (n), and is represented by Formula 23.

[0053]

(Equation 23) Then, as shown in FIG. 3 on the receiving side, the output of the filter F (z) having XL2 (n) as input and XH2 (n) are added by the adder 8, and the result is expressed by equation 24. 3 of the high frequency information signal sequence XU (n).

[0054]

(Equation 24) Substituting n = k and equations 22 and 23 into equation 24 gives equation 2
It becomes 5.

[0055]

(Equation 25) On the other hand, when the above-mentioned F (z) = 1, the third high-frequency information signal sequence XU (k) is obtained. In Expressions 21 to 25, XL1 (n-2),
It is sufficient to consider except for XL1 (k-2) and XL2 (k-2), and it is clear that the result is equal to the equation (25). Since the second low-frequency information signal sequence XL2 (n) is the same in the case of F (z) = 1 and in FIGS. 2 and 3, Xo (n) which is the output of the subband encoding device is used. Are the same in the case of F (z) = 1 and in the cases of FIGS. Therefore, it can be seen that complete reconfiguration can be realized by the configurations of FIGS. Although the cases of FIGS. 2 and 3 have been described above, it is similarly apparent that F (z) satisfying Expression 16 is generally satisfied.

As described above, it is possible to provide a sub-band encoding / decoding apparatus which realizes complete reconstruction with a simple configuration.

Now, referring to FIGS. 5 and 6, FIG.
The configuration of the block diagram of FIG. 3 will be described in further detail.

Here, the delay means Z- ¹ is realized by the register (for example, 85) shown in FIGS. In the figure, D is an input terminal having a predetermined number of bits, Q is an output terminal having the same number of bits, and C is a clock input terminal. The input data is latched and output at the rise of the clock signal input to C to "H", and the data is stored and held until the next rise to "H". That is, this register is a collection of a predetermined number of D-type flip-flops. Also, 81 and 8 in FIGS.
Reference numeral 2 denotes a JK type flip-flop, and a clock HCK obtained by dividing the clock CK input to C is output from Q. The registers 83 and 84 shown in FIG. 5 operate on the HCK, and are set to 1/1/1 of the sampling rate of the input information sequence.
At a rate of 2, input data is latched and output. That is, each of the decimators 5 and 4 in FIG. 2 is realized. The first digital filter H (z) 1 uses two multipliers of multipliers h (1) and h (3) in FIG. 2, but here, the addition is performed first and then the multiplication is performed. The configuration reduces the number of multipliers.
The adder is realized by using a plurality of two-input adders. Note that the register 85 in FIG. 6 is not shown in FIG. 2 and is not always necessary, but is added to adjust the timing of the input information sequence. CK in FIGS. 5 and 6 is a clock corresponding to the sampling rate of the input information sequence XI (n), and the rising timing of this CK and the divided HCK is sufficiently earlier than the propagation delay time of the register. Shall be.

The selectors 71 and 72 in FIG. 6 implement the interpolators 7 and 6 in FIG. Selector 7
Reference numerals 1 and 72 select and output the A input when the 1-bit signal to be input to S is "H", and select and output the B input during the "L" period. A, B and Q are all multi-bit terminals. 0 value is input to B,
A clock HCK obtained by dividing the clock CK corresponding to the sampling rate of the input information sequence XI (n) is input to S. For the digital filter G (z),
The configuration is the same as the configuration of H (z) in FIG. Although the registers 87 to 89 are not shown in FIG. 3 and are not always necessary, they are added to adjust the timing of the input information sequence and the output information sequence. (Second
(Embodiment) The second embodiment is a further improvement of the sub-band coding / decoding device described in FIGS. 5 and 6 in the first embodiment.

In the encoder of FIG. 5, the filter operation of the first digital filter H (z) 1 is performed by the input information signal sequence XI
It is performed for each clock of the clock CK corresponding to the sampling rate of (n). That is, when an information sample is input to the encoder every predetermined time T (T is a real number), the filter operation of H (z) 1 is performed once every T time. This is the third digital filter F (z) 1
The same applies to No. 3. Therefore, it is necessary to provide an adder and a multiplier that constitute a digital filter that can operate at a relatively high speed. Generally, an adder and a multiplier that can operate at high speed consume large power or have a large circuit scale. In order to construct F (z) 13,
Two registers driven by the clock CK are used.

On the other hand, in the decoder of FIG. 6, the filter operation of the fourth digital filter F (z) 14 and G (z) 9 corresponds to the sampling rate of the input information signal sequence XI (n). It is performed for each clock CK. Therefore, an adder constituting a digital filter,
It is necessary to provide a multiplier that can operate at high speed. Further, registers driven by a relatively large number of clocks CK are used for the F (z) 14 and G (z) 9 and the delay means Z- ^J12 .

As described above, the subband encoding / decoding devices described with reference to FIGS. 5 and 6 have problems such as an increase in circuit scale and power consumption.

Therefore, in the second embodiment, only every other data of the first low-band information signal sequence XL1 (n) and the first high-band information signal sequence XH1 (n) is initially encoded by the encoder. The second and fourth digital filters G (z), F (z), the second digital filter G (z), the second digital filter G (z), the second digital filter G (z),
, The configuration for inputting to the delay register Z- ^J is simplified, and a filter operation and a delay means corresponding to the inserted 0 data are omitted.

FIG. 7 is a block diagram of a sub-band encoder according to another embodiment of the present invention, and FIG. 8 is a block diagram of a sub-band decoder according to another embodiment of the present invention.
Embodiments will be described below with reference to the drawings. The same components as those in FIGS. 5 and 6 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 7, it is assumed that one sample of the input information signal sequence XI (n) is input to the encoder every time T. It is assumed that the frequency 1 / T is equal to the sampling rate when an audio signal, an image, and the like are digitized to form an information signal sequence XI (n).

The configuration of the encoder shown in FIG. 11 differs from the encoder shown in FIG. 5 in the following points. That is, one of the registers constituting the third digital filter F (z) 13 is omitted, and the clock HCK obtained by dividing the clock CK corresponding to the sampling rate of the input information signal sequence XI (n). (The cycle is 2 · T) to supply the C input of the remaining one register 135 and the C of 112 to 117 of the registers constituting the first digital filter H (z) 1. The difference is that a clock HCK is input to the input.

Accordingly, the number of registers constituting F (z) 13 is 1/2 that of the conventional example. FIG.
According to the configuration of (1), all data input to the adder and the multiplier constituting H (z) 1 are output data from the register operated by the clock HCK, and the register to which the output of H (z) 1 is input. Also operate on the clock HCK. Therefore, the H (z) filter operation need only be performed once during one HCK clock period, and only one operation is required every 2.T time.

Similarly, the third digital filter F (z)
The data input to the adder and the multiplier forming the block 13 are all output data from the register operated by the clock HCK, and the register to which the output of F (z) is input is also the register operated by the clock HCK. Therefore, F
The filter operation of (z) may be performed once in one HCK clock period.

The subband decoder will be described with reference to FIG. This sub-band decoder differs from the conventional sub-band decoder shown in FIG. 6 in the following points. That is, the point that the selectors 71 and 72 that realize the interpolator are removed, the point that one of the registers that constitute the fourth digital filter F (z) 14 is omitted, and the input information signal sequence XI
One register 1401 stores a clock HCK obtained by dividing the clock CK corresponding to the sampling rate of (n).
And the delay means Z ^-J
12, the number of registers is reduced by half, the clock HCK is input to the C input of the remaining registers 1401 and 1402, and the second digital filter G (z) 9
, The clock HCK is input to the C input of the remaining three registers 9001 to 9003, and the filter of the second digital filter G (z) Coefficient g (0) =-
The difference is that the operation relating to is separated from other operations, and that the selector 73 is provided.

Therefore, F (z), G (z)
And the number of registers constituting the delay means Z ^-J is-times. According to the configuration of FIG.
Of the adders and multipliers constituting the digital filter G (z) 9 that perform the operation except for the operation on g (0), all the data input to them are stored in the registers operating on the clock HCK. The output data is subtracted from the output of the register 1402 which also operates with the clock HCK, the selector 73 selects HCK during the “L” period, and is latched by the register 89 at the rise of the clock CK. The clock C that is latched follows the period when HCK is "L".
Since this is the rise of K, it coincides with the rise of the clock HCK. Therefore, the product-sum operation of the input information sequence and a coefficient other than g (0) of G (z) may be performed once during one HCK clock period. Similarly, for F (z), the filter operation only needs to be performed once during one HCK clock period, and one operation per 2.T time is sufficient.

On the other hand, regarding the operation regarding g (0),
As shown, a multiplier 909 is added to the output of the register 9002.
Is multiplied by the multiplier g (0) = − ／, the output is selected by the selector 73 during the period when HCK is “H”, and latched in the register 89 at the rising edge of the clock CK. This latch timing is the clock HC
It coincides with the fall of K. Therefore, the multiplier 909
Is required to operate in a period of one clock CK including the propagation delay time of the selector 73, but this operation is only multiplication, and the speeding up is easy.

In the configuration of the second embodiment as described above, in the encoder, the registers 83 and 84 corresponding to the decimators are obtained despite performing the same filter operation as in the first embodiment.
The filter operation is not performed on the data to be decimated without being latched by the above. Also, the third
The number of registers is reduced by utilizing the fact that some of the filter coefficients of the digital filter F (z) have a value of 0.

On the other hand, in the decoder, selectors 71 and 72 which realize an interpolator in the configuration of the first embodiment.
As a result, a filter operation is performed on an information sequence in which 0 values are inserted every other sample, and the filter coefficients of the second digital filters G (z) and F (z) are g
Except for (0), the operation speed of the filter operation and the number of registers are reduced by using the point that the value is 0 every other one. This is because information samples and filter coefficients having a value of 0 have no effect even if they are excluded from the product-sum operation. Therefore, the same output data can be obtained in the first and second embodiments for both the encoder and the decoder.

As described above, according to the second embodiment, when an information sample is input to the encoding device every predetermined time T (T is a real number), the digital filter H () in the encoding device and the decoding device is used. Since the filter operations of z) and F (z) are performed once every 2 · T time, it is possible to use an adder and a multiplier having a relatively low operation speed as a digital filter. is there.

The digital filter G in the decoding device
Since the product-sum operation of a coefficient other than g (0) of (z) and the input information sequence to G (z) is performed once every 2 · T time, an adder and a multiplyer constituting a digital filter are provided. It is possible to use a device whose operation speed is relatively slow as a device.

The digital filter F (z) in the encoding device and the decoding device is clocked by a clock having a period of 2 · T, and stores one sample of the information sequence. And the adder, the number of storage means can be reduced.

Further, the delay means z-J in the decoding device is constituted by J / 2 pieces of storage means which are driven by a clock having a cycle of 2 · T and store one sample of the information sequence. Therefore, the number of storage means can be reduced. Further, the digital filter G (z) in the decoding apparatus is clock-driven by a clock having a period of 2 · T, and is constituted by storage means for storing one sample of an information sequence, M pieces, a multiplier, and an adder. Therefore, the number of storage means can be reduced.

The configuration of the present invention is not limited to the above-described embodiment. For example, a digital filter H (z),
The output of the multiplier for F (z) and G (z) may be latched by a register, and the output may be input to the next-stage adder. Even in that case, C input of the register is HCK
As a result, the operation speed of the multiplier and the adder can be reduced by obtaining the output value once every 2.T time as the entire filter operation.

Further, a multiplication circuit, an addition circuit,
A so-called DSP (Digital Digital Memory) having a RAM (random access memory)
In the case where the sub-band encoding device and the decoding device according to the present invention are realized by a signal processor or the like, the amount of calculation can be reduced in the same manner as in the embodiment.

That is, the digital filters H (z), F
(Z), G (z) filter operation is performed once every 2.T time, and F (z), G (z) and delay means Z ^-J
When using a plurality of memory words in the RAM as delay means for realizing each of the above, the number of memory words is set to L, M, and J / 2, respectively.
Can be reduced.

In the first and second embodiments, the first digital filter H (z) 1 has been described as a configuration for extracting low frequency components, but it extracts high frequency components. In such a case, the “low-pass” and “high-pass” of the first and second low-frequency information signal sequences and the first, second and third high-frequency information signal sequences described above may be used. Since the above can only be reversed, it goes without saying that such a configuration may be adopted. At this time, F (z) may be an approximation of an ideal high-pass filter. However, the filter coefficient f (0) is set to 0 as described in the first embodiment.

In the first and second embodiments, the frequency band division for a one-dimensional signal has been described. However, it can be extended to a two-dimensional or three-dimensional signal by the method described in the above-mentioned well-known conventional document 2. Of course. Also,
Similar to the well-known document 3, the frequency band division and the sub-sampling may be repeated a plurality of times.

[0083]

As described above, according to the configuration of the present invention,
In particular, since the first delay means and the third digital filter are provided, the input signals of the subtraction means are approximated, so that the information amount of the second information signal sequence can be reduced with a simple configuration and complete reconstruction can be realized. There is an effect that a subband encoding device can be provided.

As described above, according to the configuration of the present invention, a subband decoding apparatus which has a simple configuration and can realize complete reconstruction is provided, especially since it has the second delay means and the fourth digital filter. There is an effect that can be.

As described above, according to the configuration of the present invention, the multipliers and the adders constituting the digital filters H (z), F (z) and G (z) are those having relatively low operating speeds. It is possible to reduce power consumption and the circuit scale.

A register constituting a digital filter F (z) of the encoder and a digital filter F of the decoder
The circuit scale can be reduced by omitting a part of each of the registers constituting (z) and G (z).

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a subband encoding / decoding device according to the present invention.

FIG. 2 is a block diagram illustrating an embodiment of a subband encoding device according to the present invention.

FIG. 3 is a block diagram illustrating an embodiment of a subband decoding device according to the present invention.

FIG. 4 is a diagram for explaining a filter F (z).

FIG. 5 is a block diagram illustrating the subband encoder of FIG. 2 in detail.

FIG. 6 is a block diagram illustrating the subband decoding apparatus of FIG. 3 in detail.

FIG. 7 is a block diagram for explaining another embodiment of the subband encoding device according to the present invention.

FIG. 8 is a block diagram for explaining another embodiment of the subband decoding device according to the present invention.

FIG. 9 is a block diagram for explaining a conventional subband division method.

FIG. 10 is a block diagram for explaining a transmitting side in FIG. 9;

FIG. 11 is a block diagram for explaining a receiving side in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st digital filter 3 subtracter (subtraction means) 4 2nd decimator 5 1st decimator 6 2nd interpolator 7 1st interpolator 8 Adder (addition means) 9 2nd digital filter 11 1st Delay register (first delay means) 12 Second delay register (second delay means) 13 Third digital filter 14 Fourth digital filter XI (n) Input information signal sequence XL1 (n) First low Area information signal sequence (first information signal sequence) XL2 (n) Second low-frequency information signal sequence (third information signal sequence) XH1 (n) First high-frequency information signal sequence (second information signal Column) XH2 (n) second high-frequency information signal sequence (fourth information signal sequence)

Continuation of front page (56) References JP-A-5-183384 (JP, A) Delebiology technique VOL. 14, NO. 29 (Technical Report of the Institute of Television Engineers of Japan [Image Communication System] (May 1990), pp. 13-18) “One Construction Method of Perfect Reconstruction Filter in Band Division Coding and Its Application to Images” THE TRANSACTIONS OF THE IEICE, VOL.E 73, NO.10 (OCT. 1990) pp. 1616-1624; A New Structure of the Perfect Reconstruction Filtration Banks for Submarine 89, No. 89, Cod. -92-98, pp.51-58 (IE89-98) IEICE Technical Report Vol.92, No.20 DSP 92-1-11, pp.59-66 (IE92-9, DSP92-9) Transactions of IEICE [B] Vol.J 71-B, No. 12, pp. 1511-1516

Claims (4)

(57) [Claims] 1. A sub-band encoding apparatus for processing an input information signal sequence by dividing the input information signal sequence into a low band and a high band, and receiving the input information signal sequence and outputting a first information signal sequence. A first digital filter H (z), first delay means for delaying the input information signal sequence for a predetermined period, a third digital filter F (z) to which the first information signal sequence is input, Subtraction means for outputting a second information signal sequence obtained by subtracting the output signal sequence of the third digital filter from the output signal sequence of the first delay means; and subsampling the first information signal sequence And a second decimator for subsampling the second information signal sequence at the same subsampling timing as the first decimator. Predetermined encoding for output signal sequence What is claimed is: 1. A sub-band encoding device for outputting a signal sequence obtained by performing a process, wherein the first digital filter H (z) includes: And the third digital filter F (z) is A subband encoding device characterized by the following. 2. A sub-band decoding device to which an output signal sequence output from the sub-band encoding device according to claim 1 is input, wherein a third information signal sequence corresponding to the first decimator is formed. A first interpolator for outputting, a second interpolator corresponding to the second decimator, for outputting a fourth information signal sequence, and a delay time of the first delay means for transmitting the third information signal sequence. A second delay means for delaying by the same delay time, a fourth digital filter to which the third information signal sequence is inputted and which has the same input / output characteristics as the third digital filter F (z) Addition means for adding and outputting the output signal sequence of the fourth digital filter and the fourth information signal sequence; and a second digital filter G (z) having the output signal sequence of the addition means as an input. And the second A subband decoding device for subtracting an output signal sequence of a second digital filter G (z) from an output signal sequence of a delay unit and outputting an output information signal sequence, wherein the second digital filter G (z) Is A sub-band decoding device characterized by the following. 3. The sub-band encoding apparatus according to claim 1, wherein when the input information signal sequence sampled at every predetermined time T is inputted, the first digital signal is inputted. Filter H (z) and / or
Alternatively, the sub-band encoding apparatus is configured to perform a filter operation of the third digital filter F (z) every 2 · T time. 4. The sub-band decoding apparatus according to claim 2, wherein when outputting an output information signal sequence sampled at predetermined time intervals T, the second digital filter G (z) The filter operation excluding the filter coefficient g (0) and / or the filter operation of the fourth digital filter F (z) is performed by 2
A sub-band decoding device characterized in that the sub-band decoding is performed every T time.