JP2852247B2 - Shared memory multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory type multiprocessor system, and more particularly to a directory type shared memory type multiprocessor system.

[0002]

2. Description of the Related Art A multiprocessor system (generally called a cluster) in which a plurality of store-in caches and shared memories are connected to one system bus,
A shared memory multiprocessor system in which a plurality of directories are connected by a directory method is realized by a known technique. For example, there are a parallel computer system using a hierarchical bus described in Japanese Patent Application Laid-Open No. 2-123361 and a tightly-coupled multiprocessor with a scalable memory band described in Japanese Patent Application Laid-Open No. 4-291446.

However, the technique disclosed in Japanese Patent Application Laid-Open No. 2-136161 does not disclose a method for guaranteeing coherency of store-in-cache between clusters. In addition, Japanese Unexamined Patent Application Publication No.
In the technique of Japanese Patent Application Laid-Open No. 291446, a crossbar (a switch that enables communication between any two clusters among a plurality of clusters connected to the cluster) is used to connect the clusters. In order to guarantee cache coherency, the same memory block is not cached at the same time between a plurality of store-in caches in a cluster or between clusters. Control.

[0004]

Problems to be Solved by the Invention
In the configuration described in Japanese Patent Application Laid-Open No. H10-157, there is a drawback that coherency of store-in cache between clusters cannot be guaranteed. In the configuration described in Japanese Patent Application Laid-Open No. 4-291446, when a configuration is used in which two systems that can operate only by a single cluster are connected, a crossbar system is used instead of a bus system. There is a disadvantage that the amount is increased. Further, in order to guarantee the coherency of the store-in cache, control is performed such that any memory block of the shared memory can be cached in only one store-in cache at the same time. For this reason, there is a disadvantage that the hit rate in the store-in cache is reduced, and the performance of the entire system is reduced.

The applicant of the present application has filed a Japanese Patent Application No. 7-102532 for a shared memory type multiprocessor system which has solved such a disadvantage. In this multiprocessor system, the same memory block is controlled so that multiple store-in caches can be shared within a cluster or between clusters, so that the store-in cache hit rate can be improved and the overall system performance can be improved. can do.

However, in the above-mentioned multiprocessor system of the prior application, the memory block address of the shared memory in the own cluster held in the store-in cache of the other cluster is registered in the directory memory in a directory system. All of the shared memory block addresses in the IP must be stored in the directory. Therefore, when the amount of hardware becomes large and the capacity of the shared memory is changed, it is necessary to prepare a directory memory corresponding to each.

Accordingly, an object of the present invention is to provide a shared memory type multiprocessor system that can further improve the above-mentioned prior application and can significantly reduce the amount of hardware.

[0008]

In order to achieve the above object, the present invention provides a plurality of processing units each having a store-in cache connected to a plurality of processors, and a plurality of processing units connected to the plurality of processing units by a system bus. A shared memory multiprocessor system having two clusters with a shared memory and a directory memory for registering a key address of a block address of a shared memory in the own cluster held in a store-in cache of another cluster; Means for searching the directory memory and determining whether an address of a memory access request to the shared memory has a cache hit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG.
0 and 201 are clusters, respectively. Cluster 200
Is composed of four processing devices 230 to 233, a shared memory 240 connected to the processing devices via a system bus 250, and a directory 260. The processing units 230 to 233 each include four processors (hereinafter, referred to as EPUs) 210.
To 213 and store-in caches 220 to 223 connected to the four EPUs.

The other cluster 201 has exactly the same configuration, and includes four processing devices 234 to 237, a shared memory 241 connected to the processing devices 234 through a system bus 251, and a directory 261. Processing devices 234 to 23
Reference numeral 7 denotes four EPUs 214 to 217 and a store-in cache 224 connected to each of the four EPUs.
To 227.

FIG. 2 is a block diagram showing in detail the directory 261 in the cluster 201 of FIG. The directory 260 has the same configuration as the directory 261. In FIG. 2, reference numeral 100 denotes a directory memory control circuit that controls the directory memory 271, and requests a memory access from the directory 260 of another cluster to the shared memory 241 in the own cluster.
A request code and an address such as a memory access request from the system bus 251 in the own cluster to the shared memory 241 in the own cluster are received, and the directory memory 271 is controlled.

FIG. 3 shows the format of the directory memory 271. The directory memory 271 includes a key address 300 of a memory block of the shared memory 241 in the own cluster held in the store-in caches 220 to 223 of another cluster, a valid bit 301 indicating that the address is valid, and a memory of the address. The block comprises a plurality of compartments storing an update bit 302 indicating that the block has been updated by writing by the EPUs 210 to 213 of other clusters. Each compartment has a key address 300 and a valid bit 30.
1, an update bit 302 is stored.

Reference numeral 102 denotes a hit status determination circuit. The hit / status determination circuit 102 searches the address read from the directory memory 271 and determines whether or not the address of the memory access request has a cache hit. As will be described later in detail, status determination is performed based on the valid bit and the update bit added to each of the key addresses of the directory memory 271.

Reference numeral 103 denotes a request replacement circuit.
Based on the determination result of the hit / status determination circuit 102, the request is replaced with a request suitable for the status of the memory block to be accessed, and the request is output to the system bus 251 or the directory 260. Reference numeral 104 denotes an eviction control circuit. When the hit / status determination circuit 102 determines that there is a cache mishit, the address of the memory access request is newly added to the directory 271 based on the status determination result.
In order to register any one of the same set addresses already registered in the directory memory 271, control is performed.

Table 1 shows the possible states of the memory blocks cached in the store-in cache used in the present embodiment.

[0016]

[Table 1] Next, the basic operation of the present embodiment will be described with reference to FIG. For convenience, the processing device 23 of the cluster 200
0 to the shared memory 240 or 2
The operation when trying to access 41 will be described. Other EPUs in cluster 200 and cluster 201
This is exactly the same for the EPU. The basic operation in the following four cases will be described according to the type of request from the EPU. (1) Read for the memory space of the own cluster (shared memory 240) (2) Read for the memory space of the other cluster (shared memory 241) (3) Write for the memory space of the own cluster (shared memory 240) (4) Other cluster First, write to the memory space (shared memory 241) of the own cluster (shared memory 2)
The operation in the case of a read for (40) will be described. Less than,
1.1. When the desired data is cached in the store-in cache 220, and 1.2. The case where the desired data is not cached in the store-in cache 220 will be described separately.

1.1. If the desired data has been cached in the store-in cache 220, that data is returned to the EPU.

1.2. If the desired data is not cached in the store-in cache 220, the store-in cache 220 issues a shared block read request (SBR) to the system bus 250. When a data reply to this SBR is returned, this is returned to the EPU. Hereinafter, 1.2.
1. The other store-in cache of cluster 200 is DE
Caching in the state, and 1.2.2. When another store-in cache of the cluster 200 is caching in the CE or CS state, and 1.2.3.
A case where none of the other store-in caches of the cluster 200 is caching will be described separately.

1.2.1. If another store-in cache in the cluster 200 is caching in the DE state, the store-in cache makes a data reply on the system bus 250 and puts itself in the CS state. The store-in cache 220 receives the data, registers it in the CS state, and returns it to the EPU. The shared memory 240 also receives this data and updates the contents of the memory.

1.2.2. If another store-in cache of the cluster 200 is caching in the CE or CS state, the cache is updated to the CS state in the CE state. The shared memory 240 performs data reply on the system bus 250. The store-in cache 220 receives this data, registers it in the CS state, and returns it to the EPU.

1.2.3. Directory 260 searches directory memory 270 if none of the other store-in caches of cluster 200 are caching. Hereinafter, 1.2.3.1. When the address is not registered in the directory memory 270;
3.2. When the address is registered in the directory memory 270 and the update bit is “0”;
2.3.3. The case where the address is registered in the directory memory 270 and the update bit is “1” will be described separately.

1.2.3.1. If the address is not registered in the directory memory 270, nothing is performed. At this time, the shared memory 240 performs data reply on the system bus 250. The store-in cache 220 receives this data, registers it in the CE state, and returns it to the EPU.

1.2.3.2. If the address is registered in the directory memory 270 and the update bit is “0”, nothing is performed. At this time, the shared memory 240
Makes a data reply and stores in cache 220
Receives the data, registers it in the CS state, and returns it to the EPU.

1.2.3.3. When the address is registered in the directory memory 270 and the update bit is “1”, the update flag is set to “0”. Further, the SBR is transferred to the directory 261 and the directory 261 is transferred.
Issues an SBR on the system bus 251. This SB
With respect to R, one of the store-in caches of the cluster 201, which is cached in the DE state, performs data reply on the system bus 251. The store-in cache that has performed the data reply updates the state from DE to CS. This data is received at directory 261 and transferred to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, registers it in the CS state, and returns it to the EPU. The shared memory 240 also receives this data and updates the contents of the memory.

Next, the case of (2) reading from the memory space (shared memory 241) of another cluster will be described. Hereinafter, 2.1. 1. when the desired data is cached in the store-in cache 220;
2. A case where desired data is not cached in the store-in cache 220 will be described separately.

2.1. If the desired data has been cached in the store-in cache 220, that data is returned to the EPU.

2.2. If the desired data is not cached in store-in cache 220, issue an SBR on system bus 250. When a data reply to this SBR is returned, this is returned to the EPU. Hereinafter, 2.2.1. The case where another store-in cache of the cluster 200 is caching in the DE state, and 2.2.2. When another store-in cache of the cluster 200 is caching in the CE or CS state, and 2.2.3. A case where none of the other store-in caches of the cluster 200 is caching will be described separately.

2.2.1. When the store-in cache of the cluster 200 performs caching in the DE state, the store-in cache makes a data reply on the system bus 250 and puts itself in the CS state. The store-in cache 220 receives the data, registers it in the CS state, and returns it to the EPU. In parallel with this, directory 26
0 receives the data and transfers it to the directory 261. The directory 261 sets the update bit for the memory block address of this data to “0”. Further, a memory block write request is issued on the system bus 251 and this data is written to the shared memory 241.

2.2.2. If other store-in caches of cluster 200 were caching in the CS state, this (these) store-in caches do nothing. Directory 260 stores SBR in directory 261
And the directory 261 issues this SBR on the system bus 251. The shared memory 241 performs data reply on the system bus 251. Directory 2
61 receives this data and transfers it to the directory 260. The directory 260 performs data reply on the system bus 250. Store-in cache 220
Receives the data, registers it in the CS state, and returns it to the EPU.

2.2.3. If none of the other store-in caches of cluster 200 are caching, directory 260 transfers to directory 261. The directory 261 registers the address of this SBR with the update bit being “0” and the valid bit being “1”. Also, it issues an SBR on the system bus 251.
Hereinafter, the operation for this SBR will be described in 2.2.3.1. When any of the store-in caches of the cluster 201 is caching in the DE state, 2.2.2.2. The case where the store-in cache of the cluster 201 is caching in the CE or CS state, and 2.2.2.3. The case where none of the store-in caches of the cluster 201 performs caching will be described separately.

2.2.3.1. If any of the store-in caches of the cluster 201 is caching in the DE state, the store-in cache is
A data reply is made on 51 to bring itself into the CS state. The directory 261 receives this data and transfers it to the directory 260. The shared memory 241 also receives this data and updates the contents of the memory. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives the data,
Register in CS state and return to EPU.

2.2.3.2. If the store-in cache of the cluster 201 is caching in the CE or CS state, in the case of the CE state, it is updated to the CS state. The shared memory 241 performs data reply to the system bus 251. The directory 261 receives this data,
Transfer to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives the data, registers it in the CS state, and returns it to the EPU.

2.2.3.3. When none of the store-in caches of the cluster 201 is caching, the shared memory 241 performs data reply on the system bus 251. The directory 261 receives this data and transfers it to the directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives the data,
Register in CS state and return to EPU.

Next, the case (3) of writing to the memory space (shared memory 240) of the own cluster will be described. Hereinafter, 3.1. When the store-in cache 220 caches the data to be written in the DE state, and 3.2. When the store-in cache 220 caches data to be written in the CE state, and 3.3. When the store-in cache 220 caches the data to be written in the CS state,
3.4. The case where the store-in cache 220 does not cache the data to be written will be described separately.

3.1. If the store-in cache 220 caches the data to be written in the DE state, it writes to this.

3.2. If the store-in cache 220 is caching the data to be written in the CE state, it writes to this and puts itself in the DE state.

3.3. If the store-in cache 220 is caching the data to be written in the CS state, it writes it into the DE state. In parallel with this, a memory block invalidation request (hereinafter referred to as INV) is issued on the system bus 250. Cluster 200
If any of the other store-in caches is cached in the CS state, it is placed in the INV state and the registration is deleted. If the update bit is registered as "0" in the directory memory 270, the directory memory 270 sets the valid bit to "0", deletes the registration, and transfers the INV to the directory 261. Directory 26
1 issues INV on the system bus 251. If any of the store-in caches of the cluster 201 is cached in the CS state, this is set to the INV state.

3.4. If the store-in cache 220 is not caching the data to be written, it issues an exclusive block read request (hereinafter, referred to as EBR) on the system bus 250. Hereinafter, 3.4.1. When another store-in cache of the cluster 200 is caching in the DE state, and 3.4.2. Cluster 2
00 is cached in CE state, and 3.4.3. When another store-in cache of the cluster 200 is caching in the CS state, and 3.4.4. The case where none of the other store-in caches of the cluster 200 is caching will be described separately.

3.4.1. When another store-in cache of the cluster 200 is caching in the DE state, the store-in cache makes a data reply on the system bus 250 and puts itself in the INV state. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

3.4.2. If another store-in cache of the cluster 200 is caching in the CE state, it is put into the INV state. The shared memory 240 performs data reply on the system bus 250. The store-in cache 220 receives the data, writes to it, and registers it in the DE state.

3.4.3. If another store-in cache of the cluster 200 is caching in the CS state, it is brought into the INV state. The shared memory 240 performs data reply on the system bus 250. The store-in cache 220 receives the data, writes to it, and registers it in the DE state. In parallel with these, the directory memory 270 is searched, and if the update bit is registered as "0", the registration is deleted by setting the valid bit to "0" and the INV is transferred to the directory 261. Directory 260 is located on system bus 251
Issue NV. If any of the store-in caches of the cluster 201 is cached in the CS state, this is set to the INV state.

3.4.4. If none of the other store-in caches of cluster 200 are caching,
The directory memory 270 is searched. Hereinafter, 3.4.
4.1. The case where it is not registered in the directory memory 270 and the case of 3.4.4.2. The case where the update bit is registered as “0” in the directory memory 270, and 3.4.
4.3. The case where the update bit is registered as "1" in the directory memory 270 will be described separately.

3.4.4.1. Directory memory 27
If it is not registered in 0, do nothing. In this case, the shared memory 240 performs data reply on the system bus 250. The store-in cache 220 receives the data, writes it, and registers it in the DE state.

3.4.4.2. Directory memory 27
When the update bit is registered as “0” at 0, the directory memory 270 deletes the registration by setting the valid bit to “0” and transfers the INV to the directory 261. The directory 261 issues an INV on the system bus 251. If any of the store-in caches of the cluster 201 are cached in the CS state, this is stored in the INV
State. In parallel with these, the shared memory 240 makes a reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

3.4.4.3. Directory memory 27
If the update bit is registered as "1" at 0, the registration is deleted by setting the valid bit to "0" and the directory 261 is deleted.
To the EBR. The directory 261 issues an EBR on the system bus 251. In response to this EBR, one of the store-in caches of the cluster 201, which is cached in the DE state, performs data reply on the system bus 251. The store-in cache that performed the data reply changes the state from the DE state to IN
Update to V state. This data is received at directory 261 and transferred to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

Next, the case (4) of writing data to the memory space (shared memory 241) of another cluster will be described. Hereinafter, 4.1. When the store-in cache 220 caches data to be written in the DE state, and 4.2. When the store-in cache 220 caches the data to be written in the CS state, and 4.3. The case where the store-in cache 220 does not cache the data to be written will be described separately.

4.1. If the store-in cache 220 caches the data to be written in the DE state, it writes to this.

4.2. If the store-in cache 220 is caching the data to be written in the CS state, it writes it into the DE state. In parallel with this, an INV is issued on the system bus 250. If another store-in cache of the cluster 200 is cached in the CS state, this is set to the INV state.

4.3. If the store-in cache 220 is not caching the data to be written, an EBR is issued on the system bus 250. Hereinafter, 4.3.
1. The other store-in cache of cluster 200 is DE
When caching is performed in the state 4.3.2. When another store-in cache of the cluster 200 is caching in the CS state, 4.3.3. The case where none of the other store-in caches of the cluster 200 is caching will be described separately.

4.3.1. When another store-in cache of the cluster 200 is caching in the DE state, the store-in cache makes a data reply on the system bus 250 and puts itself in the INV state. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

4.3.2. If another store-in cache of the cluster 200 is caching in the CS state, that store-in cache puts it in the INV state. Directory 260 is EBR in directory 261
To transfer. The directory memory 271 sets the update bit to “1” and issues an EBR on the system bus 251. If any of the store-in caches of the cluster 201 is cached in the CS state, this is set to the INV state. The shared memory 241 performs data reply on the system bus 251. This data is stored in directory 26
1 and transferred to the directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

4.3.3. If none of the other store-in caches of cluster 200 are caching,
Directory 260 transfers the EBR to directory 261. The directory memory 271 registers the update bit as “1” and the valid bit as “1”, and issues an EBR on the system bus 251. Hereinafter, the operation for this EBR will be described in 4.3.3.1. When one of the store-in caches of the cluster 201 is caching in the DE state, and 4.3.3.2. The case where the store-in cache of the cluster 201 is caching in the CE or CS state, and 4.3.3.3. The case where none of the store-in caches of the cluster 201 performs caching will be described separately.

4.3.3.1. If any of the store-in caches of the cluster 201 is caching in the DE state, the store-in cache is
A data reply is made on 51 to put itself in the INV state. This data is received at directory 261 and transferred to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

4.3.3.2. If the store-in cache of the cluster 201 is caching in the CE or CS state, it is set to the INV state. Shared memory 24
1 performs data reply on the system bus 251. This data is received at directory 261 and transferred to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

4.3.3.3. If none of the store-in caches of cluster 201 is caching,
The shared memory 241 performs data reply on the system bus 251. This data is received at directory 261 and transferred to directory 260. The directory 260 performs data reply on the system bus 250. The store-in cache 220 receives this data, writes it, and registers it in the DE state.

Next, the eviction process using the directory shown in FIG. 2 will be described. The eviction process is required according to 2.2.3. Or 4.3.3. In the case of
In this case, in order to newly register an address in the directory memory, the already registered address is deleted. Also, the address to be deleted is referred to as an eviction target address.

Hereinafter, in the same set address as the address to be newly registered, 5.1. When one of the address blocks already registered in the directory memory is invalid, and 5.2. 4. all address blocks already registered in the directory memory are valid, and any one of them is the update bit “0”;
3. The contents of the eviction process will be described separately for the case where all the address blocks already registered in the directory memory are valid and all of them are the update bit “1”.

5.1. If any of the address blocks already registered in the directory memory is invalid, the eviction process is not performed.

5.2. If all the address blocks already registered in the directory memory are valid, and if any of them is the update bit “0”, any one of these addresses is set as an eviction target address.
The registration is deleted by setting the valid bit of the eviction target address to “0”, and the directory 261 transfers the INV to the directory 260. The directory 260 issues an INV on the system bus 250. If the store-in cache of the cluster 200 is caching in the CS state, it is changed to the INV state.

5.3. If all the address blocks already registered in the directory memory are valid, and if any of them is the update bit “1”, any one of the addresses is set as the eviction target address. The registration is deleted by setting the effective bit of the eviction target address to “0”, and the directory 261 is moved to the directory 260 by E.
Transfer BR. Directory 260 is in system bus 2
Issue EBR on 50. Among the store-in caches of the cluster 200, those cached in the DE state perform data reply on the system bus 250.
The store-in cache that has performed the data reply changes the state from DE to INV. This data is received at directory 260 and transferred to directory 261. The directory 261 issues a memory block write request on the system bus 251, and the shared memory 24
1 is written with this data.

Next, a specific operation of the eviction process in the directory 261 will be described with reference to FIG.
First, assuming that a memory access request is sent from the directory 260 of the cluster 200, the directory memory control circuit 100 reads the data of the directory memory 271 and the hit / status determination circuit 10
Sent to 2. The hit status determination circuit 102 determines whether a cache hit has occurred based on the address, valid bit, and update bit read from the directory memory 271 as described above. The status is determined for each read address. Here, since the eviction process is described, it is assumed that the hit / status determination circuit 102 determines that the cache is a mishit.

The eviction process control circuit 104 controls the eviction process based on the determination result of the hit / status determination circuit 102. Here, the eviction control circuit 10
4 according to the result of the status determination. a. If any address is invalid, and 5.2. a. All addresses are valid bits "1", and any of them is an update bit "0", and 5.3. a. All addresses are valid bits "1"
Each operation will be described separately for the case where all of them are update bits “1”.

5.1. a. If any of the addresses is invalid, the eviction process is not performed.

5.2. a. All addresses are valid bits “1”, and one of them is an update bit “0”.
In this case, an INV request is transferred to the directory 260 of the cluster using any one of the address blocks as an eviction target address.

5.3. a. If all of the addresses are valid bits “1” and all of them are update bits “1”, any one of them is set as an eviction target address and the EBR is set to the directory 260 of the cluster.
Forward the request.

In this embodiment, for example, the set address of the directory memory is 17 bits and the key address is 10 bits.
When realized by managing 64 bits per block,
An 8 GB shared memory can be managed by a 128 K word directory memory. In contrast,
In the conventional directory system, a directory memory of 128 M words is required, and the memory capacity can be significantly reduced as compared with the conventional one.

[0067]

As described above, according to the present invention, the directory memory has a cache structure,
The capacity of the directory memory can be significantly reduced as compared with the conventional one, which has the effect that the configuration of the apparatus can be significantly simplified and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a directory of the embodiment of FIG. 1 in detail.

FIG. 3 is a diagram showing a format of a directory memory used in the embodiment of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 directory memory control circuit 102 hit / status determination circuit 103 request replacement circuit 104 eviction control circuit 200, 201 cluster 210-217 processor (EPU) 220-227 store-in cache 230-237 processing device 240,241 shared memory 250,251 system Bus 260,261 Directory 270,271 Directory memory

Claims (3)

(57) [Claims] 1. A shared memory type having two clusters each including a plurality of processing units each having a store-in cache connected to a plurality of processors, and a shared memory connected to the plurality of processing units and a system bus. In a multiprocessor system, a directory memory for registering a key address of a block address of a shared memory in its own cluster held in a store-in cache of another cluster, and a search for the directory memory, and a memory access to the shared memory Means for determining whether or not a request address has a cache hit. A shared memory type multiprocessor system comprising: 2. The shared memory type multiprocessor system according to claim 1, wherein when said judging means judges a cache mishit, an address judged as a mishit is newly registered in said directory memory. A shared memory type multiprocessor system, characterized in that the shared memory type multiprocessor system includes means for controlling to evict any one of the same set addresses already registered in the directory memory based on a status determination result by the determination means. 3. The shared memory multiprocessor system according to claim 2, wherein the directory memory has a valid bit indicating whether a registered address is valid for each of the registered key addresses and an update. Update bit indicating whether or not the
The shared memory type multiprocessor system according to claim 1, wherein the determination unit performs a status determination based on the valid bit and the update bit.