JP2852053B2 - Packet switching equipment - Google Patents

Description

The present invention relates to a packet switching method and a device thereof,
In particular, the present invention relates to a switching device and a switching method suitable for exchanging fixed-length packets at high speed.

[Prior art] As a network using packet switching, CCITT
(International Telegraph and Telephone Advisory Committee) A protocol using the recommended protocol X25 has been commercialized and widely used. However, recently, there has been much interest in a device for exchanging packets at high speed using a simplified protocol in order to packetize and transmit and exchange all information. The main function of such a high-speed packet switching device is to exchange packets between a plurality of input / output ports that are multiplexed at high speed (for example, about 150 Mbps) in accordance with the header information.

Among the high-speed packet switching systems, a system in which a packet has a fixed length (hereinafter, a fixed-length packet is referred to as a cell) and the switching process is performed by hardware is excellent in terms of high speed.

Such an exchange system is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-135944.
And JP-A-60-500934.
In the example disclosed in JP-A-59-135944, input cells from a plurality of input ports are multiplexed and written to a common buffer. The address written in the cell is transferred to an output port from which the cell is to be output. On the output port side, cells to be output are read from the common buffer using the transferred address. Also, in JP-A-60-500934,
The switch is basically composed of a two-input two-output switch and is connected in multiple stages to form a switch. The two-input two-output basic switch autonomously exchanges cells by using part or all bits of the cell header. In Japanese Patent Application Laid-Open No. Sho 60-500934, a packet switching device is constituted by subordinate connections of three networks, a classification network, a trap network, and an extension network, and these three types of networks are each a basic switch having the two inputs and two outputs. Is realized by multi-stage connection.

Another example is “Input Versus Output Queuei
ng on a Space-Division Packet Switch "IEE Transactions, On Communications COM-35, No. 12, 1987 (IEEE Transactions on Commu
nications Vol-35, No. 12, 1987). In the above document, the basic configuration of the switch is classified into two types, an input buffer type and an output buffer type, and the characteristics of each are analyzed. The example shown in the above-mentioned JP-A-59-135944 is an output buffer type. The input buffer type switch includes a buffer prepared for each input port and a switch circuit for transferring a buffer output to a desired output port. Input cells are temporarily stored in a buffer, and cells are output from each input port so that cells from a plurality of input ports do not collide with the same output port, and are transferred to an output port by a switch circuit.

[Problems to be Solved by the Invention] However, there are some problems in the above-mentioned conventional technology. The first problem is that it is difficult to increase the capacity of the packet switching device. In the method disclosed in JP-A-59-135944, the access speed of the common packet buffer is inversely proportional to the product of the number of input ports and the transmission speed of each input port.
The switching capacity of the packet switching device is limited by the speed of the memory used. A method of connecting a plurality of unit switches to a multistage (for example, a cross-type network) to increase the capacity is also conceivable, but in this case, wiring for connecting the unit switches becomes a problem. For example, when 32 × 32 unit switches are connected in a cross shape to form a 1024 × 1024 switch, the number of interconnections is about 4000. On the other hand, in the system disclosed in Japanese Patent Application Laid-Open No. 60-500934, an increase in the number of interconnections is a bottleneck for increasing the capacity. That is, when the number of input / output ports is N, the number of wires interconnecting the two-input / two-output basic switches is proportional to the square of log ₂ (N). The second problem relates to the input buffer type switch, and it is impossible to increase the usage rate of the switch. As described in the above document, in the input buffer type switch, if the head cell of the buffer is not output due to collision, the subsequent cells are not output even if the switch circuit has a transfer capability. It is difficult to increase the rate to 50% or more.

Accordingly, it is an object of the present invention to provide a packet switching device that can easily be increased in capacity without increasing the amount of memory.

It is another object of the present invention to improve the utilization of the input buffer type switch.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a packet switching device comprising a concentrator, a multiplexing stage, a switching stage for exchanging multiplexed signals, and a multiplexed signal transmitted to a destination subscriber. The switching stage is composed of an input buffer type switch, and the buffer for the line concentrator, the line concentrator for the multiplexing stage, the multiplexing buffer, and the buffer for the switching stage are shared. Further, the shared buffer is divided for each destination distribution stage so that each line concentrator and multiplexing stage can output packets addressed to different distribution stages.

[Operation] According to the present invention, it is possible to reduce the number of wirings by multiplexing and exchanging signals from subscribers in a multi-stage packet switching device. For example, if the subscriber interface speed is 150Mbps, multiplex this to 2.4Gbps
, It is possible to reduce the number of wires between the exchange stages to 1/16 or less. In the case of multiplexing and exchanging at N times speed, the exchange processing time of the cell is also 1 / N, so that the exchange delay can be reduced to 1 / N. Further, by using the switch of the switching stage as an input buffer type and sharing the buffer for the line concentrator and the multistage and the buffer for the switching stage, the required memory amount can be reduced.

The use rate of the input buffer type switch can be improved by dividing the buffer for each destination port and controlling each input port to output cells addressed to different output ports. That is, a different output port number is cyclically assigned to each input port, and each input port preferentially outputs a cell destined for the assigned output port. Can be suppressed.

Embodiment FIG. 1 to FIG. 9 show a first embodiment of the present invention.

FIG. 1 shows an outline of the packet switching apparatus. The cell has a fixed length of 36 bytes, the header is 4 bytes, the information section is 32 bytes, and the virtual circuit number (VC
N) is written. I / O ports 100-1-1 to 100-32-32, 101-1-1 to 101-32 of packet switching equipment
At -32, signals are input and output at 150 Mbps bit serially.

The present packet switching apparatus includes multiplexers 103-1 to 103-32 for multiplexing input signals, a space division switch 113 for exchanging multiplexed signals, and a controller 114 for the space division switch. And distribution units 102-1 to 102-32 for distributing multiplexed signals to designated output ports, and having a function of transferring cells to designated output ports according to the VCN of each cell.

The input signals are supplied to multiplexers 106-1 to 106-32.
Are multiplexed for each cell and written to the buffers 107-1 to 107-32. The buffers 107-1 to 107-32 are logically divided into cell destinations, and the input cells are
The destination distribution device is analyzed from the VCN and written to the corresponding buffer. The input / output control devices 108-1 to 108-32 scan for the presence or absence of cells in the buffer, select a cell to be transmitted, and transmit the destination to the control device 114 as a cell transfer request. The control device 114 analyzes the transfer request sent from each output control circuit, determines which cell is to be output to each distribution device, notifies each multiplexing device, and controls the space division type switch. Close the required contacts. Control device
The input / output control circuit, which has been notified of the cell transmission permission from 114,
Output a cell. When a plurality of cells request transfer to the same distribution device, only one cell can be transferred, and the other cells are not transferred.

The space division type switch 113 is a cross-point type switch, and can connect an arbitrary input to an arbitrary output. At the multiplexer outputs 110-1 to 110-32, since a 150 Mbps input signal is multiplexed by 32, it becomes a 4.8 Gbps serial signal. The distribution devices 102-1 to 102-32 determine the final output port by analyzing the VCN of the input cell, and output the final output port. Distributors do not drop cells when traffic is woven to a specific output port.
102-1 to 102-32 require a buffer. In FIG. 1, the number of input ports of the multiplexers 103-1 to 103-32 is 32. However, when the usage rate of the input lines is low, it is possible to support 32 or more lines. in this case,
The multiplexers 102-1 to 102-32 also have a line concentrating function.

FIG. 2 shows an outline of the operation timing.
Based on the cell output request from each multiplexer, arbitration for determining whether or not each cell can be output, connection control of space division type switch 113, and cell switching are executed by controller 114 in parallel. In this embodiment, the cell length is 36 bytes (288 bits), and the space division type switch 113
Since the input / output bit rate is 4.8 Gbps, the cell exchange shown in FIG. 2 requires 60 ns (288 / 4.8 × 10 ³ ).
Therefore, one cycle of the exchange processing shown in FIG. 2 is obtained by adding the switch connection control time to 60 ns. Since the efficiency of the packet switching device is the cell exchange time / exchange period, the shorter the switch connection control time, the higher the efficiency.
For example, as a space division type switch, the switching time
Using a 1 ns optical switch can increase the efficiency to 98% or more (60 / (60
+1)). In the following description, it is assumed that the switch connection control time is 0 for simplicity.

FIG. 3 shows details of, for example, the device 103-1 of FIG. 1, and shows 32 input ports 10-1-1 to 101-1.
It has a function of multiplexing cells input from −32, outputting a cell output request to the control device 114, and outputting cells based on a cell output enable / disable signal from the control device. When another multiplexing device issues a cell transfer request to the same distribution device, the cell that issued the transfer request may not be able to be output.
In order to accumulate these cells that could not be output, the multiplexing apparatus requires a buffer 107-1. Further, as described above, when the multiplexing apparatus has a line concentrating function, a buffer is required for line concentrating, so that a buffer for cell collision countermeasures and a buffer for line concentrating can be shared. is there.

The input cells are converted into parallel signals for each cell by the serial / parallel converters 301-1 to 301-32. Cells from each input port are periodically selected by the selector 302, and once latched.
After being stored in 03, it is written into the buffer 107-1.
Buffer 107 for cells from input ports 101-2 to 101-32.
In this embodiment, shift registers 300-2 to 300-32 are inserted to adjust the write timing to -1. FIG. 4 shows the above timing relationship. By dividing the 4.8 GHz clock supplied from the control device 114 by 32, a 150 MHz clock is created, and this clock is used to convert the serial / parallel converters 301-1 to 301-32 and the shift register 30
0-2 to 300-32 operate. Serial-parallel conversion 301-1 to 301-
The reference numeral 332 has a bit length equal to the cell length, and supplies information for one cell in a serial / parallel manner to the latch 303. Input 101-1
-2 to 101-1-32 are shift registers 302-2 to 300-2
The data is shifted by 9 bits (with a clock of 150 MHz) by −32, and 32 cells are written into the buffer 107-1 while 288 bits of information are input.

The buffer 107-1 is logically divided for each cell destination distribution device. The VCN portion of the header is taken out from the serial / parallel converters 301-1 to 302-32, analyzed by the outgoing route detection path 310, and based on the result, the address control circuit 315 determines the write address. This analysis is, for example, the cell's VCN
Can be realized by referring to a table using the address as an address. The contents of the table are set when the connection is set. Cell outputs from the multiplexers 103-1 to 103-32 are used to avoid cell collision toward the same distributor.
Control is performed such that cells from control device 114 to the designated distribution device are preferentially output. The control device 114 cyclically designates a different distribution device for each multiplexing device.
As a result, the utilization-delay characteristics of the packet switching device can be improved. If there is a cell addressed to the distribution device specified by the signal line 112-1 from the control device 114,
The output request of this cell is output to the control device through the signal line 111-1. If there is no cell destined for the specified distribution device, it is sequentially scanned to see if there is a cell destined for another distribution device, and if there is a cell destined for another distribution device in buffer 107-1. , And outputs the output request of the cell to the control device 114. If there are no cells in the buffer 107-1,
This is notified to the control device 114 via the signal line 111-1. When a cell transmission enable signal is received from the control device 114, the cell is read out from the buffer 107-1, converted into parallel-serial data by the shift register 305, and output. Address control device 315
Supplies the cell write and read addresses to the buffer 107-1 through the signal lines 313 and 314. The write, read, and address are selected by the selector 312 in accordance with the write / read timing of the buffer 107-1, and are supplied to the buffer 107-1.

FIG. 5 shows the details of the address control circuit 315. This circuit consists of 32 buffers that are logically divided by destination.
Holds write and read addresses to buffer 10
It has a function of determining the cell to be output and supplying it to the control circuit 114, in addition to supplying it to 7-1. Buffer write,
The read address holding circuits 500-1 to 500-32 hold the addresses of the logically divided buffers. That is,
Buffer write / read address holding circuit 500-1
To 500-32 correspond to logically divided buffers, respectively. The counters 509-1 to 509-32 manage write addresses, and the counters 510-1 to 510-32 manage read addresses. Each counter is incremented every time writing or reading is performed in the area divided into 32 parts of the buffer 107-1. When the counter reaches the upper limit of the address, the counter is controlled to return to the lower limit of the address. In order to manage the occupancy of each buffer, two match detection circuits 511-1 to 511-
32, 512-1 to 512-32 are used. That is, taking the buffer write / read address holding circuit 500-1 as an example, if the counter 509-1 and the counter 510-1 match, the buffer is empty (signal 521-1 = 'H'), If the value obtained by adding 1 to 510-1 is equal to the value of the counter 509-1, the buffer is full (signal 514-1 =
'H'). Since the two counters are incremented each time a cell is written or read, each logically divided buffer processes cells in a first-in first-out manner.

The output port determination circuit 503 determines which cell in the buffer is to be output. The selection of the output cell is performed by selecting the frame signal (FRM) received from the control circuit 114, the clock (CLK, 4.8 GHz), and the buffer writing / reading from each buffer write / read address holding circuit 500-1 to 500-32. This is performed with reference to the signals 521-1 to 521-32. Control circuit 114
After that, the frame signal shifted by one exchange period (60 ns) is distributed to each of the multiplexing circuits 103-1 to 103-32. In each address control circuit, the clock C
LK is divided by 288 (cycle 60 ns), and the output is supplied to the counter 502. This counter is reset by a frame signal (FRM). For example, as shown in FIG.
Is a signal cyclically circulating between. Each address control circuit checks whether there is a cell destined for the distribution device corresponding to the output of the counter 502, and if so, the control circuit 114
Send output request to If not, the presence / absence of a cell addressed to the distribution device after the designated one is checked at a time. If there is a cell, an output request is sent to the control circuit 114. Since each multiplexing circuit is supplied with a frame signal shifted by one switching cycle, it is possible to avoid cell collision toward the same distributor.

The destination distribution unit number of the cell output from the output port determination circuit 503 and the presence or absence of the output cell are respectively indicated by signal lines.
It is sent to the control circuit 114 through 519 and 520. The outputs of the counters 510-1 to 510-32 are input to the selector 501, and the counter output corresponding to the logically divided buffer to which the cell determined by the output port determination circuit 503 belongs is selected, and Sent to On the other hand, the write address is selected by the selector 504. Writing to each logically divided buffer is performed by the output path detection circuit 310.
The process is executed with reference to the distribution device number (signal line 311) detected in (1). That is, based on the output 311 from the output path detection circuit 310, a counter for controlling the write address of the corresponding buffer is selected, and the write address is supplied to the buffer 107-1. At the same time, the selector 505 outputs a signal 514-indicating whether there is room to write cells to the buffer.
The counter corresponding to the selected counter is selected from 1 to 514-32 ('H' indicates that there is no room to write to the buffer). The logical product of the inverted signal of the output of the selector 505, the signal INCELL (supplied by the output path detection circuit) indicating whether or not there is a cell to be written, and the write timing signal WES are supplied to the buffer as the write enable signal WE. If there is no room to write cells into the buffer, no write enable signal is output. Therefore, in this case, the cell is discarded.

The count-up of the counter groups 509-1 to 509-32 and 510-1 to 510-32 is executed by the counter control circuits 522 and 523. The counter control circuit 522 includes a cell output enable / disable signal 524 from the control circuit 114 and an output port determination circuit 503 output 519.
And a counter (510-1 to 510-32 1) for holding the read address of the buffer from which the cell was read.
Count up). Also, the counter control circuit 52
3, after the cell is written into a predetermined buffer, information INCELL indicating the presence / absence of a write cell and an output port number 311
Using the year, the corresponding counter (509-1 to 509-32 1)
One) to count up.

FIG. 7 shows details of the output port determination circuit 503. The output 518 of the counter 502 is decoded by the decoder 711 and becomes 32 signal lines 701-1 to 701-32. That is, only the signal line corresponding to the buffer number to be processed with priority is set to "H", and the others are set to "L". On the other hand, the empty / busy display signals 521-1 to 521-32 of each buffer are inverted.
Input to AND gates 703-1 to 703-32.

Here, the operation when the output 701-1 of the decoder 711 is “H” will be described. When the signal 701-1 is "H", the output of the OR gate 707-32 becomes "H". Therefore, when there is a cell in the cell buffer addressed to the distribution apparatus 1, the signal 521-1 becomes "L". , And the output of the AND gate 703-1 becomes “H”. Also, AND gates 706-1 to 706-32, O
Since the outputs of the R gates 707-1 to 707-31 become 'L', the signal 7
Only 05-1 is 'H', the others are (705-2 to 705-32) 'L', and a cell addressed to the distribution device 1 is selected. If there is no cell in the cell buffer addressed to the distribution device 1, the signal 521
-1 becomes 'H', and the AND gate 706-1 and the OR gate 707-1
Since the output becomes "H", the presence / absence of a cell addressed to the distribution device 2 and thereafter is checked in order, and the signal line (705-2 to 705-32 of 705-2 to 705-32) corresponding to the destination distribution device number of the cell detected first. One) becomes 'H'. The signals 705-1 to 705-32 are converted into a 5-bit signal 519 by the coder 710 and output. The logical sum of the signals 705-1 to 705-32 is calculated by the OR gate 709, and becomes a signal 520 indicating a cell output request.

FIG. 8 shows the configuration of the control device 114 in FIG. 1 in more detail. The 4.8 GHz clock CLK input from the outside is divided by 288 by the counter 808. By decoding this output by the decoder 810, a frame signal 811 to be supplied to each multiplexer is created and supplied to each multiplexer. Cell transmission request 11 from each multiplexer
Each of 1-1 to 111-32 is composed of 6 bits, 5 bits indicate the destination distribution device number of the cell, and 1 bit indicates the presence or absence of a cell transmission request. Five bits indicating the destination distribution device number of the cell are decoded by decoders 800-1 to 800-32, and 32 signals 801-1 to 801-1-32 to 80, respectively.
0−32−1 to 800−32−32. That is, only the signal line corresponding to the destination distribution device number becomes “H”, and the others become “L”. When there is no cell transmission request, all signal lines are set to 'L'. When there is no cell transmission request, all signal lines are set to 'L'. The decoder outputs 801-1-1 to 801-32-32 are input to the connection control devices 802-1 to 802-32 for each destination distribution device.

The connection control devices 802-1 to 802-32 correspond to output ports (that is, distribution devices) of the space division type switch 113, and determine cells to be output to each output port (arbitration). For example, in the connection control device 802-1, output requests to the output port 1 are collected. According to the frame signal 811 supplied from the control device 114, each multiplexing device outputs a transmission request for a cell of a different destination with priority. Therefore, the connection control device 802-1
Controls the output port 1 so as to preferentially accept a transmission request from the multiplexing apparatus designated by referring to the frame signal. The detailed circuit configuration is the same as that of the output port determination circuit shown in FIG. 7, and the description is omitted here. The connection control result is latched by the latches 803-1 to 303-32 at the end of each arbitration period.
The outputs of the latches 803-1 to 803-32 are collected for each multiplexing device, logically ORed, and used as a cell transmission enable / disable signal. For example, when there is a cell output request from the multiplexer 1,
Only one of the decoders 801-1-1 to 801-1-32 (80
2-1-i) becomes 'H', and a response to the cell output request appears in 805-i-1. Since the connection control result from the connection control devices 802-1 to 802-32 to the multiplexing device 1 is input to the OR gate 806-1, the OR gate 806-1 sends a response to the multiplexing device 1 to the OR gate 806-1. It will show. The control of the space division type switch 113 can be performed by signals 805-1 to 801-32-32. For example, signals 805-1-1 to 805-1
-32 indicates that only one of them (802-1-i) becomes 'H', which indicates that input port 1 should be connected to output port i. Therefore, when a cross-point type switch is used, the signals 805-1-1 to 805-805 are used.
-1-32 can be used as it is for controlling the intersection of the first row.

FIG. 9 shows the configuration of the distribution device 102-1. Buffer 105
-1 is logically divided for each destination line (101-1 to 101-32). Output 109-1 of space division switch 113
Is input to the 288-bit shift register 901 and is written to the buffer 105-1 in units of cells. In this case, the VCN of the cell is extracted from the shift register 901, analyzed by the header analyzer 902, sent to the address controller 903, and written to a predetermined position in the buffer 105-1. The cells in the buffer addressed to each circuit are periodically read out, temporarily latched by a latch 904, and then output via a destination circuit shift register (one of 905-1 to 905-32). Is done. Since the control method of the buffer 105-1 and the configuration of the address control circuit are almost the same as those of the multiplexer (the output port determination circuit is unnecessary and output periodically), detailed description is omitted.

In the above configuration, the case where the broadcast function is realized is as follows. That is, although the multiplexers 103-1 to 103-32 are logically divided for each destination, a buffer for a broadcast mode cell is further added thereto. This buffer may be physically separated from the normal cell buffer, or may be logically divided. The destination of the broadcast mode cell is its VCN
Therefore, the broadcast function can be realized by outputting the transfer request to the control device 114 a plurality of times.

As a second embodiment of the present invention, FIG. 10 shows an example in which a larger capacity packet switching device is configured. In this example, a two-stage configuration is used to expand the capacity, and each stage is composed of 32 space division switches. The multiplexers 1001-1-1 to 1001-32-32, the space division switches 1002-1 to 1002-32, 1004-1 to 1004-32, and the distribution devices 1005-1 to 1005-32 in FIG. Each is the same as the first embodiment. Buffer devices 1003-1 to 1003-32
Is a configuration in which the input signal multiplexing units 106-1 to 106-32 of the multiplexers 103-1 to 103-32 in FIG. 1 are removed so that the output signal of the space division switch is directly input. The other functions are multiplexing devices 103-1 to 103-32.
Is the same as According to this configuration, 150Mbps input 32768
Cell exchange between lines is possible. Further, in order to configure a device having a larger capacity or to improve traffic resistance characteristics, a multi-stage configuration having two or more stages may be employed.

[Effects of the Invention] As described above, according to the present invention, since input signals are multiplexed and exchanged, the number of wirings between exchange modules can be reduced, and a concentrator buffer and a multiplexed signal Since the switching buffer can be shared, the required amount of memory can be reduced and the capacity of the packet switching device can be easily increased. In addition, by dividing the input-side buffer for each destination port and controlling each input port to output cells destined for different destination ports,
The usage rate of the switching device can be improved. FIG.
The result of having calculated | required the relationship between the utilization rate of a switching device and delay by simulation is shown. The delay shown on the vertical axis is the time required to transmit one cell (time slot = 288 bits / 4.
8Gbps) as a unit. As can be seen from the figure, it is possible to improve the usage rate by 20% or more compared to the conventional method.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a packet switching device according to a first embodiment of the present invention, FIG. 2 is a diagram showing operation timing in the above device, and FIG. 3 is a multiplexer 103- in FIG.
1, FIG. 4 is a diagram for explaining the timing of cell writing from an input port to a buffer in the multiplexer, and FIG. 5 is an address control circuit 315 in FIG.
6, FIG. 6 is an explanatory diagram of a clock in the address control circuit, FIG. 7 is a configuration diagram of the output port determination circuit 503 in FIG. 5, FIG. 8 is a configuration diagram of the control device 114 in FIG. 9 is a block diagram of the distribution device 102-1 in FIG. 1, FIG. 10 is a diagram showing a packet switching device showing another embodiment of the present invention, and FIG. 11 is an improvement in the usage rate of the switching device according to the present invention. It is a figure for explaining an effect.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-247653 (JP, A) JP-A-63-22445 (JP, A) JP-A-64-11446 (JP, A) IEICE Technology Research report, SSE 88-53 (1988-7-20), p. 19-24 IEICE Technical Report, SE 87-71 (1987-7-17), p. 37-42 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] A switch for transferring a fixed-length packet input from a plurality of input lines to one of output lines determined by header information; a plurality of input ports and an input line of any of the switch means; A plurality of multiplexers connected between the plurality of input ports and multiplexing the fixed length packets input from the plurality of input ports and outputting the multiplexed packets to the input line of the switch unit; And a distributor for distributing the fixed-length packet output to the output line to a predetermined output port, wherein the switch means comprises a plurality of input lines and a plurality of output lines. A space division switch having a line and an operation of the space division switch according to header information of a fixed length packet supplied to each input line of the space division switch. Each of the multiplexing devices, a multiplexing circuit that outputs fixed-length packets input in parallel from a plurality of input ports in time series, and a multiplexing circuit that is output from the multiplexing circuit. A buffer memory for temporarily storing fixed-length packets; and output control means for outputting the fixed-length packets stored in the buffer memory to an input line of the switch means based on an instruction from the control device. A packet switching device characterized by the above-mentioned. 2. The packet switching apparatus according to claim 1, wherein said output control means repeatedly outputs a packet having header information indicating a broadcast mode a plurality of times.