JP2851314B2 - Driving method of two-terminal type active matrix liquid crystal display device - Google Patents

Driving method of two-terminal type active matrix liquid crystal display device

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Publication number
JP2851314B2
JP2851314B2 JP21039389A JP21039389A JP2851314B2 JP 2851314 B2 JP2851314 B2 JP 2851314B2 JP 21039389 A JP21039389 A JP 21039389A JP 21039389 A JP21039389 A JP 21039389A JP 2851314 B2 JP2851314 B2 JP 2851314B2
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Japan
Prior art keywords
liquid crystal
voltage
crystal display
active matrix
display device
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Japanese (ja)
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JPH0373924A (en
Inventor
清吾 富樫
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SHICHIZUN TOKEI KK
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SHICHIZUN TOKEI KK
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 液晶表示装置は低消費電力のフラットパネルディスプ
レイとして広く応用されている。中でも、スイッチング
素子を各画素に作り込んで駆動するアクティブマトリク
ス方式は大容量高品質の表示素子としてテレビ、情報端
末等に用いられつつある。スイッチング素子としては3
端子型のTFT(薄膜トランジスタ)と2端子型のダイオ
ードやMIM等の非線形抵抗素子が使われる。商品化は3
端子型のTFTが先行したが、2端子型は製造が3端子型
に対して簡単であり、今後が期待されている。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] Liquid crystal display devices are widely applied as low power consumption flat panel displays. Among them, an active matrix method in which a switching element is formed in each pixel and driven is being used as a large-capacity, high-quality display element in televisions, information terminals, and the like. 3 for switching element
A terminal type TFT (thin film transistor) and a non-linear resistance element such as a two-terminal type diode or MIM are used. Commercialization is 3
Terminal type TFTs preceded, but the two terminal type is easier to manufacture than the three terminal type, and future prospects are expected.

本発明は2端子型のスイッチング素子を用いた2端子
型アクティブマトリクス液晶表示装置の駆動方法に関す
る。
The present invention relates to a method for driving a two-terminal type active matrix liquid crystal display device using two-terminal type switching elements.

〔従来技術とその課題〕[Conventional technology and its problems]

第2図および第3図に2端子型スイッチング素子を用
いたアクティブマトリクス液晶表示装置の画素の基本配
置を示す。
FIGS. 2 and 3 show the basic arrangement of pixels of an active matrix liquid crystal display device using two-terminal switching elements.

第2図はダイオードリングといわれる方式である(特
開昭59−57273号公報)。C1,C2,C3はデータ線5、R1,R
2,R3は走査線6でありマトリクス配置されている。この
データ線5と走査線6の交点に対応して液晶表示画素10
と2端子型スイッチング素子であるダイオードリング20
とが配置されている。各ダイオードリングは順方向接続
されたダイオード群23と逆方向接続されたダイオード群
22よりなっている。個々のダイオード21は通常アモルフ
ァスシリコンのpin接合かショットキイ接合で構成され
る。
FIG. 2 shows a system called a diode ring (JP-A-59-57273). C1, C2, C3 are data lines 5, R1, R
2, R3 are scanning lines 6 arranged in a matrix. The liquid crystal display pixel 10 corresponds to the intersection of the data line 5 and the scanning line 6.
And diode ring 20 as a two-terminal switching element
And are arranged. Each diode ring is a diode group 23 connected in the forward direction and a diode group connected in the reverse direction.
It consists of 22. Each diode 21 is usually formed by a pin junction or a Schottky junction of amorphous silicon.

第3図はMIM方式の2端子型アクティブマトリクス液
晶表示装置である。C1,C2,C3はデータ線5,R1,R2,R3は走
査線6であり、そのデータ線5と走査線6の交点に対応
して液晶表示画素10と2端子型スイッチング素子である
MIM30が配置されている。MIMは金属−絶縁体−金属(導
体)構造を有し非線形の電流−電圧特性を有する2端子
型スイッチング素子である。代表的な構造としては下電
極Ta、絶縁膜としてはこのTaの陽極酸化膜(TaOx)、上
電極としてITO(透明導電体)があり、2枚のパタン
(マスク)で製造可能である。
FIG. 3 shows a two-terminal type active matrix liquid crystal display device of the MIM system. C1, C2, and C3 are data lines 5, R1, R2, and R3 are scanning lines 6, and are liquid crystal display pixels 10 and two-terminal switching elements corresponding to intersections of the data lines 5 and scanning lines 6.
MIM30 is arranged. MIM is a two-terminal switching element having a metal-insulator-metal (conductor) structure and having nonlinear current-voltage characteristics. A typical structure is a lower electrode Ta, an insulating film is an anodic oxide film (TaOx) of this Ta, and an upper electrode is ITO (transparent conductor), which can be manufactured with two patterns (masks).

第4図は従来のダイオードリングやMIM等のアクティ
ブマトリクス液晶表示装置の駆動方法に於ける走査信号
波形である(特開昭59−57288号公報)。
FIG. 4 shows a scanning signal waveform in a conventional driving method of an active matrix liquid crystal display device such as a diode ring or MIM (Japanese Patent Laid-Open No. 59-57288).

走査信号φ、φ、φはそれぞれのフィールドTA
及びTBの区間TA1、TA2、TA3及びTB1、TB2、TB3で線順次
を選択される信号である。走査信号φについて見る
と、正の書き込み区間TW1では正の書き込み電圧VW1が負
の書き込み区間TW2では負の書き込み電圧VW2が、正の保
持区間TH1では正の保持電圧VH1が負の保持区間TH2では
負の保持電圧TH2が印加される。
The scanning signals φ 1 , φ 2 , φ 3 correspond to the respective fields T A
And T B are signals for selecting line-sequential in the sections T A1 , T A2 , T A3 and T B1 , T B2 , T B3 . As for the scanning signals phi 1, a positive write section T W1 in positive write voltage V W1 is negative write section T W2 negative write voltage V W2 in the positive static period T H1 in the positive hold voltage V H1 In the negative holding section TH2 , a negative holding voltage TH2 is applied.

従来の駆動方法で問題が生ずるのは、2端子型スイッ
チング素子の液晶表示画素の駆動能力が十分でない場合
である。2端子型スイッチング素子の駆動能力で問題と
なるのは次の2点である。
A problem occurs in the conventional driving method when the driving capability of the liquid crystal display pixel of the two-terminal switching element is not sufficient. There are the following two problems in the driving capability of the two-terminal switching element.

(イ) 容量比α=CLC/CSW CSW;2端子型スイッチング素子容量 CLC;液晶表示画素容量 (ロ) 書き込み区間での電流駆動能力 この2つの値が十分でない場合、書き込み区間での書
き込み特性(ダイナミックレンジ)と、保持区間での保
持特性(クロストーク)に問題が出る。クロストークに
ついては、全体を均一にする事は可能でコントラストは
落ちるが致命的ではない。しかし、書き込み特性は極端
な場合は表示も不可能になる点で問題が大きい。
(B) Capacitance ratio α = C LC / C SW C SW ; Two-terminal switching element capacitance C LC ; Liquid crystal display pixel capacitance (b) Current drive capability in the write section If these two values are not sufficient, The problem arises in the write characteristics (dynamic range) and the retention characteristics (crosstalk) in the retention section. Regarding crosstalk, it is possible to make the whole uniform and the contrast is reduced, but it is not fatal. However, the writing characteristics are problematic in that display is not possible in extreme cases.

容量比αは液晶表示画素が大きくCLC/CSWが4〜5以
上取れるような設計では問題がない。しかし、液晶プロ
ジェクターや液晶ビュウファインダー等小型高密度の用
途ではCLC/CSWは3以下、極端な場合は1を割るケース
さえ生じ従来の駆動法では対応できない。
The capacitance ratio α has no problem in a design in which the liquid crystal display pixel is large and CLC / CSW can be 4 to 5 or more. However, C LC / C SW 3 or less in the liquid crystal projectors, liquid crystal Shipping Accessories finder such as a small high-density applications, extreme cases can not be handled by even occur prior driving method case dividing 1.

書き込み区間での電流駆動能力についても、ダイオー
ドリング等では良好だが素子面積の小さな小型高密度の
用途には問題となる。まして、生産性を考慮してより構
造の簡単なMIMを用いた場合には非常に問題である。
The current drivability in the writing section is good for a diode ring or the like, but poses a problem for small and high-density applications with a small element area. Furthermore, it is very problematic when MIM having a simpler structure is used in consideration of productivity.

本発明の従来方式の欠点の解決を目的としている。即
ち、容量比や書き込み区間での電流駆動能力の十分でな
い2端子型スイッチング素子でも駆動可能な2端子型ア
クティブマトリクス液晶表示装置の駆動方法を提供する
事が本発明の目的である。
It is aimed at overcoming the disadvantages of the prior art scheme of the present invention. That is, an object of the present invention is to provide a driving method of a two-terminal type active matrix liquid crystal display device which can be driven even by a two-terminal type switching element having insufficient capacity ratio and current driving capability in a writing section.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は走査信号に工夫を加える事により、従来にお
ける2端子型アクティブマトリクス液晶表示装置の駆動
方法を改善している。即ち、書き込み区間の前にはこの
書き込み電圧とは逆極性で且つ書き込み電圧の絶対値と
等しいか書き込み電圧以上の大きさの絶対値の電圧のリ
セット電圧をとるリセット区間を設けた走査信号を用い
る事を特徴としている。
The present invention improves the conventional method of driving a two-terminal type active matrix liquid crystal display device by modifying the scanning signal. That is, before the writing section, a scanning signal having a reset section having a reset voltage having a polarity opposite to the writing voltage and having a voltage having an absolute value equal to or greater than the writing voltage and having an absolute value greater than or equal to the writing voltage is used. It is characterized by things.

〔実施例〕〔Example〕

以下、実施例に基づき本発明を説明する。 Hereinafter, the present invention will be described based on examples.

第1図は本発明の2端子型アクティブマトリクス液晶
表示装置の駆動方法に於ける走査信号波形の実施例であ
る。
FIG. 1 is an embodiment of a scanning signal waveform in a method for driving a two-terminal type active matrix liquid crystal display device according to the present invention.

走査信号φ 、φ 、φ はそれぞれのフィー
ルドTA及びTBの区間TA1、TA2、TA3及びTB1、TB2、TB3
線順次に選択される信号である。走査信号φ につい
て見ると、正の書き込み区間TW1では正の書き込み電圧V
W1が負の書き込み区間TW2では負の書き込み電圧VW2が、
正の保持区間TH1では正の保持電圧VH1が負の保持区間T
H2では負の保持電圧VH2が印加される。この点では第4
図に示した従来例と同様である。本発明の走査信号の特
徴は書き込み区間の前にこの書き込み電圧とは逆極性で
且つ書き込み電圧の絶対値と等しいかそれ以上大きさの
絶対値の電圧のリセット電圧をとるリセット区間を設け
た事にある。即ち、正の書き込み区間TW1の前には負の
リセット区間TR1、負の書き込み区間TW2の前には正のリ
セット区間TR2を設け、それぞれのリセット電圧を書き
込み電圧より絶対値で高めに設定している。
Scanning signal φ 1 *, φ 2 *, φ 3 * in each field T A and T interval T A1 of B, T A2, T A3 and T B1, T B2, line-sequentially the signal selected by the T B3 is there. Looking at the scanning signal φ 1 * , in the positive write period T W1 , the positive write voltage V
W1 is a negative writing period T W2 negative write voltage V W2 in,
In the positive holding section T H1 , the positive holding voltage V H1 is changed to the negative holding section T.
At H2 , a negative holding voltage V H2 is applied. In this regard, the fourth
This is the same as the conventional example shown in FIG. A feature of the scanning signal of the present invention is that a reset section is provided before the write section, in which a reset voltage of a voltage having a polarity opposite to the write voltage and having an absolute value greater than or equal to the absolute value of the write voltage is obtained. It is in. That is, a negative reset section T R1 is provided before the positive write section T W1 , and a positive reset section T R2 is provided before the negative write section T W2 , and the respective reset voltages are made higher in absolute value than the write voltage. Is set to

第7図は本発明の他の実施例の走査信号である。 FIG. 7 shows a scanning signal according to another embodiment of the present invention.

第1図Zは第1図の実施例の走査信号群の各タイミン
グでの最大電圧11と最小電圧12を示している。本実施例
ではいわゆる行毎反転法を用いているため、走査信号の
書き込み電圧の極性に応じて最大電圧11、最小電圧12が
変動する。書き込み電圧が正のタイミングでは最大電圧
と最小電圧の差はVR2−VH2、負のタイミングではVH1−V
R1となる。駆動回路の動作電圧を節約するには、駆動回
路の動作電圧をこの最大電圧と最小電圧の差、ここでは
VR2−VH2(VH1−VR1)に設定できる事が公知である。そ
のためにはこの2つのタイミング間電圧差VR2−VH1(V
H2−VR1)を持つ信号(第7図X)を第1図の走査信号
から差し引けば第7図の走査信号φ **、φ **
φ **となり、動作電圧がVR2−VH1(VH2−VR1)の分
だけ節約出来る。
FIG. 1Z shows the maximum voltage 11 and the minimum voltage 12 at each timing of the scanning signal group of the embodiment of FIG. In this embodiment, since the so-called row-by-row inversion method is used, the maximum voltage 11 and the minimum voltage 12 vary depending on the polarity of the write voltage of the scanning signal. The difference between the maximum voltage and minimum voltage programming voltage is positive timing V R2 -V H2, V H1 -V-negative timing
It becomes R1 . To save the operating voltage of the driving circuit, the operating voltage of the driving circuit is calculated by subtracting the operating voltage of this driving circuit from the maximum voltage and the minimum voltage.
It is known that V R2 −V H2 (V H1 −V R1 ) can be set. For this purpose, the voltage difference between these two timings V R2 −V H1 (V
H2 -V R1) a having signal (Fig. 7 X) a seventh view of a scanning signal phi 1 ** by subtracting from the scanning signal of FIG. 1, phi 2 **,
φ 3 ** , and the operating voltage can be reduced by V R2 −V H1 (V H2 −V R1 ).

本実施例ではリセット区間のタイミングを直前の走査
線の書き込み区間で行ったが、独立に或はずらしても構
わない。
In this embodiment, the timing of the reset section is set in the immediately preceding write section of the scanning line, but may be independently or staggered.

又、リセット区間の長さは後述する第6図の説明図の
如く書き込み区間よりも長く取った方が本発明の効果が
大きい。
The effect of the present invention is greater when the length of the reset section is longer than that of the write section as shown in FIG. 6 described later.

〔発明の効果〕〔The invention's effect〕

次に本発明の効果を説明する。 Next, the effects of the present invention will be described.

第5図は従来例の書き込み区間の電圧状態を示す説明
図である。データ信号をVDとすると、書き込み区間TW1
の前の保持区間TH2では保持電圧VH2+データ電圧VDが、
書き込み区間の後の保持区間TH1では保持電圧VH1+デー
タ電圧VDが印加される。書き込み区間TW1ではデータ信
号がOFFの時にはVW1+VD(OFF)が、データ信号がONの
時はVW1+VD(ON)がそれぞれ印加される。
FIG. 5 is an explanatory diagram showing a voltage state in a writing section in a conventional example. When the data signal and V D, write section T W1
Holding period T H2 in the holding voltage V H2 + data voltage V D of the front of,
In the holding section T H1 after the writing section, the holding voltage V H1 + the data voltage V D is applied. In the write section TW1 , V W1 + V D (OFF) is applied when the data signal is OFF, and V W1 + V D (ON) is applied when the data signal is ON.

保持区間TH2での液晶表示画素に印加されている電圧
をVaとする。書き込み区間TW1でデータ信号がOFFの時に
はVW1+VD(OFF)の電圧が印加され、もし容量比CLC/C
SWが1の時には容量結合で瞬間的に液晶表示画素に印加
される電圧はVd2となる。このように容量比が十分に取
れていない場合には本来ならば2端子型スイッチング素
子に印加される電圧VW1+VD(OFF)−VaがCLC/(CSW+C
LC)の割合でしか印加されない。これでも2端子型スイ
ッチング素子の書き込み区間での電流駆動能力が十分に
あればよいが、不十分な場合には書き込み区間TW1で電
流が液晶表示画素に注入されず、書き込み後の液晶表示
画素に印加される電圧Ve2と書き込み前の電圧Vd2の差は
十分に取れない。同様にデータ信号がONの時にはVW1+V
D(ON)の電圧が印加され、液晶表示画素に印加される
電圧はVd1となり、書き込み後の液晶表示画素に印加さ
れる電圧Ve1と書き込み前の電圧Vd1の差は十分に取れな
い。保持区間に電圧が保持電圧VH1+データ電圧VDとな
ると容量結合によって、液晶表示画素に印加される電圧
はVf1、Vf2となる。この電圧が液晶表示画素を駆動する
事になるが、以上のような容量比と書き込み区間での電
流駆動能力が十分でない場合にはON書き込みの際の液晶
駆動電圧Vf1とOFF書き込みの場合の液晶駆動電圧Vf2
差が十分取れず、十分なコントラストをとる事ができな
い。
The voltage applied to the liquid crystal display pixels in the holding section TH2 is defined as Va. When the data signal is OFF in the writing section TW1 , a voltage of V W1 + V D (OFF) is applied, and if the capacitance ratio C LC / C
When SW is 1, the voltage instantaneously applied to the liquid crystal display pixel by the capacitive coupling becomes Vd2 . As described above, when the capacitance ratio is not sufficient, the voltage V W1 + V D (OFF) −Va normally applied to the two-terminal switching element is C LC / (C SW + C
LC ). Even this may be at the current drive capability of the write period of the two-terminal type switching element is sufficient, but no current in the write period T W1 if insufficient is injected into the liquid crystal display pixel, the liquid crystal display pixel after the writing Cannot be sufficiently obtained between the voltage Ve2 applied to the memory cell and the voltage Vd2 before writing. Similarly, when the data signal is ON, V W1 + V
A voltage is applied D (ON), the voltage applied to the liquid crystal display pixel difference between the voltage V e1 and before writing voltage V d1 applied next V d1, a liquid crystal display pixel after the writing is not sufficiently taken . When the voltage becomes the holding voltage V H1 + the data voltage V D in the holding section, the voltages applied to the liquid crystal display pixels become V f1 and V f2 due to capacitive coupling. This voltage drives the liquid crystal display pixels, but when the capacity ratio and the current driving capability in the writing section are not sufficient as described above, the liquid crystal driving voltage Vf1 for ON writing and the liquid crystal driving voltage VOFF for OFF writing A sufficient difference in the liquid crystal drive voltage Vf2 cannot be obtained, and a sufficient contrast cannot be obtained.

従来例の最大の問題点は書き込み区間の最初の状態で
2端子型スイッチング素子に十分な電圧が掛からない点
に集約される。
The biggest problem of the conventional example is that a sufficient voltage is not applied to the two-terminal switching element in the initial state of the writing section.

第6図は本発明の実施例の書き込み区間の電圧状態を
示す説明図である。本発明では書き込み区間TW1の前に
逆極性のリセット電圧VR1が印加されるリセット区間TR1
を有する事が従来例と異なる。リセット区間の初めには
容量結合で瞬間的に液晶表示画素に印加される電圧はVb
となり、リセット区間で電流が液晶表示画素に注入さ
れ最後にはVc となる。書き込みTW1でデータ信号がOFF
の時には液晶表示画素に印加される電圧はVd2 、ONの
時にはVd1 となる。ここで注目すべきは従来例の電圧V
d1、Vd2と本発明の実施例の電圧Vd1 、Vd2 の違いで
ある。リセット区間の追加によって本発明の実施例の電
圧Vd1 、Vd2 は従来例の電圧Vd1、Vd2に比べかなり小
さくなっている。この結果書き込み区間に2端子型スイ
ッチング素子に印加される電圧が大きくなる。このよう
に本発明では従来例の最大の問題点を大幅に改善でき
る。その結果、最終的に液晶表示画素に印加される電圧
Vf1 とVf2 の差は大きくなり、コントラストが増大す
る。
FIG. 6 is an explanatory diagram showing a voltage state in a writing section according to the embodiment of the present invention. In the present invention, the reset section T R1 in which the reset voltage V R1 of the opposite polarity is applied before the write section T W1.
Is different from the conventional example. At the beginning of the reset period, the voltage instantaneously applied to the liquid crystal display pixel by capacitive coupling is V b
* , The current is injected into the liquid crystal display pixel in the reset period, and finally becomes V c * . Data signal is turned off at write TW1
The liquid crystal display voltage applied to the pixel V d2 *, the V d1 * when the ON when the. What should be noted here is the voltage V of the conventional example.
This is the difference between d1 and Vd2 and the voltages Vd1 * and Vd2 * of the embodiment of the present invention. With the addition of the reset section, the voltages V d1 * and V d2 * of the embodiment of the present invention are considerably smaller than the voltages V d1 and V d2 of the conventional example. As a result, the voltage applied to the two-terminal switching element during the writing period increases. As described above, according to the present invention, the greatest problem of the conventional example can be greatly improved. As a result, the voltage finally applied to the liquid crystal display pixel
The difference between V f1 * and V f2 * increases, and the contrast increases.

以上のリセット区間TR1に於けるリセット電圧VR1は、
本発明の効果を得るには書き込み電圧VW1、VW2の絶対値
より等しいか大きくなくてはならない。リセット電圧が
書き込み電圧よりも小さな場合にはVd1 、Vd2
Vd1、Vd2と等しくなり本発明の効果が得られない。
In the reset voltage V R1 to the aforementioned reset period T R1,
In order to obtain the effect of the present invention, the write voltages VW1 and VW2 must be equal to or greater than the absolute values. When the reset voltage is smaller than the write voltage, V d1 * and V d2 *
It becomes equal to V d1 and V d2, and the effect of the present invention cannot be obtained.

以上の如く、本発明に依れば従来十分なコントラスト
が得られなかった低容量比、低電流駆動能力の2端子型
スイッチグ素子であっても高コントラストでの駆動が可
能となる。
As described above, according to the present invention, it is possible to drive a high-contrast two-terminal switching element having a low capacitance ratio and a low current driving capability, which has not been able to obtain sufficient contrast.

尚、本実施例では書き込み区間の直前にリセット区間
を設けたが、間に他の電圧の区間を挿入しても本発明の
効果は変わらず本発明に包含される。
In this embodiment, the reset section is provided immediately before the write section. However, even if another voltage section is inserted therebetween, the effects of the present invention are not changed and are included in the present invention.

又、本実施例では走査信号φ 、φ 、φ
書き込み区間TA1、TA2、TA3及びTB1、TB2、TB3を連続さ
せたが、間に適当な区間を挿入しても構わない。
Further, in this embodiment, the writing sections T A1 , T A2 , T A3 and T B1 , T B2 , T B3 of the scanning signals φ 1 * , φ 2 * , φ 3 * are made continuous, but an appropriate section is provided therebetween. May be inserted.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の2端子型アクティブマトリクス液晶表
示装置の駆動方法の実施例に於ける走査信号を示す波形
図、第2図および第3図はいずれも従来技術に係る典型
的な2端子型アクティブマトリクス液晶表示装置の基本
構成を示す回路図、第4図は従来技術に係る2端子型ア
クティブマトリクス液晶表示装置の駆動方法に於ける走
査信号を示す波形図、第5図は従来技術における書き込
み区間前後における液晶表示画素への電圧印加状態を示
す波形図、第6図は本発明の実施例に於ける書き込み区
間前後に於ける液晶表示画素への電圧印加状態を示す波
形図、第7図は本発明の駆動方法の走査信号の他の実施
例を示す波形図である。 5……データ線、 6……走査線、 10……液晶表示画素、 20……ダイオードリング、 30……MIM、 φ 、φ 、φ ……走査信号。
FIG. 1 is a waveform diagram showing a scanning signal in an embodiment of a method for driving a two-terminal type active matrix liquid crystal display device of the present invention, and FIGS. 2 and 3 are all typical two-terminals according to the prior art. FIG. 4 is a circuit diagram showing a basic structure of a liquid crystal display device of the active matrix type, FIG. 4 is a waveform diagram showing a scanning signal in a driving method of a two-terminal type active matrix liquid crystal display device according to the prior art, and FIG. FIG. 6 is a waveform diagram showing the state of voltage application to the liquid crystal display pixel before and after the writing period. FIG. 6 is a waveform diagram showing the state of voltage application to the liquid crystal display pixel before and after the writing period in the embodiment of the present invention. FIG. 9 is a waveform chart showing another embodiment of the scanning signal of the driving method of the present invention. 5 ...... data line, 6 ...... scanning lines, 10 ...... liquid crystal display pixels, 20 ...... diode ring, 30 ...... MIM, φ 1 * , φ 2 *, φ 3 * ...... scan signal.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】マトリクス配置されたデータ線及び走査線
と、該データ線及び走査線の交点に対応して設けられた
液晶表示画素と少なくとも1つの2端子型スイッチング
素子とを有し、前記走査線に印加される走査信号と前記
データ線に印加されるデータ信号により液晶表示画素が
駆動される2端子型アクティブマトリクス液晶表示装置
の駆動方法に於て、 2端子型スイッチング素子は非線形抵抗素子であり、該
走査信号は正負の書き込み電圧をとる書き込み区間を有
し、 該書き込み区間の前には該書き込み電圧とは逆極性で且
つ前記書き込み電圧の絶対値と等しいか前記書き込み電
圧以上の大きさの絶対値の電圧のリセット区間を有する 事を特徴とする2端子型アクティブマトリクス液晶表示
装置の駆動方法。
1. A scanning device comprising: data lines and scanning lines arranged in a matrix; a liquid crystal display pixel provided at an intersection of the data lines and the scanning lines; and at least one two-terminal switching element; In a method for driving a two-terminal active matrix liquid crystal display device in which a liquid crystal display pixel is driven by a scanning signal applied to a line and a data signal applied to the data line, the two-terminal switching element is a non-linear resistance element. The scanning signal has a write section having positive and negative write voltages, and before the write section, has a polarity opposite to the write voltage and equal to or greater than the absolute value of the write voltage. A method for driving a two-terminal type active matrix liquid crystal display device, comprising a reset section of a voltage having an absolute value of:
【請求項2】2端子型スイッチング素子はMIM素子であ
る 事を特徴とする請求項1記載の2端子型アクティブマト
リクス液晶表示装置の駆動方法。
2. The method of driving a two-terminal active matrix liquid crystal display device according to claim 1, wherein the two-terminal switching element is a MIM element.
【請求項3】2端子型スイッチング素子の静電容量は表
示画素の静電容量の3分の1より大きい 事を特徴とする請求項1記載の2端子型アクティブマト
リクス液晶表示装置の駆動方法。
3. The method of driving a two-terminal active matrix liquid crystal display device according to claim 1, wherein the capacitance of the two-terminal switching element is larger than one third of the capacitance of the display pixel.
JP21039389A 1989-08-15 1989-08-15 Driving method of two-terminal type active matrix liquid crystal display device Expired - Lifetime JP2851314B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21039389A JP2851314B2 (en) 1989-08-15 1989-08-15 Driving method of two-terminal type active matrix liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21039389A JP2851314B2 (en) 1989-08-15 1989-08-15 Driving method of two-terminal type active matrix liquid crystal display device

Publications (2)

Publication Number Publication Date
JPH0373924A JPH0373924A (en) 1991-03-28
JP2851314B2 true JP2851314B2 (en) 1999-01-27

Family

ID=16588589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21039389A Expired - Lifetime JP2851314B2 (en) 1989-08-15 1989-08-15 Driving method of two-terminal type active matrix liquid crystal display device

Country Status (1)

Country Link
JP (1) JP2851314B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4829196B2 (en) * 2007-09-28 2011-12-07 株式会社リコー Projection optical device

Also Published As

Publication number Publication date
JPH0373924A (en) 1991-03-28

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