JP2851027B2 - Semiconductor switching device having buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate turn-off (GT)
O) Thyristor, static induction thyristor (SI thyristor), insulated gate bipolar transistor (IGB)
T) In a power semiconductor device such as a MOS control thyristor (MCT), a buffered anode or anode-emitter structure is provided in a predetermined short-circuit structure to fire without affecting other characteristics having a trade-off relationship. The present invention relates to a semiconductor switching device having a high-speed and high-efficiency buffer with improved characteristics and turn-off characteristics.

[0002]

2. Description of the Related Art It is common for thyristors to employ an anode short-circuit structure with a pin-type buffer for the purpose of latching up to set a low on-voltage and further reducing turn-on and turn-off times.

FIGS. 27 and 28 schematically show an example of an anode short-circuit structure in a conventional GTO for the purpose of operating at a high frequency of 1 kHz or more. 27, reference numeral 1 denotes a cathode region, 2 denotes a gate region, 3 denotes an anode region, and 4 denotes an anode short-circuit region. Reference numeral 5 denotes an n-buffer layer, and reference numeral 6 denotes an n-base layer. FIG. 28 shows how a large number of anode short-circuit regions 4 are arranged. In the structure examples of FIG. 27 and FIG. 28, the tail time related to the loss is longest in the turn-off characteristic, and the overall loss is also large.

FIGS. 29 and 30 schematically show an example of a short circuit structure in a conventional SI thyristor.

The structure shown in FIG. 29 has a problem that it is difficult to fire or does not fire (latch up does not occur) because the short-circuit resistance is small in the structure with a buffer.

FIG. 31 schematically shows a waveform of a characteristic which makes it difficult to fire in the buffered SI thyristor using the anode short-circuit structure of FIG. FIG. 32 is a schematic diagram of a characteristic that does not fire, and FIG. 33 is a schematic diagram of a measurement circuit.

FIG. 34 shows electronic processing when the structure of FIG. 29 is applied to a structure without a buffer. n base layer (n _B ) 6 and p anode region (p _E ) 3
The depletion layer according to the diffusion potential between the n base layer (n _B )
6 and short-circuit resistance is generated until electrons are expelled into the n ⁺ anode short-circuit region 4 to ignite.

FIG. 35 shows electronic processing when the structure of FIG. 29 is applied to an example of a structure with a buffer. N buffer layer 5 and p anode region (p emitter)
(P _E ) 3, the width of the depletion layer is small, and the short-circuit resistance generated while electrons remaining in n base layer 6 and n buffer layer 5 are extruded to n ⁺ region of anode short-circuit region 4 is considerably small. . Therefore, the electrons travel to the p anode region (p _E ) 3
Almost no holes are injected into the anode short-circuit region (n ⁺ ) 4 before the holes are injected from the anode, resulting in a characteristic that the firing is difficult or impossible.

FIG. 2 shows an example of the anode short-circuit structure shown in FIG.
Although the ignition characteristics are excellent as compared with the structure example of No. 9, the ratio of the turn-off loss as the heat loss generated at the time of high-frequency operation is increased, and the total generated loss is increased. It depends on the carrier lifetime control for the processing of the electrons in the n base layer (n _B ) 6 which existed in the ON state, and an increase in the ON voltage and an increase in the leak current caused by the lifetime control. This is because the total loss has increased.

[0010]

The object of the present invention is to provide a pin
It is an object of the present invention to provide a semiconductor switching element having a buffer in which the ignition characteristics are improved and the turn-on characteristics are not adversely affected, and the tail characteristics are improved in the turn-off characteristics in a buffered anode short-circuit structure.

[0011]

The construction of the present invention is as follows. That is, in a semiconductor switching element having a buffer, a low resistivity p + layer (p anode region (pE2) (31) having a relatively shallow junction depth) having a relatively shallow junction depth, The resistivity or the junction depth of a predetermined low resistivity is relatively shallowly formed n
+ Layers (anode short-circuit areas 4) are alternately arranged in the vertical direction, and the p + layer (3
1) and ap + layer (p anode region (pE1) (30) having a relatively deep junction depth formed with a relatively low junction depth in the lateral direction relative to the n + layer (4). ) Is provided as a semiconductor switching element having a buffer, characterized by having an anode-emitter short-circuit structure in which the semiconductor switching elements are periodically arranged.

[0012]

1 to 3 show an anode short-circuit structure according to the present invention. FIG. 1 shows a schematic cross-sectional structure diagram and a corresponding impurity distribution diagram of a semiconductor switching element having an n-buffer (epi-buffer) formed by epitaxial growth as a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional structure diagram and impurity distribution diagram of a semiconductor switching element having an n-buffer (diffusion + epi-buffer) formed by a diffusion process and epitaxial growth as a second embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram and impurity distribution diagram of a semiconductor switching element having an n-buffer (diffusion buffer) formed by a diffusion process according to a third embodiment of the present invention. FIG. 4 shows an impurity concentration distribution near the anode short-circuit structure in the epi-buffer. 1 to 3, reference numeral 1 denotes a cathode region (n _E ), 2 denotes a buried gate region (p _B ), 30 denotes a p anode region (p _E1 ) having a relatively deep junction depth, and 31 denotes a relatively shallow region. A p-anode region (p _E2 ) having a junction depth, 4 is an anode short-circuit region (n), 5 is an n-buffer layer, and 6 is an n-base layer (n _B ).

[0013] Regarding the ignition characteristics, the p anode region (p _E ) is divided into a p anode region (p _E1 ) having a relatively deep junction depth and a p anode region (p _E2 ) having a relatively shallow junction depth. And the anode short-circuit region (n,
In 4), for example, when the area is reduced to about 6 μm × 9 μm, a short-circuit resistance occurs, and the p anode region (p _E1 ,
Holes are injected from p _E2 ) to obtain good ignition characteristics.

There is almost no difference in the turn-on characteristics as compared with a structure in which no short-circuit region is provided in the p-anode region, and similar characteristics can be obtained.

The tail current characteristic in the turn-off characteristic can be described in a process of processing electrons in two stages as described later (FIGS. 6 and 7).

FIG. 5 is an enlarged view of an anode short-circuit structure in a semiconductor switching device having a buffer according to the present invention.

FIGS. 6 and 7 are diagrams for explaining the principle of operation in which electrons accumulated in the n base layer (n _B ) 6 and the n buffer layer 5 during the tail period are discharged to the anode side. 6 is an explanatory view of the I stage (corresponding to the cross section taken along the line AA 'in FIG. 5), and FIG. 7 is an explanatory view of the II stage (B-B in FIG. 5).
B ′).

Eliminating electrons earlier during the tail period is a major factor in reducing the turn-off loss of the device, and also leads to a higher speed of the device.

The process of discharging electrons to the anode is performed in two stages in the anode short-circuit structure of the semiconductor switching device having the buffer according to the present invention, which will be described below.

[Step I] A depletion layer is generated in the n-buffer layer 5 due to a diffusion potential generated between the p-anode region (p _E1 ) 30 having a relatively deep junction depth and the n-buffer layer 5. Was used. That is, the n base layer (n _B )
6 and the electrons accumulated in the n-buffer layer 5 tend to move to a lower potential, so that the p anode region (p _E1 ) 30 having a relatively deep junction depth and the relatively shallow junction depth It flows between the p anode regions (p _E2 ) 31 which have the same.

[Step II] A relatively shallow region is formed between the p anode region (p _E1 ) 30 having a relatively deep junction depth and the p anode region (p _E2 ) 31 having a relatively shallow junction depth. Since the n ⁺ anode short-circuit region 4 having a relatively shallow junction depth exists between the p _E2 layer (31) having the junction depth and the p _E2 layer (31), the relative short-circuit region is formed in the same manner as the operation described in the I stage. A depletion layer is generated in the n-buffer layer 5 due to the diffusion potential between the p-anode region (p _E2 ) 31 having a relatively shallow junction depth and the n-buffer layer 5, and a high potential is applied to the n ⁺ anode short-circuit region 4. Form. Therefore, the electrons are in the p _E2 layer (3
It flows into the n ⁺ anode short-circuit region 4 between 1) and the p _E2 layer (31), and is eventually discharged to the anode side.

After the stages I and II, the electrons remaining in the n base layer (n _B ) 6 and the n buffer layer 5 are discharged to the anode side to suppress the injection of holes from the anode side and reduce the tail current. It is possible to reduce the size and tail time.

8 to 11 show examples applied to various devices. FIG. 8 shows an embodiment in which the present invention is applied to a GTO. In FIG. 8, 1 is a cathode region (n _E ) of GTO, 2 is a gate region (p _B ), and 30 is a p anode having a relatively deep junction depth. A region (p _E1 ), 31 is a p anode region (p _E2 ) having a relatively shallow junction depth, 4 is an n ⁺ anode short-circuit region, 5 is an n buffer layer, and 6 is an n base layer (n
_B ). FIG. 9 is a diagram showing an embodiment in which the present invention is applied to a buried gate type SI thyristor. Since the reference numbers correspond to those in FIG. 8, the description of each area is omitted.
In FIG. 9, the gate region 2 has a buried structure. FIG.
0 is a diagram showing an embodiment in which the present invention is applied to a surface gate type SI thyristor. Each reference number corresponds to FIG. 8 and FIG. In FIG. 10, the gate region 2 has a surface gate structure. FIG. 11 is a diagram showing an embodiment in which the present invention is applied to an IGBT. 8, 9 and 1
Corresponds to 0. Here, 7 is a p base layer (p _B ) of the IGBT, 8 is an n collector region (n _E ) of the IGBT, and 9 is a gate electrode of the IGBT.

A method of manufacturing a semiconductor switching element having a buffer according to the present invention will be described with reference to FIGS.

(A) The n-buffer layer 5 is formed on the n-base layer 6 by three methods shown in FIGS. 12 is a process chart for forming the n-buffer layer 5 by the epitaxial growth method, FIG. 13 is a process for forming the n-buffer layer 5 by the diffusion + epitaxial growth method, and FIG. In each process diagram, the impurity density distribution in the n buffer layer 5 and the n base layer 6 is also schematically shown. It can be seen that different impurity distribution densities occur depending on the difference in the process of forming the n-buffer layer 5.

(B) Next, the p _B layer 2 serving as a gate region
Then, a p _E1 layer 30 serving as a p anode region having a relatively deep junction depth is formed (FIG. 15).

[0027] (c) Next, the p _B layer 2 serving as the buried gate region by epitaxial growth embedding by epitaxial growth layer 10 (FIG. 16).

(D) Next, an n _E layer 1 serving as a cathode region is formed (FIG. 17).

(E) As an anode short-circuit structure, a p _E2 layer 31 is formed as a p anode region having a relatively shallow junction depth (FIG. 18).

(F) Next, similarly, as an anode short-circuit structure, an anode short-circuit region 4 (n ⁺ ) having a relatively shallow junction depth is formed (FIG. 19).

(G) The anode short-circuit region (n
+) 4 and dimensions of the pE1 layer 30 and the pE2 layer 31 are shown in FIG.
Shown in N + anode short-circuit region 4 with dimensions of 6 μm × 9 μm
Was formed at a pitch of 22 μm vertically and 32 μm horizontally.

As a semiconductor switching element having a buffer, a buried gate type SI thyristor (FIG. 9) was experimentally manufactured, and the results are shown in FIGS. Distribution of ON voltage _VTM with respect to resistivity of n-buffer layer 5 (epi-buffer) formed by epitaxial growth (device diameter φ32
(in the case of μm) is shown in FIG. When the resistivity of the epi-buffer is 1.0 Ω · cm, about V _TM = 3.5 V (600 A), 10
About V _™ = 3.0 V (600 A) is obtained at Ω · cm. The ON voltage _VTM tends to decrease as the resistivity of the epibuffer increases.

FIG. 22 shows the breakdown voltage of the device manufactured in FIG. Epibuffer resistivity is 1.0Ω · cm
And a withstand voltage of about 1.6 kV is obtained at 10.0 Ω · cm.

FIG. 23 and FIG. 24 show the ignition characteristics in the case of an epi-buffer of 1.0 Ω · cm. FIG. 23 shows time dependence, and FIG. 24 shows VI characteristics. I _A = 600
At A, V _TM = 3.5 V was obtained.

FIG. 25 shows a comparison of the turn-off loss E _off (mJ / pulse) with respect to the ON voltage _VTM . That is,
30 shows a comparison between the conventional anode short-circuit structure shown in FIGS. 27 and 30 and the structure of the present invention. Switching condition is 12
50V / snubber capacitor C _S at 300A is 0.1μ
F, V _DM (overshoot peak voltage) is 1670V
I adjusted to. In the structure example of the present invention, the turn-off loss E _off
However, when V _TM = 3.5 V, it is reduced to about し て も as compared with the conventional example shown in FIG.

Referring to FIG. 25, the reason why the structure of the present invention has a smaller turn-off loss is that electrons remaining in the n base layer (n _B ) 6 and the n buffer layer 5 during the tail period are explained with reference to FIGS. This is because the two-stage process quickly pulls out the anode.

FIG. 26 shows a comparison of turn-off waveforms of three types of devices having an on-voltage _VTM of about 3.5 V. The turn-off switching conditions are the same as in FIG.
00A, snubber capacitor C _S is 0.1 μF, V
_DM (overshoot peak voltage) is 1670V, 12
5 ° C. In the structure of the present invention, the tail time is clearly short, and the tail current is small.

[0038]

According to the present invention, an anode p-layer is periodically arranged in an anode structure of a pin thyristor,
The p-layer and the n-layer having a junction depth relatively smaller than the anode p-layer are alternately arranged in the vertical direction, so that the majority carriers remaining in the base layer when the thyristor is turned off from on are removed. The tail time for pulling out can be efficiently reduced in between. That is, according to the present invention, a semiconductor having a buffer having improved ignition characteristics and improved tail characteristics in turn-off characteristics without adversely affecting turn-on characteristics, resulting in reduced turn-off loss and reduced turn-off time A switching element can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional structural view of a semiconductor switching element having an epi-buffer as a first embodiment of the present invention and a corresponding impurity distribution diagram.

FIG. 2 is a schematic cross-sectional structure diagram and an impurity distribution diagram of a semiconductor switching element having a diffusion + epi buffer as a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional structure diagram and an impurity distribution diagram of a semiconductor switching element having a diffusion buffer according to a third embodiment of the present invention.

FIG. 4 is an impurity concentration distribution diagram of a short-circuited anode in an epi-buffer.

FIG. 5 is a diagram showing an anode short-circuit structure.

FIG. 6 is a diagram showing processing of electrons during a tail period,
The I stage (AA ′ in FIG. 5) is shown.

FIG. 7 is a diagram showing electronic processing during a tail period,
The stage II (BB 'in FIG. 5) is shown.

FIG. 8 is a diagram showing an embodiment in which the present invention is applied to a GTO.

FIG. 9 is a diagram showing an embodiment in which the present invention is applied to a buried gate SI thyristor.

FIG. 10 is a diagram showing an embodiment in which the present invention is applied to a surface gate type SI thyristor.

FIG. 11 is a diagram showing an embodiment in which the present invention is applied to an IGBT.

FIG. 12 is a diagram illustrating a buffer forming process by an epitaxial growth method.

FIG. 13 is a view showing a buffer forming process by diffusion + epitaxial growth method.

FIG. 14 is a diagram illustrating a buffer forming process by a diffusion method.

FIG. 15 is a process diagram of forming a p _E1 layer 30 serving as a p anode region having a relatively deep junction depth with a p _B layer 2 serving as a gate region.

FIG. 16 is a view showing a buried gate epitaxial process.

FIG. 17 is a process chart of forming an n _E layer 1 serving as a cathode region.

FIG. 18 is a process diagram of forming a p _E2 layer 31 to be a p anode region having a relatively shallow junction depth.

FIG. 19 is a process chart of forming an anode short-circuit region 4 (n ⁺ ).

FIG. 20: Anode short-circuit region 4 (n ⁺ ) and p _E1 layer 3
FIG. 3 is a schematic diagram of dimensions of a 0, p _E2 layer 31.

FIG. 21 is a diagram showing a distribution of an on-voltage (V _™ ) with respect to a resistivity (Ω · cm) of an epi-buffer.

FIG. 22 is a diagram showing the withstand voltage of the device with respect to the resistivity (Ω · cm) of the epibuffer.

FIG. 23 is a diagram showing the time dependence of the ignition characteristics in an epi-buffer of 1.0 Ω · cm.

FIG. 24 is a diagram showing VI characteristics of firing characteristics in an epi buffer of 1.0 Ω · cm.

FIG. 25 is a diagram showing a comparison of a turn-off loss with respect to an on-voltage (V _™ ).

FIG. 26 is a diagram showing a comparison of turn-off characteristic waveforms for three types of devices having an on-voltage (V _™ ) of about 3.5V.

FIG. 27 is a diagram showing an example of a conventional anode short circuit structure with a buffer of a GTO.

FIG. 28 is an example of a conventional GTO (a plan view on the anode side).

FIG. 29 is a structural example of a conventional SI thyristor (SI short-circuit structure).

FIG. 30 is a structural example (waveform anode structure) of a conventional SI thyristor.

31 is a diagram showing waveforms of characteristics that make it difficult to fire in the buffered SI thyristor with the anode short circuit shown in FIG. 29.

32 is a diagram showing a waveform of a characteristic of not firing in the buffered SI thyristor with the anode short circuit of FIG. 29;

FIG. 33 is a diagram showing a circuit for measuring a firing waveform in the buffered SI thyristor with the anode short circuit shown in FIG. 29;

34 is a diagram showing an electrostatic induction effect in the case where there is no buffer in the anode short circuit of FIG. 29.

FIG. 35 is a diagram illustrating an electrostatic induction effect in a case where a buffer is provided when the anode is short-circuited in FIG. 29;

[Explanation of symbols]

Reference Signs List 1 cathode region (n _E ) 2 gate region (p _B ) 3 anode region (p _E ) 4 anode short-circuit region (n ⁺ ) 5 n buffer layer 6 n base layer (n _B ) 7 IGBT p base layer (p _B) 8) n collector region (n _E ) of IGBT 9 gate region of IGBT 10 epitaxial growth layer 30 p anode region (p _E1 ) 31 having relatively large junction depth 31 p anode region (p _E2 ) having relatively small junction depth )

Claims (1)

(57) [Claims] 1. A semiconductor switching device having a buffer, comprising: a p-type anode region having a relatively low junction depth of a relatively low resistivity; and a p-type anode region having a low resistivity or a predetermined low resistivity. The shallowly formed anode short-circuit region and the anode short-circuit region are alternately arranged in the vertical direction. A semiconductor switching element having a buffer, comprising: an anode-emitter short-circuit structure in which a relatively deep p-anode region is periodically arranged.