JP2848681B2 - Exclusive control circuit of multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an exclusive control circuit in a multiprocessor system.

(Prior Art) Conventionally, a procedure for acquiring exclusion between processors and executing a process in a multiprocessor system is as follows.

A processor that intends to execute a process for requesting exclusion issues a request for acquiring exclusion.

After confirming that the request has been accepted, the processor that has performed the exclusion acquisition starts the process to be executed.

The case where the request is not accepted is as follows.

1) Exclusivity previously acquired by the user has not been released yet.

2) When another processor has already acquired exclusion.

3) A processor having a higher priority than itself issues an exclusive acquisition request.

When the above processing is completed, the processor releases the exclusion.

The release of exclusion here is when the process is completed,
That is, since the request for the destination device is issued after being output to the system bus, when the load on the system bus increases, the output of the request to the destination device is delayed, and the release of the exclusion is postponed. Become. Therefore, the situation as described in 1) occurs, and the next exclusion acquisition request is not accepted until the exclusion acquired by itself is released.

(Problems to be Solved by the Invention) As described above, in the conventional multiprocessor system, the release of the exclusion is performed when the processing is completed, that is, after the request for the partner device is output to the system bus. When the load on the system bus increases, the output of a request to the partner device is put on hold, and the release of exclusion is postponed. For this reason, in order for the processor to perform the exclusion process, it is necessary to wait for the exclusion acquired earlier to be released.

The present invention has been made in order to eliminate such a conventional disadvantage. If the previously acquired exclusion is acquired by the own processor, the next exclusion is performed without waiting for the exclusion to be released. It is an object of the present invention to provide an exclusive control circuit of a multiprocessor system which can perform the exclusive processing of the multiprocessor system by increasing the processing speed.

[Structure of the Invention] (Means for Solving the Problems) An exclusive control circuit of the present invention that achieves the above-mentioned conventional object is as follows:
In a multiprocessor system composed of a plurality of processors, when a processor executes memory access, interprocessor communication, input / output processing, and the like, one processor takes exclusive control of the processor to perform processing exclusively. An exclusion control unit, an exclusion acquisition request counter for counting the number of exclusion acquisition requests executed by the own processor while the own processor is acquiring exclusion, and the number of requests counted in the exclusion acquisition request counter overflows. An exclusive acquisition request prohibition unit for inhibiting acceptance of a new request issued by the own processor in the event that the request has been issued, and an exclusion release inhibition for inhibiting release of exclusion when one or more requests are counted in the exclusion acquisition request counter. Means.

(Operation) In the present invention, if the previously acquired exclusion is acquired by the own processor, the next exclusion process can be performed without waiting for the exclusion to be released.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an outline of a multiprocessor system to which the present invention is applied. In the figure, a plurality of processors 200, a memory 300 and a channel 400 are connected via a system bus 100, and data transfer between the devices is performed by the system bus 100.
Run through.

FIG. 2 is a block diagram showing the configuration of an exclusive control circuit according to one embodiment of the present invention.

The exclusive control circuit according to the present embodiment is incorporated in the processor 200 shown in FIG. 1, and includes a microprogram control unit 201, a decoder 203, a bus acquisition control unit 205, an exclusive acquisition flip-flop 208, and an exclusive acquisition Request counter 209
Is provided. Reference numerals 301 to 305 denote AND gates, and 110 denotes a signal line in the system bus 100. If the signal line 110 is active (true value of 0), it indicates that exclusive acquisition is being performed. 121,
122 and 123 are also signal lines in the system bus 100, respectively.
An exclusive acquisition request signal (0 true value) of each processor 200 is sent.

The microprogram control unit 201 controls a microprogram address and outputs a microinstruction 202. The decoder 203 decodes the micro instruction 202 output from the micro program control unit 201. Here, reference numeral 204 denotes an exclusive acquisition request signal (1 true value), which is inverted and output to the signal line 121. Reference numeral 206 denotes an exclusion release request signal (1 true value), which is sent to the bus acquisition control unit 205. Reference numeral 207 denotes an exclusion release signal (1 true value), which is output from the bus acquisition control unit 205. The bus acquisition control unit 205 controls acquisition of the system bus 100 and transfer of information to the system bus 100. The exclusion acquisition flip-flop 208 is set when the own processor is acquiring exclusion. The exclusive acquisition request counter 209 has an exclusive acquisition flip-flop 2
When the exclusive acquisition request signal 204 becomes active while 08 is set, the count is incremented.

210 is a signal (1 true value) that becomes active when the count of the exclusion acquisition request counter 209 is 1 or more, 211
Is a signal (1 true value) that becomes active when the count of the exclusive acquisition request counter 209 overflows.

In a multiprocessor system as shown in FIG. 1, when a certain processor 200 accesses the memory 300, performs input / output processing with the channel 400, and performs data transfer with another processor. In some cases, the user wants to use the other device exclusively. For this reason, control is exercised between the processors 200 to take exclusion.

Exclusive control will be described with reference to FIG. When the processor 200 acquires exclusion, its execution is realized by the microinstruction 202. First, a microinstruction 202 including a request for acquiring exclusion is output from the microprogram control unit 201. This is decoded by the decoder 203, and the exclusive acquisition request signal 204 and the signal line 121 on the system bus 100 become active.

At this time, when a processor having a higher priority than the own processor has issued an exclusion acquisition request (when one of the signal lines 122 and 123 is active), or when exclusion has already been acquired (when the signal line 110 is active). The setting of the exclusive acquisition flip-flop 208 is prohibited.

The output of exclusive acquisition flip-flop 208 is AND gate 302
And the microprogram control unit 201 outputs a microinstruction 202 including a request to acquire exclusion again if the output of the exclusion acquisition flip-flop 208 is not active. . Then, when the signal lines 110, 122, 123 become inactive, the exclusion acquisition flip-flop 208 is set, the signal line 110 becomes active, and the processor can acquire exclusion.

Also, the microprogram control unit 201 advances the processing of the microprogram by setting the exclusive acquisition flip-flop 208.

Next, the exclusion is released, which is also realized by the microinstruction 202. The microprogram control unit 201 outputs a microinstruction 202 including a request for releasing exclusion. This is decoded by the decoder 203, the exclusion release request signal 206 becomes active, and is sent to the bus acquisition control unit 205.

The bus acquisition control unit 205 controls acquisition of the system bus 100. After outputting an access to a device to be subjected to exclusion processing to the system bus 100, the exclusion release signal 207 is activated. At this time, the exclusive acquisition request counter 209
, The exclusive release signal 207 is input to the reset input of the exclusive acquisition flip-flop 208 via the AND gate 304, and resets the exclusive acquisition flip-flop 208. Thus, the processor releases the exclusion.

Since the release of the exclusion is performed after the request to the other party is output to the system bus 100, a wait occurs when the load on the system bus increases. On the other hand, irrespective of this, since the microprogram advances the processing in advance, there is a case where the next exclusive acquisition request is made.

 Hereinafter, the operation in such a case will be described.

Since the previously acquired exclusion has not yet been released, the exclusion acquisition flip-flop 208 is in the set state. Here, when the exclusion acquisition request signal 204 becomes active, the exclusion acquisition request counter 209 is counted up. If one or more requests are counted in the exclusion acquisition request counter 209, the signal 210 becomes active. Therefore, even if the exclusion release signal 207 becomes active to release the exclusion previously acquired in this state, Inhibited by signal 210. Therefore, the paper ejection acquisition flip-flop 208 is not reset, and the exclusive acquisition request counter 209 is counted down instead.

Thus, the processor 200 can perform the next exclusion process even in a state where the exclusion previously acquired by the own processor has not been released.

When the exclusive acquisition request counter 209 overflows, the signal 211 becomes active. Therefore,
By prohibiting the output of the exclusion acquisition flip-flop 208 by the signal 211 and sending it to the microprogram control unit 201, the processing of the microprogram is prevented from proceeding further.

[Effect of the Invention] As described above, according to the exclusive control circuit of the multiprocessor system of the present invention, if the previously acquired exclusion is acquired by the own processor, it is released. By allowing the next exclusion process to be performed without waiting, speeding up of the process is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a multiprocessor system to which the present invention is applied, and FIG. 2 is a block diagram showing the configuration of an exclusive control circuit according to an embodiment of the present invention. 100: System bus, 200: Processor, 201: Microprogram control unit, 202: Microinstruction, 203
... Decoder, 204... Exclusive acquisition request signal, 205... Bus acquisition control unit, 206... Exclusive release request signal, 207.

Claims (1)

(57) [Claims] In a multiprocessor system comprising a plurality of processors, when a processor executes memory access, interprocessor communication, input / output processing, etc., a single processor performs processing exclusively. Exclusion control means for taking an exclusion, an exclusion acquisition request counter for counting the number of exclusion acquisition requests executed by the own processor while the own processor is acquiring the exclusion, and An exclusion acquisition request prohibition unit for inhibiting acceptance of a new request issued by the own processor when the number of requests overflows, and canceling exclusion when one or more requests are counted in the exclusion acquisition request counter. And a exclusion release prohibition means for prohibition. Circuit.