JP2848171B2 - SCSI controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SCSI controller, and more particularly to data transfer in a system to which a small computer system interface (SCSI) for small and medium computer systems standardized by the American National Standards Institute (ANSI) is applied. For controlling the SCSI controller.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional SCSI controller of this kind.

The SCSI controller includes a SCSI bus interface circuit 4 for transmitting and receiving data to and from a small computer device such as a small computer and its peripheral devices via a SCSI side bus 12. , Receives and stores data from the small computer device in predetermined units in accordance with a first write signal SR.W, and sequentially reads out stored data in units of the predetermined unit in accordance with a first read signal SR.R And a first empty signal SR · E and a full signal S indicating an internal storage state and an operation state.
SC for outputting R / F and not-ready SR / NR signals
An SI-side FIFO register 3, a host bus interface circuit 1 for transmitting and receiving data and control signals to and from a host device via a host-side bus 11 and a control signal line,
SCSI side FIFO according to second write signal HR / W
The read data of the register 3 is received and stored via the internal data bus 13, and the stored data is sequentially read in accordance with the second read signal HR · R and supplied to the host device via the host bus interface circuit 1.
A second empty signal HR.E, a full signal HR.F, and a not-ready signal HR indicating an internal storage state and an operation state.
A host-side FIFO register 2 for outputting NR, and the number of data received from the small computer device are stored in accordance with an instruction from the host device, and are stored in the host-side FIFO register.
A transfer byte number register 7 for decrementing the data number each time data is supplied from the register 2 to the host device; a main control signal and a first empty signal SR
.E, full signal SR.F and not-ready signal SR.N
SCSI bus transfer control circuit 6 for controlling data write / read operation of SCSI side FIFO register 3 according to R
And the main control signal and the second empty signal HR
E, an internal transfer control circuit 5 for controlling the data write / read operation of the host side FIFO register 2 in accordance with the full signal HR.F and the not ready signal HR.F, a SCSI bus transfer control circuit 6 for generating the main control signal and A main sequence circuit 8 for controlling the operation of each unit including the internal transfer control circuit 5;
A SCSI control circuit 9 for controlling the operation of the small computer device under the control of the bus transfer control circuit 6 is provided.

Next, the operation of the SCSI controller will be described.

The host bus interface circuit 1 receives data and control signals from a host device via a host bus 11 and control signal lines, and supplies the data and control signals from each unit to the host bus 11.
And to a host device via a control signal line.

The main sequence circuit 8 includes a host bus
When a control signal is received from the interface circuit 1 and indicates a data transfer state, the internal transfer control circuit 5 and the SCSI bus transfer control circuit 6 are activated by a transfer start command.

When the SCSI bus transfer control circuit 6 is activated and receives a signal, it sends a request signal REQ to the SCSI control circuit 9.
When the SCSI control circuit 9 detects that the acknowledgment signal ACK has become active, the SCSI-side FIFO register 3 activates the write signal SR · W to transfer the data of the SCSI-side bus 12 to the SCSI bus. Writing via the interface circuit 4 The internal transfer control circuit 5 activates the read signal SR / R after confirming that the SCSI side FIFO register 3 is not in the empty state by the empty signal SR · E. The data of the SCSI-side FIFO register 3 is output onto the internal data bus 13, and the internal transfer control circuit 5 activates the write signal HR · W upon seeing the full signal HR · F, thereby The data is written into the FIFO register 2 on the host side. At this time, the internal control circuit 5 decrements the value of the transfer byte number register 7.

The host bus interface circuit 1 comprises:
By a read signal from the outside (host device),
The operation was to read data from the host-side FIFO register 2.

When the host computer does not receive the data of the number of data set in the transfer byte number register 7 and the small computer device stops the data transfer, the host device stops the data transfer. After confirming that the transfer has been performed, an instruction to stop the transfer command or an instruction to stop and disconnect the transfer command is issued to the SCSI controller.
Since there is a possibility that data may remain in the SI-side FIFO register 3, when issuing a stop instruction, it is necessary to wait a sufficiently long time after the data transfer is interrupted.

Regarding such a SCSI interface protocol, "ANSI X3.1" of the American National Standards Institute.
31-1986 Small Computer Sy
"Stem Interface" and "ANSI X3
T9.2 / 86-109 Revision 10g
Small Computer System Int
surface-2 ".

In a block type computer system, the SCSI controller transfers data in units of one block. At this time, if the number of data is set in the transfer byte number register 7 in units of one block to transfer a large amount of data, the transfer data number must be reset every time one block of data is transferred.

When the number of transfer bytes to be set is maximized, when the small computer device interrupts the data transfer for some reason, the host device must issue a transfer stop instruction to the SCSI controller. Must. This transfer stop instruction normally interrupts the transfer immediately and clears the contents of the host-side FIFO register 2, the SCSI-side FIFO register 3, and the transfer byte number register 7, so that the data remaining in the SCSI controller is lost. Is falling. Therefore, the data block must be transferred to the host device again, and the host device resets the transfer byte number register 7 and issues a transfer command.

In a character-type computer system, the number of data to be transferred may not be determined at the start of transfer. As the character type is represented by a magnetic tape, the number of transfer data at the time of writing is ECF (END O).
F FILE) is determined. Also in this case, it may not be possible to set the number of transfer data in the SCSI controller in advance.

Therefore, even if a device can set the number of data to be transferred in advance, if the transfer speed is to be increased, the maximum number of data that can be set is set in the transfer byte number register 7 and a transfer command is issued to transfer the data. The operation is started, and when the transfer is completed, it is confirmed that the data transfer from the small computer device has been completed.
The transfer operation of the I controller must be broken. At this time, a worst case occurs in which a break instruction for a transfer operation issued by the host device to the SCSI controller loses data remaining inside the SCSI controller depending on the timing of issuing the instruction.

In order to avoid such a situation, the number of data set in the transfer byte register 7 must be as small as possible (one block in the case of a block type), and data transfer must be performed for each set number of data. Must. In this method, the number of data must be set every time the data of the number of data is transferred. further,
If the host performs the DMA transfer, the DMA controller must also set and activate the number of transfer data. In this case, the occupation time of the host bus becomes longer, and the performance of the entire system is significantly reduced.
The situation is that the true performance of the controller and the DMA controller itself cannot be exhibited.

A specific example in which the transfer performance is reduced will be described below. When the transfer speed of the SCSI-side data bus 12 (8-bit bus) of this SCSI controller is 10 Mbytes / sec and the transfer speed of the DMA controller (8-bit bus) is also 10 Mbytes / sec, the transfer of the first data starts. The minimum time required for the transfer (initial setting is assumed to be completed for both the SCSI controller and the DMA controller) is as follows: If the minimum cycle of I / O access of the host device is 100 ns, the transfer byte number register 7 of the SCSI controller It takes 90 ns to set the transfer byte number register and the register for determining the transfer direction of the DMA controller in a total of 90 ns.
At 0 ns, the initiator selects a target SCSI controller according to the SCSI protocol.
At this time, the SCSI controller selected as the target generates an interrupt due to the selection, and the interrupt causes a command to process the message-out phase and the command-out phase to the target SCSI controller. Issue.
The minimum time in the SCSI protocol so far is bus-free delay (800 ns) + arbitration delay (2.4 μs) + bus set delay (0 ns: m)
ax 1.8 μs) + bus clear delay (0 ns: ma)
x800ns) + Bus settle delay (400ns) +
Deskew delay × 2 (90 ns) Deskew delay × 2 (90 ns), which is 3780 ns.

The time for issuing a command is 100n.
s, message (1 byte) and command (6 bytes)
The minimum time required to transfer is (assertion time +
Negation time) × 7, which is 1260 ns.

If it is attempted to transfer 1024 bytes in the subsequent data phase, (fast assertion time + fast negation time) × 1024, ie, 10
2.4 μs is required even at the minimum, and one sector 1024
Read / sector 20 bytes with byte disk drive
When performing a write operation, 102.4 μs × 20, that is, 2.048 ms is required. As described above, if it is assumed that no problem occurs from the arbitration of the SCSI bus, the minimum time required is 900 (ns) +1260 (ns) +3780 (ns)
+2.048 (ms) = 16.088 (ms). At this time, if data is transferred one sector at a time, and the SCSI bus is released every time one sector is transferred, then (900 (ns) +1260 (ns) +3780 (n
s)) × 20 + 2.048 (ms) = 77.76 (m
s) +2.048 (ms) = 79.808 (ms). When transferring data continuously without releasing the SCSI bus, 900 (ns) × 20 + 1260 (ns) +3780
(Ns) +2.048 (ms) = 25.088 (ms) Since the overhead time of the DMA controller is not taken into account in the above time, it is actually larger than the above value.

From the above calculation, when the SCSI bus is released for each sector, it takes about five times as long as the transfer time when no problem occurs, and even when the SCSI bus is not released, it is 64% or more. This time is further required, which causes a problem that the original performance of the SCSI controller and the DMA controller cannot be exhibited.

[0020]

In the conventional SCSI controller, when a transfer stop command is issued from the host device, the data transfer is immediately interrupted, and the host-side FIFO register 2, SCSI-side FIFO register 3, and transfer buffer are transferred. Since the contents of the number register 7 are cleared, the host-side FIFO register 2 and SC
There is a problem that the data remaining in the SI-side FIFO register 3 is lost, and it is necessary to re-transfer the data of that part again. To avoid this, the number of data set in the transfer byte number register 7 is reduced. If it is minimized, the number of data must be set for each data transfer, and the transfer speed is reduced.

An object of the present invention is to provide a SCSI controller that can transfer data remaining in a FIFO register without losing the data and can increase the transfer speed.

[0022]

A SCSI controller according to the present invention receives and stores data from a small computer device in predetermined units according to a first write signal, and stores the stored data in accordance with the first read signal. And a SCSI-side FIFO register for outputting a first empty signal, a full signal, and a not-ready signal indicating an internal storage state and an operation state, and the SCSI-side FIFO register according to a second write signal.
Receives and stores the read data of the register, sequentially supplies the stored data to a host device in accordance with a second read signal, and outputs a second empty signal, a full signal, and a not-ready signal indicating an internal storage state and an operation state. The host-side FIFO register for outputting and the number of data received from the small computer device are stored in accordance with an instruction of the host device, and the host-side FIFO register is stored.
A transfer data number register for decrementing the number of data each time data is supplied from the FO register to the host device; and the SC according to a main control signal and the first empty signal, full signal and not ready signal.
A first transfer control circuit for controlling a data write / read operation of the SI side FIFO register, and a data write / read operation of the host side FIFO register in accordance with the main control signal and the second empty signal, full signal and not ready signal And a main control circuit for generating the main control signal and controlling the operation of each unit including the first and second transfer control circuits.
In the controller, a mode register that outputs a mode control signal that becomes an active level by a transfer stop signal from the host device when data corresponding to the number of data stored in the transfer data number register is not supplied to the host device, A logic gate for taking a logical sum of the mode control signal and a first full signal from the SCSI-side FIFO register and using the logical sum as a first full signal to the first transfer control circuit; When the output signal of the logic gate becomes an active level, the SCSI by the first transfer control circuit
In addition to stopping writing data to the FIFO register on the side, reading data from the FIFO register on the SCSI side, writing data to the FIFO register on the host side, and reading data from the FIFO register on the host side are enabled. Have.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment is similar to the conventional SCS shown in FIG.
The difference from the I controller is that when the data of the number of data stored in the transfer byte number register 7 is not supplied to the host device, the mode control signal MC which becomes active level by the transfer stop signal from the host device is output. A logical register G1 that takes the logical sum of the mode control signal MC and the first full signal SR · F from the SCSI-side FIFO register 3 to generate a first full signal to the SCSI bus transfer control circuit 6; When the output signal of the logic gate G1 becomes active level by the transfer stop signal, the writing of data to the SCSI side FIFO register 3 by the SCSI bus transfer control circuit 6 is stopped, and the SCSI side FIFO
Read data from FO register 3, host-side FIFO
Write data to O-register 2, this host-side FIF
The point is that data can be read from the O register 2.

Next, the operation and effect of this embodiment will be described.

If the small computer device has stopped transferring data while the data of the number set in the transfer byte number register 7 has not been received, the host device determines that the data transfer has been stopped. After the recognition, the SCSI controller issues a command to stop the transfer command or a command to stop and disconnect the transfer. At this time, the SCSI side FIFO register 3,
Since data may possibly remain in the host-side FIFO register 2, the output signal (MC) of the mode register 10
Is set to “1”. Since the mode control signal MC output from the mode register 10 is an input to the OR-type logic gate G1, if the mode control signal MC is "1", SC
The SI bus transfer control circuit 6 is in the same state as when the full signal SR-F from the SCSI side FIFO register 3 is output.

When the SCSI bus transfer control circuit 6 detects that the SCSI side FIFO register 3 is full, the operation of the SCSI control circuit 9 and the operation of the SCSI bus interface circuit 4 are temporarily stopped. That is, SCS
The I controller stops activating the request signal REQ until the full signal to the SCSI bus transfer control circuit 6 returns to inactive.

At this time, the internal transfer control circuit 5
Reads data from the FIFO register 3 of the host
Write to IFO register 2. However, the SCSI side FIF
If the empty signal SR · E of the O register 3 is active or the not-ready signal SR · NR is active, the reading operation cannot be performed, so that the internal transfer is temporarily stopped, and the full signal HR · F
If the not-ready signal HR / NR is active, the write operation cannot be performed, and the internal transfer is temporarily stopped.

In other cases, reading from the FIFO register 3 on the SCSI side, writing into the FIFO register 2 on the host side, and reading from the FIFO register 2 on the host side can be performed. Until the device becomes empty
Since the transfer operation from the O-register 3 to the host-side FIFO register 2 is continued, even if the transfer of data from the SCSI-side bus 12 is stopped, the clear state where the data remains in the SCSI-side FIFO register 3 will not occur. Absent. The data written in the host-side FIFO register 2 is picked up by the DMA controller of the host device by DMA transfer.

Therefore, when the output signal (MC) of the mode register 10 is set to "1", the SCSI bus transfer is stopped, and after the data in the SCSI controller is taken, the transfer command is broken and disconnected. The data transfer from the small computer device can be safely stopped without data loss in the controller.

When the mode register 10 is provided, the transfer speed as the transfer performance until the data transfer is interrupted is the same as the ideal transfer operation assuming that the above-mentioned problem does not occur, and it is 1024 bytes per sector. Drive 20
900 (ns) when trying to transfer sectors
+1260 (ns) +3780 (ns) +2.048
(Ms), that is, 16.88 ms. Also, S
To transfer data continuously without releasing the CSI bus, 900 (ns) × 20 + 1260 (ns) +378
0 (ns) +2.048 (ms), that is, 25.08
Since this is 8 ms, the time can be reduced by 64% or more.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In this embodiment, an OR type second logic gate G2 is further provided in the first embodiment, and the mode register 10
The logical sum of the mode control signal MC from the main control circuit 8 and the transfer temporary stop signal ITST from the main sequence circuit 8 is calculated and then input to one input terminal of the (first) logic gate G1.

In this embodiment, the transfer temporary stop signal ITST
Is "1", the operation is the same as when the mode control signal MC is "1". Basic operations and effects are the same as those of the first embodiment.

[0036]

As described above, according to the present invention, a mode register for setting a mode control signal to an active level in accordance with an instruction from a host device is provided, and at least one of the mode control signal and the transfer temporary stop signal from the main sequence circuit is provided. The logical sum of the control signal and the full signal from the SCSI-side FIFO register is taken to be a full signal to the first transfer control circuit, so that the data is transferred by the number of data set in the transfer data number register. If not, temporarily stop the reception on the SCSI bus side,
Read FIFO register on SCSI side, FIFO on host side
Since the writing and reading of the O register can be continued, the data remaining in the SCSI controller at the time of stopping the data transfer can be read from the host-side FIFO, and the data can be read from the small computer without losing the data. There is an effect that the data transfer on the device side can be interrupted and disconnected, and the data transfer speed can be increased because the data need not be divided or retransmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional SCSI controller.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host bus interface circuit 2 Host side FIFO register 3 SCSI side FIFO register 4 SCSI bus interface circuit 5 Internal transfer control circuit 6 SCSI bus transfer control circuit 7 Transfer byte number register 8, 8a Main sequence circuit 9 SCSI control circuit 10 Mode Register G1, G2 Logic gate

Claims (1)

(57) [Claims] 1. A method for receiving and storing data from a small computer device in predetermined units in accordance with a first write signal, sequentially reading stored data in units of the predetermined unit in accordance with a first read signal, and storing the data in an internal storage. A SCSI-side FIFO register for outputting a first empty signal, a full signal, and a not-ready signal indicating a state and an operation state; and the SCSI-side FIFO register according to a second write signal.
The read data of the O register is received and stored, and the stored data is sequentially supplied to the read host device in accordance with a second read signal. In addition, a second empty signal, a full signal, and a not ready signal indicating an internal storage state and an operation state are provided. And the number of data received from the small computer device is stored in accordance with an instruction from the host device.
A transfer data number register for decrementing the number of data each time data is supplied from the IFO register to the host device; and a transfer control register for controlling the main control signal and the first empty signal, the full signal and the not ready signal.
A first transfer control circuit for controlling a data write / read operation of a CSI-side FIFO register, and a data write / read operation of the host-side FIFO register in accordance with the main control signal and a second empty signal, a full signal and a not-ready signal And a main control circuit that generates the main control signal and controls the operation of each unit including the first and second transfer control circuits.
A mode register for outputting a mode control signal which becomes an active level in response to a transfer stop signal from the host device when the data corresponding to the number of data stored in the transfer data number register is not supplied to the host device; A logic gate for taking a logical sum of the mode control signal and a first full signal from the SCSI-side FIFO register and using the logical sum as a first full signal to the first transfer control circuit; When the output signal of the logic gate becomes an active level, the SCS by the first transfer control circuit is changed.
Writing of data to the I-side FIFO register is stopped, and data can be read from the SCSI-side FIFO register, data can be written to the host-side FIFO register, and data can be read from the host-side FIFO register. A SCSI controller, characterized in that: