JP2842351B2 - Head degaussing method and circuit for magnetic disk drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk drive, and more particularly to a method for demagnetizing a magnetic head and a circuit therefor.

[0002]

2. Description of the Related Art In a conventional magnetic disk drive, a data signal sent from a host to a magnetic disk controller is code-converted, written to a disk via a magnetic head, and a code read from the magnetic disk by a magnetic head is magnetically converted. The data is decoded by the disk control device and transmitted to the upper side as a data signal.

In the prior art, when a read operation is performed immediately after the head is magnetized, specific write data causes
Since the direction of the write current is deviated in one direction and the head is magnetized, noise may be included in the read data and normal reading may not be performed. In order to avoid this, known techniques for providing a magnetic disk device with a head degaussing circuit are described in JP-A-63-244403 and JP-A-1-15302. The former is a magnetic head degaussing circuit having a detecting means for taking out the magnetic disk from the apparatus, a current switching means for alternately generating an inversion signal for a certain period activated by the magnetic disk, and a means for attenuating the inversion AC signal.

In the latter, a magnetic head degaussing circuit has been proposed which applies a current in which the direction is inverted at a predetermined cycle and the level gradually decreases in a conduction / cutoff erasing current.

[0005]

However, all of the above-described magnetic head degaussing circuits are processed in an analog manner and are not always stable in terms of aging, but are preferably processed in a logical manner. In particular, depending on the types and characteristics of the magnetic head and the magnetic disk medium, it is difficult to cope with a single magnetic head degaussing circuit.

SUMMARY OF THE INVENTION An object of the present invention is to digitally process a magnetic head capable of selecting a degaussing signal having an optimum period corresponding to different types of magnetic heads and magnetic disk media. Accordingly, it is an object of the present invention to provide a magnetic head degaussing method and a circuit for normalizing a read operation immediately after a write operation in which a head is magnetized.

[0007]

SUMMARY OF THE INVENTION A head degaussing method for a magnetic disk drive according to the present invention comprises a plurality of degauss signals having different periods which are individually transmitted from a high-order side which is a high-order circuit incorporated in the magnetic disk drive. A degaussing signal selecting step of continuously outputting at least one of the degaussing signals determined by a middle to higher-side selection signal, and a first demagnetizing signal corresponding to the higher-level device after an input data writing period from the higher-level
Setting a first degaussing period by counting the lower-side reference clock based on the count value of the above, and after the first degaussing period, further setting a lower side by a second count value corresponding to the upper-side device. Counting a second degaussing period by counting the reference clock of the second stage, and after the input data writing period from the upper side, the lower side reference clock is demagnetized by the delay value of the upper side to demagnetize the input data writing period. A write signal delay step of counting and setting an output write period continuously during the write period, and a step of adding the degauss signal to the write data signal only during the degauss period generated on the lower side and outputting the write data signal. Have.

Further, the head degaussing circuit of the magnetic disk drive of the present invention comprises a high-order degaussing signal having a different cycle and individually transmitted from a high-order side which is a high-order circuit built in the magnetic disk drive. A degaussing signal selecting means for continuously outputting at least one of the degaussing signals determined by the selection signal, and a lower count value obtained by a first count value corresponding to the upper device after an input data writing period from the upper device. Means for setting a first degaussing period by counting the reference clock on the side, and counting the lower reference clock after the first degaussing period by a second count value corresponding to the upper device. Means for counting the second degaussing period
After the input data writing period from the upper side, the lower reference clock is counted by the delay value of the upper side so that the degaussing period is counted continuously to the input data writing period, and the output writing period is set. Signal delay means; and means for adding the degauss signal to the write data signal only during the degaussing period generated on the lower side and outputting the write data signal.

Further, the degaussing signal selecting means converts one additional data 0 signal determined by the additional data 0 selection signal transmitted from the upper side from a plurality of additional data 0 signals transmitted as a degaussing signal from the upper side. Select and select additional data 0
An additional data 0 selection circuit that outputs a signal, and a plurality of additional data 1 selection signals that are respectively determined by a plurality of additional data 1 selection signals that are sent from the upper side to a plurality of additional data 1 signals that are sent as a demagnetization signal from the upper side. It has a plurality of additional data 1 selection circuits for selecting a data 1 signal and outputting as a plurality of selection additional data 1 signals.

[0010] The means for setting the first degaussing period includes: a reference clock transmitted from the lower side; and an additional data transmitted from the upper side after the input write gate signal from the upper side becomes inactive. It has an additional data 0 counting circuit that outputs an additional data 0 permission signal for a time indicated by the 0 count value signal.

Further, the means for counting the second degaussing period includes: outputting the reference clock transmitted from the lower side after the additional data 0 permission signal of the additional data 0 counting circuit becomes inactive; After the additional data 1 enable signal, which is the output signal of the preceding additional data 1 counting circuit, becomes inactive, the time indicated by the corresponding plurality of additional data 1 count signals transmitted from the upper side is It has a plurality of additional data 1 counting circuits each outputting a corresponding additional data 1 permission signal.

Further, the write signal delay means is transmitted from the lower side while the input write gate signal from the upper side is active and after the input write gate signal from the upper side becomes inactive. A write signal delay circuit for activating an output write gate signal for a time indicated by a write gate delay value signal transmitted from the upper side of the reference clock.

The output means outputs the selected additional data 0 signal generated on the lower side as an additional write data signal only while the additional data 0 enable signal is output from the additional data 0 counting circuit. An additional data selection circuit to be output, and one of an input write data signal, which is write data transmitted from a higher-order side, and the additional write data, which is an output signal from the additional-data selection circuit, from the higher-order side. And a write data selection circuit for selecting an input write gate signal and outputting an output write data signal.

Further, the additional data selection circuit outputs the additional data 0 signal to the additional write data signal when the additional data 0 permission signal of the additional data 0 counting circuit is active, and When the plurality of additional data 1 permission signals of one counting circuit are active, the additional data selection circuit outputs the corresponding selected additional data 1 signal to the additional write data signal.

Still further, the write gate delay value signal is:
It may have a value equivalent to the first count value or the second count value, or a value equivalent to the sum of the first count value and the second count value.

According to the present invention, a demagnetization signal having an optimum cycle is selected corresponding to different types of magnetic heads and magnetic disk media, and the magnetic head is demagnetized by the degauss signal after the completion of the input data writing, so that the head is demagnetized. A method and circuit for demagnetizing a magnetic head that makes the abnormality of the read operation immediately after writing normal can be obtained.

The write data selection circuit outputs an input write data signal while the input write gate signal is active. When the input write gate signal becomes inactive, the write data selection circuit outputs a time indicated by the first count signal. During this period, a degaussing signal selected by the selection signal of the degaussing signal 00 signal or the degaussing signal 01 signal is output. Next, during the time indicated by the second count value signal, the demagnetization signal of another cycle selected by the selection signal from the demagnetization signal 10 or the demagnetization signal 11 is output.

The write signal delay circuit activates the output write gate signal while the input write gate signal is active, and when the input write gate signal becomes inactive, the time is extended by the write gate delay value signal. After the demagnetization signal is sent, the output write gate signal is made inactive.

[0019]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The additional data 0 selection circuit 3 outputs an additional data 00 signal f and an additional data 01 signal g, which are two demagnetization signals having different periods, by switching with the additional data 0 selection signal h. The additional data 1 selection circuit 4 has 2
An additional data 10 signal i and an additional data 11 signal j, which are two demagnetization signals, are switched and output by an additional data 1 selection signal k. Additional data 0 selection circuit 3 and additional data 1
FIG. 2 shows a timing chart of the input / output signals of the selection circuit 4.

The additional data 0 counting circuit 5 has an input write gate signal d for defining the write time of the input write data a, an additional data 0 count value signal 1 indicating the demagnetization period by the number of reference clocks, and a reference clock signal. n is connected to an upper side (not shown). The additional data 1 counting circuit 6 is connected to the upper side (not shown) of the additional data 1 count value signal m and the reference clock signal n which are different from the above, and the additional data 0 permission signal output by the additional data 0 counting circuit 5 p and an additional data 0 end signal q are also connected.

The additional data selection circuit 2 has a selection additional data 0 signal e output from the additional data 0 selection circuit 3 and a selection additional data 1 signal o output from the additional data 1 selection circuit 4.
Are connected as input signals, and the additional data 0 permission signal p
And the additional data 1 permission signal r are connected as gates.

The write signal delay circuit 7 includes an input write gate signal d, a reference clock signal n, and a write gate delay value signal u indicating the transmission period of the degaussing signal by the number of reference clocks. , And the output write gate signal t is connected to the write data selection circuit 1 as an output.

The write data selection circuit 1 receives the additional write data signal c of the write data selection circuit 2, the input write data a,
The input write gate signal d is connected, and the output write data signal b is connected to the lower side (not shown).

FIG. 5 is a block diagram of the additional data 0 counting circuit 5 of FIG. In the OR circuit 51, the input write gate signal d is connected to an external circuit, and the additional data 0 permission signal p is connected to the flip-flop circuit 54. The counting circuit 52 is connected to an external circuit by the input write gate signal d, the additional data 0 count value signal 1 and the reference clock signal n.

The AND circuit 53 is connected to the OR circuit 51 by a logical sum signal a5, and is counted by a counting end signal c5.
Connected to

The flip-flop circuit 54 outputs a logical product signal b
5 is connected to the AND circuit 53, connected to the external circuit by the reference clock signal n, and connected to the external circuit by the additional data 0 permission signal p.

The AND circuit 55 outputs an additional data 0 permission signal p.
Is connected to the flip-flop circuit 54, the counting end signal c5 is connected to the counting circuit 52, and the additional data 0 end signal q is connected to an external circuit.

FIG. 6 is a timing chart of the additional data 0 counting circuit 5.

Next, the configuration of FIG. 7 will be described.

The logic circuit 61 is connected to the flip-flop circuit 64 by an additional data 1 permission signal r, and is connected to an external circuit by an additional data 0 end signal q and an additional data 0 permission signal p. The counting circuit 62 is connected to an external circuit with the additional data 0 permission signal p, the additional data 1 count value signal m, and the reference clock signal n.

The AND circuit 63 is connected to the logic circuit 61 by a logical sum signal a6, and is connected to the counting circuit 62 by a count end signal c6.

The flip-flop circuit 64 outputs a logical product signal b
At 6, it is connected to the AND circuit 63, connected to an external circuit by the reference clock signal n, and connected to the external circuit by the additional data 1 permission signal r.

FIG. 8 is a timing chart of the additional data 1 counting circuit 6.

Next, the configuration of FIG. 9 will be described.

The OR circuit 71 outputs the delayed write gate signal s7
Is connected to a flip-flop circuit 74, is connected to an external circuit by an input write gate signal d, and is connected to an output write gate signal t.
To connect to the external circuit.

The counting circuit 72 is connected to an external circuit by an input write gate signal d, a write gate delay value signal u, and a reference clock signal n.

The AND circuit 73 is connected to the OR circuit 71 by the output write gate signal t, and is connected to the counting circuit 72 by the count end signal c7.

The flip-flop circuit 74 outputs a logical product signal b
7 is connected to the AND circuit 73, and is connected to an external circuit by the reference clock signal n.

FIG. 10 is a timing chart of the write signal delay circuit 7.

Next, referring to FIGS. 1, 2, 3 and 4,
The operation will be described.

The additional data 0 selection circuit 3 outputs one of the additional data 00 signal f and the additional data 01 signal g as the selected additional data 0 signal e with the value indicated by the additional data 0 selection signal h. The upper half of FIG. 2 outputs the additional data 00 signal f as the selected additional data 0 signal e when the additional data 0 signal h is “0”, and outputs the additional data 01 when the additional data 0 selection signal h is “1”. A state where a signal g is output as a selection additional data 0 signal e is shown.

The additional data 1 selection circuit 4 outputs one of the additional data 10 signal i and the additional data 11 to the selected additional data 1 signal o with the value indicated by the additional data 1 selection signal k. In the lower half of FIG. 2, when the additional data 1 selection signal k is "0", the additional data 10 signal i is selected.
The additional data 1 signal j is output when the additional data 1 selection signal k is "1".
Is output.

The write signal delay circuit 7 activates the output write gate signal t when the input write gate signal d becomes active, and the write gate delay value signal u when the input write gate signal d becomes inactive. After counting the value indicated by (3 in this embodiment), the output write gate signal t is made inactive. That is, the falling of the input write gate signal d is extended and output as the output write gate signal t.

When the input write gate signal d becomes active, the additional data 0 counting circuit 5 activates the additional data 0 enable signal p in synchronization with the reference clock signal n, and the input write gate signal d becomes inactive. Then, after counting the value indicated by the additional data 0 count value signal 1 ("2" in this embodiment), the additional data 0 permission signal p is made inactive, and a pulse is output as the additional data 0 end signal q.

That is, the falling edge of the input write gate signal d is extended and output as an additional data 0 permission signal p, and a pulse is output as an additional data 0 end signal q to indicate the end of counting.

When both the additional data 0 permission signal p and the additional data 0 permission signal q become "1", the additional data 1 counting circuit 6 activates the additional data 1 permission signal r in synchronization with the reference clock signal n. After counting the value indicated by the additional data 1 count value signal m (“4” in this embodiment), the additional data 1 permission signal r is made inactive.

The write gate delay value signal u is the additional data 0 count value signal 1 or the additional data 1 count value signal m.
Or the same value as the sum of the two count values.

When the additional data 0 permission signal p is active, the additional data selection circuit 2 selects the additional data 0 signal e.
Is output to the additional write data signal c, and when the additional data 1 permission signal r is active, the selected additional data 1 signal o is output to the additional write data signal c.

Write data selecting circuit 1 outputs input write gate signal a to output write gate signal b while input write gate signal d is active, and writes data select circuit 1 while input write gate signal d is inactive. The additional write data signal c is output as the output write data signal b.

That is, while the input write gate signal d is active, the input write data signal a is output as the output write data signal b, and when the input write gate signal d becomes inactive, the additional data 0 count value signal is output. The selected additional data 0 signal e is output to the output write data signal b during the time indicated by l, and the selective additional data 1 signal o is output to the output write data signal b during the time indicated by the additional data 1 count value signal m. I do.

That is, after the input write data signal a is written, the output write gate signal t is extended, and the output write data signal b is transmitted with a 50% duty data to demagnetize the head.

[0053]

According to the present invention, it is possible to select a degaussing signal having an optimal period corresponding to different types of magnetic heads and magnetic disk media, and it is digitally processed so that it is stabilized for a long time. By demagnetizing the magnetic head after the end of writing, there is an effect that a magnetic head degaussing method and a circuit for demagnetizing the head immediately after the writing operation in which the head is magnetized can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 shows an additional data 0 selection circuit and additional data 1 shown in FIG.
FIG. 4 is a timing chart illustrating the operation of the selection circuit.

FIG. 3 is a timing chart showing an operation of the write signal delay circuit of FIG. 1;

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 5 is a block diagram showing an embodiment of an additional data 0 counting circuit 5 of FIG. 1;

FIG. 6 is a timing chart showing the operation of FIG. 5;

FIG. 7 is a block diagram showing an embodiment of the additional data 1 counting circuit 6 of FIG. 1;

FIG. 8 is a timing chart showing the operation of FIG. 7;

FIG. 9 is a block diagram showing an embodiment of a write signal delay circuit 7 of FIG. 1;

FIG. 10 is a timing chart showing the operation of FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write data selection circuit 2 Additional data selection circuit 3 Additional data 0 selection circuit 4 Additional data 1 selection circuit 5 Additional data 0 counting circuit 6 Additional data 1 counting circuit 7 Write signal delay circuit 51, 61, 71 OR circuit 52 , 62, 72 Counting circuit 53, 55, 63, 73 AND circuit 54, 64, 74 Flip-flop circuit

Claims (10)

(57) [Claims] 1. A head degaussing method for a magnetic disk drive, comprising: a plurality of degaussing signals having different periods individually transmitted from a high-order side which is a high-order circuit built in the magnetic disk drive; A degaussing signal selecting step of continuously outputting at least one of the degaussing signals determined by the selection signal; and a lower count value based on a first count value corresponding to the upper-level device after an input data write period from the higher-level device. Setting a first degaussing period by counting the reference clocks of the following, and after the first degaussing period, further counting the lower reference clocks by a second count value corresponding to the upper device. Counting the second degaussing period by using the input data writing period from the upper side, and setting the lower reference clock to the degaussing period by the delay value of the upper side. A write signal delay step of counting and setting an output write period continuously during the write period, and a step of adding the degauss signal to the write data signal only during the degauss period generated on the lower side and outputting the write data signal. Degaussing method for a magnetic disk drive. 2. A head degaussing circuit for a magnetic disk drive, comprising: a plurality of degaussing signals having different periods individually transmitted from a high-order side which is a high-order circuit built in the magnetic disk unit; A degaussing signal selecting means for continuously outputting at least one of the degaussing signals determined by the selection signal; and a first count value corresponding to the upper device after the input data writing period from the upper device. Means for setting a first degaussing period by counting reference clocks of the following, and after the first degaussing period, further counting the lower reference clock by a second count value corresponding to the upper device. Means for counting the second degaussing period by means of: and after the input data writing period from the upper side, linking the degaussing period to the input data writing period by the lower reference clock by the delay value of the upper side. A magnetic disk drive having write signal delay means for counting and counting and setting an output write period, and means for adding the degauss signal to the write data signal only during the degaussing period generated on the lower side and outputting the write data signal Head degaussing circuit. 3. The demagnetizing signal selecting means converts one additional data 0 signal determined by an additional data 0 selection signal transmitted from a higher order from a plurality of additional data 0 signals transmitted as a demagnetizing signal from a higher order side. An additional data 0 selection circuit that selects and outputs the selected additional data 0 signal, and a plurality of additional data 1 selection signals transmitted from the upper side to a plurality of additional data 1 selection signals transmitted from the upper side as a plurality of additional data 1 selection signals correspond to each other. 3. The head degaussing circuit according to claim 2, further comprising a plurality of additional data 1 selection circuits for selecting one of the additional data 1 signals and outputting the selected additional data 1 signals. And means for setting the first degaussing period, wherein the reference clock transmitted from the lower side is added to the additional data transmitted from the upper side after the input write gate signal from the upper side becomes inactive. 3. The head degaussing circuit for a magnetic disk drive according to claim 2, further comprising an additional data 0 counting circuit that outputs an additional data 0 enable signal for a time indicated by the 0 count value signal. 5. The means for counting the second degaussing period comprises: outputting the reference clock transmitted from the lower side after the additional data 0 permission signal of the additional data 0 counting circuit becomes inactive; and After the additional data 1 enable signal, which is the output signal of the preceding additional data 1 counting circuit, becomes inactive, the time indicated by the corresponding plurality of additional data 1 count signals transmitted from the upper side is 3. The head degaussing circuit according to claim 2, further comprising a plurality of additional data 1 counting circuits each outputting a corresponding additional data 1 permission signal. 6. The write signal delay means is transmitted from the lower side while the input write gate signal from the upper side is active and after the input write gate signal from the upper side becomes inactive. 3. The magnetic disk drive head according to claim 2, further comprising a write signal delay circuit that activates an output write gate signal for a time indicated by a write gate delay value signal transmitted from the upper side of the reference clock. Degaussing circuit. 7. The additional data 0 signal generated on the lower side as an additional write data signal only while the enable signal of the additional data 0 is being output from the additional data 0 counting circuit. An additional data selection circuit to be output, and one of an input write data signal which is write data transmitted from the upper side and the additional write data which is an output signal from the additional data selection circuit, 3. A head degaussing circuit for a magnetic disk drive according to claim 2, further comprising: a write data selection circuit for selecting with an input write gate signal and outputting the output write data signal. 8. The additional data selection circuit outputs the additional data 0 signal to the additional write data signal when the additional data 0 enable signal of the additional data 0 counting circuit is active. 8. The magnetic disk drive according to claim 7, further comprising an additional data selection circuit for outputting the selected additional data 1 signal corresponding to the additional write data signal when the plurality of additional data 1 permission signals of one counting circuit are active. Head degaussing circuit. 9. The head degaussing circuit according to claim 6 , wherein the write gate delay value signal has a value equivalent to the first count value or the second count value. 10. The head degaussing circuit according to claim 6 , wherein the write gate delay value signal has a value equivalent to a sum of the first count value and the second count value.