JP2842234B2 - Lead pin manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead pin used for a semiconductor device package used for electric or electronic products and the like, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in the field of manufacturing electronic products,
A PGA (Pin Grid Array) package is widely used as a semiconductor device package used for a product requiring high reliability and high functionality.

FIG. 4 is a view for explaining the structure of a PGA package. As shown in FIG.
5. The structure of the PGA package 12 assembled by laminating the mount layer 16 and the back surface layer 17 has a lead pin 11 for inputting and outputting data and signals required by the semiconductor integrated circuit on the lower surface of the package. Are arranged in multiple rows. If this structure is used, QFP (Quad Flat P
The package itself can be made smaller compared to a surface mount package in which leads are arranged in a row on the side, such as an ackage). Therefore, when a semiconductor integrated circuit having a large size of 15 mm square or more and having a large number of electrodes exceeding 1000 is packaged, the use of a PGA package enables a high-density mounting of a semiconductor device.

However, when a structure in which a semiconductor integrated circuit is mounted below the PGA package is employed, the structure having the multi-row arrangement cannot necessarily be employed.

For this reason, the lead pins must be arranged on the outer surface of the semiconductor integrated circuit, and the advantage of mounting the semiconductor device at a high density cannot be exhibited. On the other hand, as shown in FIG. 4, when the semiconductor integrated circuit is mounted on the upper side, another wiring layer is further provided under the mount layer to reduce the number of wiring layers to two.
With a structure having more than one layer, it is possible to arrange lead pins directly below the package surface. However, the number of wiring layers is increased and contact failure between layers is likely to occur (particularly, a ceramic PGA package). ), The production yield of the PGA package is remarkably reduced, and the package itself is increased, thereby lowering the mounting density of the semiconductor device.

In order to avoid the above-mentioned disadvantages, the wiring layer is generally provided with a single layer and a mount layer is provided. However, since the mount area is required to be flat, it is impossible to perform wiring. The lead pins cannot be arranged in multiple rows on the surface directly below the semiconductor integrated circuit, but are arranged on the outer surface of the semiconductor integrated circuit. Therefore, in large size,
When a semiconductor integrated circuit having a large number of electrodes is formed into a PGA package, in addition to a large mounting area, a considerable area is divided by lead pins arranged on the outer surface of the semiconductor integrated circuit, and the package itself becomes large. Therefore, the mounting density of the semiconductor integrated circuit may be lower than that of a mounting package such as a QFP.

As a countermeasure for improving the mounting density of the PGA package, as shown in Japanese Patent Laid-Open No. 3-198367, two types of bumps having the same structure are used as compared with the conventional structure in which one chip is packaged. One PGA package by facing the pattern surface of the IC chip with bumps, sandwiching the lead wires between the bump pads of both chips, bonding the lead wires in a sandwich state, and sealing both chips into a package On the other hand, there has been proposed a semiconductor integrated circuit device having a structure in which two semiconductor integrated circuits are mounted.

However, in the proposed device, the IC
When the number of electrodes of the chip increases, the number of electrodes and lead pins of the PGA package also increases in proportion to the increase, so that the PGA package itself becomes large. Therefore, in the case of an IC having an extremely large number of electrodes, there is a problem that the mounting density is reduced.

[0009]

SUMMARY OF THE INVENTION General-purpose PGA
The package lead pins cannot be arranged in multiple rows on the lower surface of the semiconductor integrated circuit, but are arranged on the outer surface thereof, so that a lot of space is allocated to the arrangement of the lead pins and the package becomes larger than necessary. was there.

An object of the present invention is to overcome the problems of the prior art and to establish a method for manufacturing lead pins which is effective for reducing the size of a PGA package and improving the mounting density of a semiconductor integrated circuit. It was done.

The present invention, as shown in FIGS.
The gist is the following (1) and (2) lead pin manufacturing methods.

(1) A method of manufacturing lead pins 11 used in a semiconductor device package, the method comprising:
A method for manufacturing a lead pin, comprising forming a plurality of grooves 4 on the side surface of an eleventh surface and crimping a conductive material into these grooves 4 (see FIG. 2).

(2) A method of manufacturing lead pins 11 used in a semiconductor device package in which a front surface layer, a wiring layer, a mount layer, and a back surface layer are stacked, wherein a plurality of grooves 4 are formed on a side surface of each lead pin 11. A method of manufacturing a lead pin, comprising pressing a conductive material into these grooves 4 (see FIG. 2).

[0014]

The lead pin of the present invention has a structure in which a plurality of electrodes are wired for one lead pin when used in a PGA package. With such a structure, the number of lead pins used per PGA package can be reduced, and the space allocated to the arrangement and arrangement of the lead pins is reduced. Can be By utilizing the miniaturized PGA package, the packaging density of the semiconductor integrated circuit can be improved.

FIG. 1 is a view showing a lead pin of the present invention. FIG. 1 (a) is an overall perspective view thereof, and FIG. 1 (b) is a horizontal sectional view taken along the line AA in FIG. 1 (a). Is shown. As is apparent from FIG. 1, the lead pin 11 is formed by pressing a pin member 5 having a groove 4 on the opposite side surface and an electrode made of a conductive material (for example, Au wire) into the groove 4 as described later. It has a structure that was made.

When assembling a semiconductor device package using the lead pins of the present invention, for example, the connection between the lead pins (dimensions: 200 μm square, about 3 mm in length) and the package body (the back layer 17 in FIG. 4) is made on the package. Electrode terminal holes provided at lead pin positions (dimensions: 210 ± 5
μm square, depth of about 500μm)
Solder the electrode terminal material provided on the package body and the electrode provided on the lead pin side (Pb / Sn = 95/5 alloy, melting point approx.
(° C).

FIG. 1B is a cross-sectional view in which a convex portion 9 is provided on the surface of the electrode. The convex portion 9 is desirable for increasing the bonding force when the lead pin is inserted into the package body. Is not essential in the present invention.

Since the assembling is performed by the joining method, the joining force between the lead pin and the package body depends on the material of the material used for the electrode terminal material (eg, Mo-Mn material) of the package body and the electrode portion on the lead pin side. Is affected by
It is important to select the materials used for the lead pins, their electrodes, and electrode terminal materials.

Epoxy resin is suitable as a material for the lead pin. Epoxy resin has excellent heat resistance (about 300 ° C, at least 180 ° C or more) and insulation, as is conventionally used for LSI encapsulants.
This is because it can be formed by a molding method and has good workability. On the other hand, the strength of epoxy resin is lower than that of ordinary lead pin material (for example, material
To strength 60 kgf / mm ² of the lead pin material 42Ni-Fe, the strength of the epoxy resin becomes 34kgf / mm ^2). However, in the lead pin structure of the present invention, since a metal electrode is crimped to the side surface of the lead pin, there is no problem in strength, and by using epoxy resin, flexibility can be expected as a lead pin material. .

As the material of the electrode, a material having good conductivity may be used. However, since the electrode is pressure-bonded to the side surface of the lead pin, it is necessary to select a material that does not easily peel off after the pressure bonding. Considering this point, Au or Cu is suitable, and Au is particularly desirable.

As a method of providing the Au electrode on the side surface of the lead pin, there is a method of forming an Au thin film by a sputtering method or a vapor deposition method. Therefore, in the present invention, a method of crimping an Au wire (for example, a diameter of about 60 μm) or the like to the side surface of the lead pin is adopted. Assuming that the crimping method is adopted, Au is often used as an actual crimping material, and has high flexibility, so that crimping is easy. Furthermore, since Au has excellent solder wettability, the reliability of the electrical connection between the electrode of the lead pin and the electrode terminal material of the package body increases when joining the lead pin to the package body, and the mechanical property is improved. A sufficient bonding strength can also be ensured.

Although the shape of the lead pin is basically a polygonal pillar, it is preferably a square pillar (for example, a 200 μm square and about 3 mm long) for manufacturing reasons. As will be described in a specific manufacturing method described later, when soldering lead pins to the package body, it is possible to prevent the occurrence of an electrical short circuit or opening without making a mistake in the joining direction. This is because it becomes easy. However, in the practice of the present invention, there is no problem even if the shape of the lead pin is a column as long as the soldering is reliably performed.

It is desirable that the number of electrodes, which are a feature of the present invention and are wired by pressing against one lead pin, is 2 to 4. Wiring layer of general-purpose PGA package
In the wiring layer 15 in FIG. 4, the line width of the wiring used is about 150 μm, and the pitch interval between the lead pins is about 1000 μm. Therefore, it is limited to pass six wirings between the pitches. It becomes impossible to wire five or more electrodes to one. As described above, the shape of the lead pin is desirably a quadratic prism, but in this case, the number of grooves for electrode bonding to be processed is limited to four on each side surface. Becomes Furthermore, even when using the lead pin of the present invention, in consideration of the matching with the commonly used PGA package,
The diameter and pitch of the lead pins need to conform to the standard. For this reason, it is desirable that the number of electrodes be two or more and four or less per lead pin because of the above-mentioned restrictions. However, when designing the PGA package, increase the lead pin size (for example,
Even if a pentagonal or more polygonal prism shape is adopted and the lead pin pitch is further increased (for example,
(00 μm or more) If no problem occurs, the number of electrodes to be wired per lead pin can be five or more.

As described above, in the lead pin of the present invention,
Since one pin has a plurality of electrodes, the space for arranging the lead pins can be reduced. Therefore, by using the lead pins, the size of the package itself can be reduced, and the packaging density can be improved.

Next, the lead pin of the present invention and a method for manufacturing the same will be specifically described with reference to the drawings.

FIG. 2 is a view for explaining one embodiment of a method for manufacturing a lead pin according to the present invention. As shown in FIG. 1, the lead pin manufactured in the embodiment has a rectangular column shape, and two electrodes are crimped to the side surface thereof.

FIG. 2A shows a quadrangular prism 1 made of an epoxy resin, which is formed by a molding method and used as a base material of a lead pin, and has a size of 200 μm square and a length of 4 cm. (B) and (c) are square pillars 1 made of epoxy resin.
2 shows a method of processing the pin material 5 from the above. After fixing the square pole 1 with the fixing jig 2, the dicing saw 3 cuts a groove 4 (dimensions: about 100 μm in groove width × 30 μm in groove depth) on one side surface and the opposite side of the square pillar 1, and the pin material is cut. 5 is molded. The processed groove 4 is used as a groove for pressure bonding for securing the bonding strength between the lead pin and the electrode.

Next, (d) and (e) show a method of crimping a pin material and an electrode material. 60μm diameter as electrode
Then, the Au wire 6 is folded in two by a preliminary process of crimping, and is attached to the groove 4 from one end of the pin material 5. afterwards,
The Au wire 6 is pressed against the pin material 5 by the roller 8 having the concave portion 7, and at this time, the convex portion 9 is provided on the surface of the Au electrode.
The above effects are exhibited by the convex portions 9. Further, after forming the convex portion 9, an extra Au wire 6 is used by a file roller 10 so that the Au wire 6 does not protrude from the edge of the groove of the pin material 5.
Is shaved off, molded, and finished to a shape as shown in the horizontal sectional view of FIG.

In the same manner (f), after cutting the pin material 5 to a predetermined length, one end of the pin material 5 is processed into a pyramid shape (not shown) in order to make one end of the pin material 5 a tip of a lead pin.
Furthermore, since there is a risk that an electrical short circuit may occur at both ends of the pin material and the electrode when the pin material is kept pressed, the Au wires 6 at both ends crimped to the pin material 5 with a solution of the electrode (for example, aqua regia).
Is dissolved and removed to produce the lead pin 11 of the present invention shown in FIG.

FIGS. 3A and 3B are views for explaining a method of joining lead pins when a semiconductor device package is manufactured using the lead pins of the present invention. FIGS. 3A and 3B further show the joining state. FIG. 3 (c) shows the joining points of the lead pins in the PGA package. That is, after the lead pin 11 is inserted into the electrode terminal material 13 made of the material Mo-Mn provided on the back surface layer 17 of the ceramic package 12, it is joined with solder (Pb / Sn = 95/5 alloy), and Connected.

In the conventional PGA package, 528 lead pins are required, and the total arrangement area is 48 mm square (23.04 cm ² ). However, by using the lead pins of the present invention, 248 lead pins are used. As a result, the total array area became 42 mm square (17.64 cm ² ). Comparing the mounting areas, it can be seen that the use of the lead pin of the present invention can reduce the mounting area to about 75%, and can greatly improve the mounting density.

[0032]

According to the present invention, since the arrangement area of the lead pins can be reduced, a semiconductor device package smaller than the conventional one can be manufactured, and the mounting density of the semiconductor integrated circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a view showing a lead pin of the present invention, and FIG.
1A is an overall perspective view thereof, and FIG. 1B is a horizontal sectional view taken along the line AA in FIG.

FIG. 2 is a diagram illustrating one embodiment of a method for manufacturing a lead pin according to the present invention.

FIG. 3 is a diagram illustrating a method of joining lead pins when a semiconductor device package is manufactured using the lead pins of the present invention.

FIG. 4 is a diagram illustrating the structure of a PGA package.

[Explanation of symbols]

1 ... square pillar, 2 ... fixing jig, 3 ... dicing saw,
4 ... groove 5 ... pin material 6 ... electrode (Au wire) 7 ... concave part 8 ...
Roller 9: Convex part, 10: File roller, 11: Lead pin 12: PGA package (ceramic package), 13
… Electrode terminal material 14… Surface layer, 15… Wiring layer, 16… Mount layer, 17…
Back layer 18 ... Wiring

Claims (2)

(57) [Claims] 1. A lead used in a semiconductor device package.
A method of manufacturing a pin, the side of each lead pin
Multiple grooves and press the conductive material into these grooves.
A method for manufacturing a lead pin, comprising: 2. A method of manufacturing a lead pin used for a semiconductor device package having a surface layer, a wiring layer, a mount layer, and a back surface layer laminated, wherein a plurality of grooves are formed on a side surface of each lead pin, and these grooves are formed. A method of manufacturing a lead pin, comprising: crimping a conductive material onto a lead pin.