JP2839676B2 - Circuit pattern formation method - Google Patents

Circuit pattern formation method

Info

Publication number
JP2839676B2
JP2839676B2 JP2236423A JP23642390A JP2839676B2 JP 2839676 B2 JP2839676 B2 JP 2839676B2 JP 2236423 A JP2236423 A JP 2236423A JP 23642390 A JP23642390 A JP 23642390A JP 2839676 B2 JP2839676 B2 JP 2839676B2
Authority
JP
Japan
Prior art keywords
circuit pattern
circuit board
circuit
area
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2236423A
Other languages
Japanese (ja)
Other versions
JPH04116887A (en
Inventor
文朗 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2236423A priority Critical patent/JP2839676B2/en
Publication of JPH04116887A publication Critical patent/JPH04116887A/en
Application granted granted Critical
Publication of JP2839676B2 publication Critical patent/JP2839676B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は例えば電気機器および電子機器に用いられる
回路基板上に展開する回路パターンの形成方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming a circuit pattern developed on a circuit board used for, for example, electric equipment and electronic equipment.

(従来の技術) 一般に、電気機器および電子機器内部には回路パター
ンを有する回路基板が多数組み込まれている。大量生産
品においては、それらの回路基板上への回路パターン形
成には、量産性の良いウェットエッチング処理により形
成する方法が採用されていることが多い。例えば第4図
(a)に示すように、回路基板41が回路基板絶縁部51と
その一方の主面側に接着された回路パターン形成用の金
属層52からなり、その金属層52にポジレジスト層40を被
着する。
(Prior Art) In general, a large number of circuit boards having circuit patterns are incorporated in electric devices and electronic devices. For mass-produced products, a method of forming a circuit pattern on such a circuit board by wet etching with good mass productivity is often adopted. For example, as shown in FIG. 4 (a), a circuit board 41 is composed of a circuit board insulating portion 51 and a metal layer 52 for forming a circuit pattern adhered to one main surface thereof. The layer 40 is applied.

次に、上記ポジレジスト層40に、所望回路パターン52
が描かれているマスク42を密接させ、紫外線43を照射す
る(第4図(b))。
Next, a desired circuit pattern 52 is formed on the positive resist layer 40.
Are brought into close contact with each other and irradiated with ultraviolet rays 43 (FIG. 4 (b)).

ついで現像を施すとポジレジスト層40の上記感光部分
50bは除去される。なお、50aは上記マスク42によるポジ
レジスト層40の未感光部分である(第4図(c))。
Then, when development is performed, the above-described photosensitive portion of the positive resist layer 40 is formed.
50b is removed. Reference numeral 50a denotes an unexposed portion of the positive resist layer 40 by the mask 42 (FIG. 4 (c)).

次に、上記ポジレジスト層40の残された未感光部分50
bをマスクにしてエッチングを施すことにより、金属層5
2の剥離予定域が除去されて所望回路パターン形状の金
属層52aが残る(第4図(d))。
Next, the remaining unexposed portion 50 of the positive resist layer 40
By performing etching using b as a mask, the metal layer 5
The area 2 to be peeled is removed to leave the metal layer 52a having the desired circuit pattern shape (FIG. 4 (d)).

ついで、上記ポジレジスト層の未感光部分50aを除去
して所望形状の回路パターン金属層52aが回路基板絶縁
部51上に得られる(第4図(e))。
Next, the unexposed portion 50a of the positive resist layer is removed to obtain a circuit pattern metal layer 52a having a desired shape on the circuit board insulating portion 51 (FIG. 4 (e)).

このように、ウェットエッチング処理方式ではマスク
が必要となり、高精度、広面積になる程高額の費用が必
要となる。このため、一枚のマスクでできるだけ多くの
製品を量産して亘担を軽減する必要があった。最近の少
量生産品や開発型製品においては、たとえ回路パターン
の標準化が設計時点で成されていても全て標準回路パタ
ーンで説明することは困難であり、多くの場合新規開発
回路パターが必要となる。また、回路基板1枚に数枚の
マスクが必要であるような製品も多く、特に1台しか生
産しないような開発型システム製品においては、マスク
代だけで非常に高額なものとなってしまう問題があっ
た。更に、電気化学的手段にて処理されるため危険な薬
品を使用する工程がウェットエッチング処理にはあり、
技術的に無公害対策が必要で、そのため処理設備や処理
工程も複雑にならざるを得ず製造リードダイムが増大
し、これによっても高額なものとなってしまう問題があ
った。他の回路パターン形成方法においても、電気化学
的手段を用いないがマスクに代わるスクリーンが必要で
あり、回路基板絶縁部に導電塗料を印刷して焼き付ける
印刷法や、マスクは必要としないが電気化学的手段を用
いるレーザ露光法、同様に電気化学的手段を用いるパタ
ーンめっき法等も、上記のいずれかの問題があり、この
ため少量生産品や開発型製品の設計開発、製造におい
て、より低価格化が図れる代替技術の要求が強かった。
As described above, the wet etching method requires a mask, and the higher the precision and the area, the higher the cost. For this reason, it was necessary to mass-produce as many products as possible with one mask and reduce the burden. In recent small-volume products and development-type products, even if circuit patterns are standardized at the time of design, it is difficult to explain them all with standard circuit patterns, and in many cases, newly developed circuit patterns are required . Also, there are many products that require several masks per circuit board. In particular, in a development-type system product in which only one is produced, the cost for the mask alone becomes very expensive. was there. Furthermore, there is a process in the wet etching process that uses dangerous chemicals because it is processed by electrochemical means,
Technically, pollution-free countermeasures are required, so that the processing equipment and processing steps must be complicated, and the number of manufacturing lead dimes increases, which is also expensive. In other circuit pattern forming methods, a screen instead of a mask is necessary without using electrochemical means, and a printing method in which conductive paint is printed and baked on a circuit board insulating portion, and a mask is not required but electrochemical method is required. The laser exposure method using a conventional method and the pattern plating method using an electrochemical method also have any of the above-mentioned problems. Therefore, lower cost is required in the design, development, and manufacture of small-scale products and development-type products. There was a strong demand for alternative technologies that could be used.

(発明が解決しようとする課題) 以上述べたように従来の回路パターンは多くの場合ウ
ェットエッチング処理により形成されるため、多数のマ
スクを使用するわりには生産台数の少ない製品におい
て、機能に見合った低価格化が計れないという欠点があ
った。
(Problems to be Solved by the Invention) As described above, the conventional circuit pattern is often formed by wet etching, and therefore, in a product with a small number of production units, a large number of masks are used, and the product is suitable for its function. There was a disadvantage that the price could not be reduced.

本発明は、上記の欠点を除去すべくなされたもので、
マスクを用いた複雑なウェットエッチング処理工程を経
ず回路基板上に回路パターンを形成することを目的とす
る。
The present invention has been made to eliminate the above disadvantages,
An object of the present invention is to form a circuit pattern on a circuit board without going through a complicated wet etching process using a mask.

〔発明の構成〕[Configuration of the invention]

(課題を解決するための手段) 本発明に係る回路パターンの形成方法は、絶縁基板と
この上に積層された金属箔の導電層からなる回路基板の
該導電層を一部除去して所定回路パターンに形成するに
あたり、導電層に対し回路パターン予定域と剥離予定域
の境界部に高密度レーザ光束を照射して除去し、次いで
導電層の剥離予定域に低密度レーザ光束を照射し絶縁基
板との付着力を低減させて剥離除去する手段を含む回路
パターンの形成方法。
(Means for Solving the Problems) In a method for forming a circuit pattern according to the present invention, a predetermined circuit is formed by partially removing a conductive layer of a circuit board composed of an insulating substrate and a conductive layer of a metal foil laminated thereon. In forming the pattern, the conductive layer is removed by irradiating a high-density laser beam on the boundary between the planned circuit pattern area and the planned peeling area, and then irradiated with a low-density laser beam on the planned peeling area of the conductive layer. A method for forming a circuit pattern, comprising means for removing and removing the adhesive force of the circuit pattern.

(作 用) 本発明においてはエッチング処理工程を用いずに回路
基板上に回路パターンを形成するようにしたので、エッ
チング処理にて発生する種々の欠点を除去する。更に回
路パターン設計時点よりCADを採用し数値制御機械等を
直結しておくことにより完全自動化を図ることができ、
少量生産における回路基板の回路パターンの形成におい
ても低価格、かつ短時間で達成できる。
(Operation) In the present invention, since a circuit pattern is formed on a circuit board without using an etching process, various defects generated in the etching process are eliminated. Furthermore, by adopting CAD from the point of circuit pattern design and connecting directly to numerical control machines, etc., complete automation can be achieved,
Even in the formation of a circuit pattern on a circuit board in small-scale production, it can be achieved at low cost and in a short time.

(実施例) 以下、本発明における一実施例について図面を参照し
て説明する。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

一実施例に用いられる第3図のレーザ加工装置におけ
るYAGレーザ加工装置部30は、レーザ開閉および出力レ
ベル等の加工に関する要因を制御装置31により制御する
ようになっており、レーザ光の投射口に専用高精度光学
レンズ32を具備し、さらにその直下に、回路基板33の金
属層面をレーザ光束34に対し垂直に固定できる治具を有
する高精度移動テーブル35が設置されている。この高精
度移動テーブル5は縦横斜め回転のそれぞれの移動およ
び修正が可能でYAGレーザ加工装置部30と共通の制御装
置31により制御されるものである。また、YAGレーザ加
工装置部30と高精度移動テーブル35を制御する制御装置
31は、CAD装置36に接続されており、このCAD装置36で作
画した回路パターンの数値データのやり取りができるよ
うに構成されている。
A YAG laser processing device section 30 in the laser processing device of FIG. 3 used in one embodiment is configured such that factors related to processing such as laser opening and closing and an output level are controlled by a control device 31. A high-precision moving table 35 having a dedicated high-precision optical lens 32 and a jig that can fix the metal layer surface of the circuit board 33 vertically to the laser beam 34 is provided immediately below. This high-precision moving table 5 can be moved and corrected in vertical, horizontal, and oblique rotations, and is controlled by a control device 31 common to the YAG laser processing device 30. Also, a control device for controlling the YAG laser processing unit 30 and the high-precision moving table 35
Numeral 31 is connected to a CAD device 36 so that numerical data of a circuit pattern created by the CAD device 36 can be exchanged.

本発明の回路パターン形成方法では、上記CAD装置36
で作画した回路パターンの数値データを制御装置31が受
け取り、レーザ開閉および出力レベル等の加工に関する
要因の制御および高精度移動テーブル35の制御を施し、
第1図(a)に、またこの図の破線円で囲み示す部分を
拡大して第2図に示すように、高密度YAGレーザ光束10
を専用光学レンズ11を用いて絞り込み、回路基板12上に
金属層23に形成される所望回路パターンの予定域23aと
剥離予定域23bの境界部に沿って照射する。このレーザ
光照射により境界部の金属層のみを昇華除去し切断し
て、それら予定域間に回路基板絶縁部22が底に露出する
境界溝13を作り、それら予定域間が別離される。
In the circuit pattern forming method of the present invention, the CAD device 36
The control device 31 receives the numerical data of the circuit pattern drawn in the above, performs control of factors related to processing such as laser opening and closing and output level, and controls the high-precision moving table 35,
FIG. 1A is an enlarged view of a portion surrounded by a broken-line circle in FIG. 1A, and as shown in FIG.
Is squeezed using the dedicated optical lens 11 and is irradiated along the boundary between the planned area 23a of the desired circuit pattern formed on the metal layer 23 on the circuit board 12 and the planned peeling area 23b. By this laser beam irradiation, only the metal layer at the boundary portion is removed by sublimation and cut to form a boundary groove 13 where the circuit board insulating portion 22 is exposed at the bottom between the predetermined regions, and the predetermined regions are separated from each other.

次に、第1図の(b)に示すように、低密度YAGレー
ザ光束20を金属層の剥離予定域23bにのみ照射し加熱す
る。この加熱処理によって、回路基板における金属層23
の剥離予定域23bと回路基板絶縁部22との間の付着力が
低下する。
Next, as shown in FIG. 1 (b), the low-density YAG laser beam 20 is irradiated only on the area 23b where the metal layer is to be separated, and heated. By this heat treatment, the metal layer 23 on the circuit board is
The adhesive force between the expected peeling region 23b and the circuit board insulating portion 22 is reduced.

次に、第1図(c)に示すように、剥離装置14を用い
て上記剥離予定域23bの金属層のみに対し剥離すること
により、回路パターン形成予定域23aの金属層が残留し
所望の回路パターン15が形成される。
Next, as shown in FIG. 1 (c), only the metal layer in the scheduled area 23b is peeled off using the peeling device 14, so that the metal layer in the area 23a where the circuit pattern is to be formed remains and a desired layer is left. The circuit pattern 15 is formed.

〔発明の効果〕〔The invention's effect〕

以上述べたようにこの発明によれば、エッチング処理
工程を用いずに回路基板上に回路パターンが形成でき
る。これによりエッチング処理にて発生する種々の欠点
から容易に解放され、更に回路パターン設計時点よりCA
Dを採用し数値制御機械等と直結しておけば完全自動化
を図ることもでき、たとえ1枚しか生産しない回路基板
の回路パターンの形成においても低価格でしかも短時間
で提供できる。
As described above, according to the present invention, a circuit pattern can be formed on a circuit board without using an etching process. As a result, various drawbacks caused by the etching process can be easily released, and the CA
If D is used and is directly connected to a numerical control machine or the like, complete automation can be achieved, and even in the case of forming a circuit pattern on a circuit board that produces only one sheet, it can be provided at a low cost and in a short time.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(c)は本発明の一実施例に係わる回路
形成方法を工程順に説明するためのいずれも斜視図、第
2図は第1図(a)の一部を拡大して示す斜視図、第3
図は回路形成に用いられるレーザ加工装置の斜視図、第
4図(a)〜(e)は従来の回路形成方法を工程順に説
明するためのいずれも斜視図である。 10……高密度レーザ光束、12……回路基板 20……低密度レーザ光束、22……回路基板絶縁部 23……回路基板の金属層 23a……回路パターンの形成予定域 23b……剥離予定域
1 (a) to 1 (c) are perspective views for explaining a circuit forming method according to an embodiment of the present invention in the order of steps, and FIG. 2 is an enlarged view of a part of FIG. 1 (a). Perspective view, third
The drawings are perspective views of a laser processing apparatus used for circuit formation, and FIGS. 4 (a) to 4 (e) are perspective views for explaining a conventional circuit formation method in the order of steps. 10 high-density laser beam, 12 circuit board 20 low-density laser beam 22, circuit board insulating part 23 metal layer of circuit board 23a circuit pattern formation area 23b peeling Area

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基板とこの上に積層された金属箔の導
電層からなる回路基板の該導電層を一部除去して所定回
路パターンに形成するにあたり、導電層に対し回路パタ
ーン予定域と剥離予定域の境界部に高密度レーザ光束を
照射して除去し、次いで導電層の剥離予定域に低密度レ
ーザ光束を照射し絶縁基板との付着力を低減させて剥離
除去する手段を含む回路パターンの形成方法。
1. A circuit board comprising an insulating substrate and a conductive layer of a metal foil laminated thereon, wherein said conductive layer is partially removed to form a predetermined circuit pattern. A circuit including a means for irradiating a boundary portion of an area to be peeled with a high-density laser beam to remove the area, and then irradiating an area to be peeled of the conductive layer with a low-density laser beam to reduce adhesion to an insulating substrate and to remove the area. The method of forming the pattern.
JP2236423A 1990-09-06 1990-09-06 Circuit pattern formation method Expired - Fee Related JP2839676B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2236423A JP2839676B2 (en) 1990-09-06 1990-09-06 Circuit pattern formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2236423A JP2839676B2 (en) 1990-09-06 1990-09-06 Circuit pattern formation method

Publications (2)

Publication Number Publication Date
JPH04116887A JPH04116887A (en) 1992-04-17
JP2839676B2 true JP2839676B2 (en) 1998-12-16

Family

ID=17000538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2236423A Expired - Fee Related JP2839676B2 (en) 1990-09-06 1990-09-06 Circuit pattern formation method

Country Status (1)

Country Link
JP (1) JP2839676B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010000881A (en) * 2000-10-25 2001-01-05 안지양 The method of forming circuit pattern on circuit board
DE102010019406B4 (en) * 2010-05-04 2012-06-21 Lpkf Laser & Electronics Ag Method for partially releasing a defined area of a conductive layer
DE102010019407B4 (en) 2010-05-04 2013-06-27 Lpkf Laser & Electronics Ag Method for introducing electrical insulation into printed circuit boards
US20200246910A1 (en) * 2019-02-05 2020-08-06 Preco, Inc. Laser cutting metal foil with a polymer backing layer

Also Published As

Publication number Publication date
JPH04116887A (en) 1992-04-17

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