JP2834881B2 - Data judgment device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data determination device for reading address information recorded on a recording medium such as a video disk.

[Conventional technology]

2. Description of the Related Art Conventionally, a data determination device has been widely used as a circuit for detecting address information recorded on a recording medium such as a video disk. In such a recording medium, the quality of a reproduced signal is significantly reduced due to dropout or the like, which may hinder reading of an address signal. An erroneous reading of the address information causes a malfunction at the time of random access, an erroneous display of the current playback position, and the like, and the quality of the playback device is significantly reduced. Therefore, there is a demand for a data discriminating apparatus in which the reading error of the address information is small even if the quality of the reproduced signal is degraded.

Next, a conventional data determination device will be described with reference to a data determination device used for a video disk. In the composite video signal reproduced by the video disk, it is assumed that address information is recorded over three lines as shown in FIG. 4A in synchronization with the horizontal synchronizing signal within the vertical bright line period. FIG. 4B shows the address signal of one horizontal scanning line enlarged on the time axis, and 24-bit address information is recorded in one horizontal synchronization period. The time from the horizontal sync signal to the first bit is
The time between T1 and the bit is defined as T2. The address information is represented by the logical inversion direction of the signal. The edge from 0 to 1 indicates “1” of the data, and the edge from 1 to 0 indicates “0”. Therefore, when data “1” or “0” continues, it is assumed that an edge occurs between bits as shown. The address information recorded in this manner is read by the data determination device.

FIG. 5 is a block diagram showing an example of a conventional data determination device. In this figure, an input terminal 1 is a terminal to which a composite video signal including data is input as shown in FIG. 6 (a), for example. The sync separation circuit 2 extracts only the sync signal from the composite video signal, and its output is supplied to the sync processing circuit 3. The synchronization processing circuit 3 generates a timing signal of a horizontal scanning line on which data is recorded and a trailing edge timing signal of the horizontal synchronization signal shown in FIG. 6 (b) as a data gate signal from the input synchronization signal. , And outputs a horizontal scanning timing signal to the first AND circuit 5. Data separation circuit 4
Is 50IR for the composite video signal given to input terminal 1.
By slicing at the level of E, FIG. 6 (c)
As shown in (1), the signal is converted into a binary digital signal, and its output is given to the AND circuit 5 as a data signal. The AND circuit 5 supplies only the data of the line on which the data is recorded to the edge detection circuit 6 and the D flip-flop 7 by the logical product output with the data gate signal.
The edge detection circuit 6 detects the rise and fall of the output signal of the AND circuit 5, and outputs a positive pulse as an edge signal as shown in FIG. 6 (d). The timing signal at the trailing edge of the horizontal synchronization signal of the synchronization processing circuit 3 is supplied to the set input terminal of the first RS flip-flop 8 and the NOR circuit 9 having a negative logic input. The data determination device has a clock oscillator 10 for generating a constant clock signal, and its output is provided to first and second counters 11 and 12. The counter 11 counts this clock and outputs the result to the NOR circuit 9.
The counter output is reset by the output of the first and second decoders 13 and 14, and the counted output is supplied to the first and second decoders 13 and 14. The decoders 13 and 14 output pulses of positive polarity to the AND circuits 15 and 16 when the count value of the counter 11 reaches a set value. A data detection timing signal is supplied from the NOR circuit 17 described later to the RS flip-flop 8 as a reset signal. Therefore, the RS flip-flop 8 is the sixth
Is set at time t ₁ of the rear end of the horizontal synchronizing signal as shown in FIG. (E), Q outputs of between times t ₃ when the first bit of data is detected 1, and the other time 0 Become. And
During the period when the RS flip-flop 8 is set, the output of the first decoder 13 is output, and during the period when the RS flip-flop 8 is reset, the outputs of the AND circuits 15 and 16 and the NOR circuit 18 are output.
Is transmitted to the set input terminal of the second RS flip-flop 19. The decoder 13 is for setting after the counter 11 at time t ₁ is reset, the flip-flop 19 at time t ₂ by counting a predetermined number of pulses as shown in Figure No. 6 (f). Also since the time t ₃ the flip-flop 8 and 19 is reset, thereafter the time t ₃ ~ by the decoder 14
until t _4, the flip-flop 19 by the output from the decoder 14 into ...... between times t ₅ ~t ₆ are set. That the second RS flip-flop 19 is set at time t ₂ when the predetermined time T3 has elapsed from the edge of the timing following the horizontal synchronizing signal as shown in Figure 6 (f), also this point on FIG. 6 (d)
Are set every time T4 from the edge detection timing shown in FIG. The output of the NAND circuit 21 is supplied to the D-type flip-flop 7, and the AND circuit 5
Is latched, and the latch result is output from the first output terminal 22 as shown in FIG. 6 (h). Then, an AND signal of the output of the edge detection circuit 6 and the output of the RS flip-flop 19 is output from the second output terminal 23 as a data detection signal as shown in FIG. 6 (h). Since the latch result of the D-type flip-flop 7 is the level of the data signal immediately after the edge detection, the rising edge shown in FIG. 6A matches 1 and the falling edge matches 0. Thus, data output can be obtained from the first output terminal 22. The second flip-flop 19 is reset via the NOR circuit 17 by the output of the NAND circuit 21. The counter 12 counts the pulses of the clock oscillator 10, and the decoder 20 outputs a negative pulse from the output terminal 24 when the counted value reaches a predetermined value. If the output of the edge detection circuit 6 appears before the counting is completed, the RS flip-flop 19 is reset via the NAND circuit 21 and the NOR gate 17, and the Q output resets the counter 12.
Therefore, no pulse of negative polarity appears from the decoder 20. That is, only when the output of the edge detecting circuit 6 does not appear at the output terminal 24 for a certain period of time determined by the decoder 20 while the second RS flip-flop 19 is 1 (FIG. 6 (h)). As shown in (1), a pulse of negative polarity appears. This occurs only when the data signal is lost due to dropout of the recording medium or the like, as shown by a broken line m in FIG. 6 (a). That is, a signal indicating that data cannot be determined is output from the third output terminal 24.

The RS flip-flop 19 is set at a time slightly before the edge signal of the data to be determined as shown in FIG. 6 (f). Therefore, if the setting of the count time of the decoder 20 is set slightly behind the edge signal of the data to be determined as shown by j in FIG. 6 (f), the set state is set only for a short time before and after the edge signal. Becomes That is, while the RS flip-flop 19 is in the reset state, even if noise remains in the data signal, it can be removed.
The edge e between bits can also be removed as shown in FIG. Thus, the output of the RS flip-flop 19 functions as a data detection window. Since the signal reproduced from the recording medium contains a lot of jitters and the like, and it is necessary to consider the rotation error of the video disk at the time of starting, the width of the data detection window is determined by these conditions. Data detection window is decoder 20
, Or is opened and closed until an edge is detected in the data detection window. Since the edge signal detected in the data detection window passes through the NOR circuit 17 and is input to the reset terminal of the counter 11, the RS flip-flop 19 is set again after a certain time determined by the decoder 14 after the edge is detected. Then, a data detection window is opened to determine the data of the next bit.

[Problems to be solved by the invention]

However, in such a conventional data determination device,
Consider a case where a part of the data detection signal is missing as shown by a broken line n as shown in FIG. 6 (a). In this case, since the data indicated by the dashed line is originally present, the logic of this data must fall, that is, be zero information. However, since a part of the signal is missing, the rising edge of the data signal is detected immediately after the data detection window (RS flip-flop 19) is set, and it is determined that the data is data according to the edge direction of the data signal. At this time, since the edge of the data signal is detected in the data detection window, no pulse output appears at the output terminal 24. Therefore, the data cannot be determined and the logic of the data is set to 1
Erroneously determined that

As described above, in the conventional data determination device, since the edge of the input data is detected immediately after the data detection window is opened, an erroneous determination is made when a part of the data is lost due to dropout or the like. There were drawbacks.

The present invention has been made in view of such a conventional problem, and it is an object of the present invention to provide a data determination device that does not make an erroneous determination even when a part of data is lost due to dropout or the like. Make it an issue.

[Means for solving the problem]

The present invention is a data determination device that determines data transmitted by inversion of a logic level at a predetermined timing, and includes an edge detection circuit that detects inversion of a logic level of an input signal, and timing of logic inversion of the input signal. A window control means for setting the data detection circuit to an active state at predetermined time intervals; and a logic inversion detected while the edge detection circuit is in the active state is detected at a time closest to a specific time in the active state. Edge selection means for selecting the logic inversion edge, data output means for outputting logic information in accordance with the logic inversion direction selected by the edge selection means, and a fixed time window from the time of the logic inversion selected by the edge selection circuit. And delay means for delaying the output by the control means.

[Action]

According to the present invention having such features, the inversion of the logic of the input signal sequence is detected by the edge detection circuit,
The edge detection circuit is activated every predetermined time including the timing of the logical inversion of the input signal to prevent noise due to signal determination in other time zones. When a plurality of logical inversions are detected by the edge detection circuit within the window, the edge selecting means selects an edge closest to a specific time, that is, the timing at which the data is inverted, and determines data based on the logical inversion. ing. Thereafter, in order to prevent the timing of the window from shifting, the operation of the window is delayed from the selected logical inversion time.

〔Example〕

Next, a data discriminating apparatus according to an embodiment of the present invention will be described with reference to the drawings, taking a video disc as an example. FIG. 1 is a block diagram showing a configuration of a data determination device according to one embodiment of the present invention. In FIG. 1, an input terminal 31 is a terminal to which a composite video signal including data is input.
The output is supplied to a sync separation circuit 32 and a data separation circuit 34. The synchronization separation circuit 32 extracts only the synchronization signal from the composite video signal, and its output is provided to the synchronization processing circuit 33. The synchronization processing circuit 33 supplies a timing signal of a horizontal scanning line on which data is recorded from the input synchronization signal to the AND circuit 35 as a data gate signal. The data separation circuit 34 converts the composite video signal supplied to the input terminal 31 into a binary digital signal by slicing the composite video signal at a level of 50 IRE, and the output thereof is supplied to the AND circuit 35 as a data signal. The AND circuit 35 supplies only the data of the line in which the data is recorded by the data gate signal to the edge detection circuit 36 and the D flip-flop 37 by the logical product output.
The edge detection circuit 36 detects the rising and falling edges of the output signal of the AND circuit 35, and outputs a positive pulse as an edge signal. The timing of the trailing edge signal of the synchronization processing circuit 33 is given to an RS flip-flop 38 and a NOR circuit 39 having a negative logic input. The data determination device has a clock oscillator 40 for generating a constant clock signal, and its output is provided to first and second counters 41 and 42. The counter 41 counts the clock signal and outputs a NOR circuit.
Reset by 39 clocks and data conversion circuit
The counter is loaded with a numerical value by the load data 43, and its output is given to the first and second decoders 44 and 45. The decoders 44 and 45 output pulses of positive polarity to the AND circuits 46 and 47 when the count values of the counter 41 are different from each other. The AND circuits 46 and 47 and the NOR circuit 48 constitute a switch circuit in which one of the outputs is selected by the output of the RS flip-flop 38,
The output is supplied to the second RS flip-flop 49 in the same manner as in the above-described conventional example. The second counter 42
Counts the clock generated by the clock oscillator 40, and its output is supplied to the third and fourth decoders 50 and 51. When the value of the counter 42 becomes a predetermined value, the decoder 50 gives a pulse of negative polarity to the flip-flop 49 to reset it. On the other hand, the decoder 51 increases the output of the second counter 50 as it approaches the center of the data detection window,
The value is converted to a value that decreases as the distance from the center increases, and the output is used as position information in the first data register 52.
Output to

The Q output of the flip-flop 49 and the output of the edge detection circuit 36 are supplied to a NAND circuit 53. The NAND circuit 53 supplies the logical product output to the data registers 52, 54, the first D flip-flop 37, the D flip-flop 55, and the third counter 56. D flip-flop 37,5
The output of 5 is output as a holding signal of the data registers 52 and 54, respectively. The first data register 52 holds the supplied data by the timing pulse of the AND circuit 53, and its output is supplied to the second data register 54 and the magnitude comparator 57. Data register
Numeral 54 holds the given data as a timing pulse of the NAND circuit 53, and its output is given to the magnitude comparator 57 and the data conversion circuit 43. The third counter 56 counts the output of the NAND circuit 53, that is, the number of edge signals detected when the second RS flip-flop 49 is set (when the data detection window is open). The output is provided to a fifth decoder 58. The decoder 58 decodes this output and outputs 3-bit outputs Q1, Q2, Q3. The following table shows the input / output relationship of the fifth decoder 58.

On the other hand, the magnitude comparator 57 is a data register
This is to compare the position information held in 52 and 54. When the position information (1)> the position information (2), “1” is set. When the position information (1) ≦ the position information (2), the position information is “1”. 0 ”is output. This output is supplied to an AND circuit 59 and a NAND circuit 60.
Given to. The NAND circuit 59 supplies a logical product of this output and the output Q3 of the decoder 58 to the OR circuit 61. OR circuit
61 controls the switch 62 based on the logical sum signal with the Q2 output of the decoder 58. Switch 62 is OR circuit 61
Is "1", the first D flip-flop 3
7. When "0", the output of the second D flip-flop 55 is supplied to the first output terminal 63. The NAND circuit 60 calculates the first counter value by the logical product of the output of the fifth decoder Q3 and the output of the magnitude comparator 57.
41 to give the load output. The output of the decoder 50 is output from the second output terminal 64 as a data detection signal, and the Q1 output of the decoder 58 is output from the output terminal 65 as a signal indicating that data cannot be detected. Here, RS flip-flop 38, OR circuit 39, clock oscillator 40, counter 4
1. The decoders 44 and 45, the AND circuits 46, 47 and 53, the NOR circuit 48, and the RS flip-flop 49 constitute a window control unit that activates the edge detection circuit every predetermined time including the timing of logical inversion. The clock oscillator 40, the counter 42, the decoder 51, the data registers 52 and 54, the magnitude comparator 57 and the AND circuit 59, the OR circuit 61 and the switch 62 detect the edge of the logical inversion detected at the time closest to the specific time in the window. This constitutes an edge selecting means for selection. The D flip-flops 37 and 55 constitute data determining means for outputting logic information according to the direction of logic inversion selected by the edge selection circuit. Further, the counter 56, the decoder 58, the NAND circuit 60, the data conversion circuit 43, and the counter 41 constitute a delay unit for delaying the output by the window control unit for a certain period of time from the logical inversion time selected by the edge selection circuit. .

Next, the operation of this embodiment will be described. Also in this embodiment, as shown in FIG. 2A, a composite video signal including data is supplied to an input terminal 31 and a sync separation circuit is provided.
The synchronization signal is separated by 32, and a data signal as shown in FIG. 2 (c) is output by the logical product of the data separation circuit 34 and the synchronization processing circuit 35. Also, the trailing edge timing signal of the horizontal synchronization signal shown in FIG. 2B is output from the synchronization processing circuit 33, and the flip-flop 38 is set. While the flip-flop 38 is set, the output of the decoder 44 supplies the set signal to the RS flip-flop 49 via the switch circuit including the AND circuits 46 and 47 and the NOR circuit 48 in the same manner as in the above-described conventional example. . FIG. 2 (e) shows the operation of the RS flip-flop 38, in which the time from the trailing edge of the horizontal synchronizing signal until the first bit data is detected is 1. During this time, the first decoder 44 and the second and subsequent bits are determined by the second decoder 45. The time T5 in FIG.
This is the time until the RS flip-flop 49 is set. The RS flip-flop 49 is set at a time slightly before the edge of the data signal to be determined, and the count time setting of the third decoder 50 is set to be slightly smaller than the edge of the data signal to be determined as shown in FIG. Set to be behind. In this case, the RS flip-flop 49 becomes as shown in FIG.
It functions as a data detection window as shown in FIG. Since the signal reproduced from the recording medium contains a lot of jitters and the like, it is necessary to consider the rotation error of the disk when starting the video disk.
Is determined by those conditions.

FIG. 3 is a diagram showing the outputs of the second counter 42 and the fourth decoder 51. In the data detection window of the RS flip-flop 49, the counter 42 counts up in accordance with the clock as shown in FIG. 3 (a), and the decoder 51 responds accordingly, as shown in FIG. 3 (b). The position information that maximizes the median is given to the data register 52. Now, with the data detection window open, one edge signal is normally detected. Therefore, the counter 56 counts 1, and the output of the decoder 58 becomes 1 and the output of the OR circuit 61 becomes 1 as shown in Table 1. At this time, the switch 62 is set to the A side, and the output of the first D-type flip-flop 37 is output from the output terminal 63 as shown in FIG. 2 (h). Since the output of the D flip-flop 37 is the logic of the data of the detected edge signal, the data contained in the video signal can be output as shown in FIG. 2 (h). Since the output of the decoder 50 is generated at the end of the data detection window of the RS flip-flop 49, it can be output from the output terminal 64 as a data detection signal as shown in FIG. 2 (i). Further, as shown in Table 1, Q1 of the fifth decoder 58
The output is 0, and this is regarded as an undeterminable signal and output terminal 65
Can output more.

Also, the data detection window is opened and closed for a time determined by the third decoder 50. Then, since the edge signal detected in the data detection window is added as a reset signal to the counter 41 via the NAND circuit 39, the flip-flop 49 is turned on again after a predetermined time T7 has elapsed since the edge was detected (FIG. 2). Set as shown in f). Thus, a data detection window at time T6 is opened to determine the data of the next bit.

Now, a case where data is lost as shown by a broken line m in FIG. 2A will be described. In this case, since no edge detection is performed in the data detection window, the input of the decoder 58 becomes 0. Therefore, the output is as shown in Table 1.
Q1 becomes 0, and a determination impossible signal is output from the output terminal 65. If the output of the output terminal 65 is determined at the timing of the negative pulse output to the output terminal 64, the result is 0.
It can be seen that the data has been correctly determined at the time of, and that the data has not been correctly determined at the time of 1.

Next, a case where a part of data is lost as indicated by n in FIG. 2A will be described. In this case, the edge signal is output twice in the data detection window as shown in FIGS. 2 (c), 2 (d) and 2 (f). First, when the first edge signal is detected, the AND circuit 35 at that time is detected.
Is stored in the D flip-flop 37 at the same time as the output of the decoder 51, that is, the position information is stored in the first flip-flop 37.
Is stored in the data register 52. At this time, the decoder 51
As described above, the position information, which is the output of the data detection window, becomes larger as the time is closer to the center of the data detection window. Next, when the second edge signal is detected, the output of the AND circuit 35 at that time is stored in the D flip-flop 37, and at the same time, the first output of the previous edge stored in the flip-flop 37 is stored. The output of the gate 35 is a D flip-flop 55
And the position information of the decoder 51 at that time is stored in the data register 52. At the same time, the position information at the time of the previous edge signal stored in the first data register 52 is stored in the second data register 54. When the edge signal is detected twice, there is a high probability that the edge signal closer to the center of the data detection window is a correct data position. Therefore, which of the two edge signals is closer to the center of the data detection window depends on the first and second signals.
Can be determined by comparing the position information of the data registers 52 and 54 described above. The magnitude comparator 57 determines the position information of the input, and in the case of the data window p shown in FIG. 2 (f), the edge detected later is closer to the center of the data detection window. The output of 57 becomes 1. In this case, since the input of the decoder 58 is 2, the output is 0 for the output Q2 and 1 for the output Q3 from Table 1. Therefore AND circuit 59
Is satisfied, the output becomes 1 and the switch is set to the A side via the OR circuit 60. Thus the first
Of the flip-flop 37, that is, the data detected later is output from the first output terminal 63. In this case, the first counter 41 is reset by the edge signal detected later, and then the detection window is opened again at the time determined by the decoder 45, and the next data is determined.

In the case where the latter half of the data is lost as shown by a broken line q in FIG. 2A, the edge detected later is more data as shown by a data detection window r in FIG. 2F. Close to the center of the detection window. In this case, the output of the magnitude comparator 57 becomes 0. Also in this case, since the input of the decoder 58 is 2, the output of the decoder 58 is 0 for Q2 and 1 for Q3 from Table 1. Therefore, the output of the AND circuit 59 is 0 because one of its inputs is 0, the output of the OR circuit 60 is also 0, and the switch 62 is set to the A side. Also in this case, the data of the D flip-flop 55 detected earlier is output from the first output terminal 63. The first counter 41 must open the next data detection window based on the position of the previously detected edge (the edge determined to be correct). Will be reset,
Next, the timing at which the data detection window is opened is shifted, and the next data determination cannot be performed correctly. Therefore, two edge signals are detected in the data detection window,
If it is determined that the previously detected edge signal is correct (Q3 output of decoder 58 is 1, magnitude comparator
In the case where the output of 57 is 0), a load signal is generated by the AND circuit 60, and a value to be taken by the counter at that time is obtained from the position detected previously by the data conversion circuit 43,
The value is loaded into the counter 41. In this way, after the reset is performed by the previously detected edge signal, the same count value as when the reset is not performed by the later detected edge signal can be obtained. By continuing the counting operation in this manner, the time at which the next data detection window is opened can be made correct. When two edge signals are detected in the data detection window, the output Q1 becomes 0 according to Table 1, and the value is output to the third output terminal 65. As a result, it is determined that the data has been correctly determined, so that the output of the second output terminal 64 can be used as a data detection signal, and the output of the output terminal 63 can be taken out as its data logic.

When three or more edge signals are detected in the data detection window, the input to the decoder 58 becomes three or more, and the output of the decoder 58 becomes 1 as shown in Table 1. Therefore, similarly to the case where the data situation is missing, it can be output to the outside that the data cannot be correctly determined by the output of the output terminal 65. As described above, in this embodiment, among the edges detected during the period in which the data detection window is set, the edge closest to the center of the data detection window is detected, so that part of the data is lost due to dropout or the like. In this case, an erroneous determination can be prevented.

In the present embodiment, the number of edges detected in the data detection window is up to two valid. However, a third D-type flip-flop and a third data register are provided and a decoder 58 is provided.
Also provides an output when the input becomes three, and the magnitude comparator correspondingly detects the largest one from the three inputs, thereby validating up to three edges in the output window. It is also possible.
Further, by a similar extension, a data determination device capable of determining data from a larger number of edges can be configured.

Further, in the present embodiment, the output of the decoder 51 is maximum at the center of the data detection window and minimum at both ends. However, the output of the decoder 51 is minimum at the center of the data detection window and maximum at both ends. It is also possible to detect the smallest one by inverting the logic of.

〔The invention's effect〕

As described above in detail, according to the present invention, even when a part of data is lost due to dropout or the like, data is determined based on a change in an edge closest to the center value of the window. The possibility of erroneous determination can be extremely reduced. Therefore, when used in a circuit for detecting address information of a video disk or the like, it is possible to provide a data judging device in which reading errors of address information are small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a data judging device according to one embodiment of the present invention, FIG. 2 is a time chart showing the operation of this embodiment, and FIG. 3 is a decoder 50, 51 and counter of this embodiment. A time chart showing the relationship between the count value and the data detection window of 42, FIG. 4 is a tie chart showing an example of data superimposed on the composite video signal, FIG. 5 is a circuit diagram showing an example of a conventional data determination device, FIG. 6 is a time chart showing the operation. 32: Sync separation circuit, 33: Synchronization processing circuit, 34: Data separation circuit, 35, 46, 47, 59 ... AND circuit, 53, 60 ... NAND circuit, 39, 48 ... NOR circuit, 61 …… OR circuit, 36…
... Edge detection circuit, 37,55 ... D flip-flop, 38,
49 …… RS flip-flop, 40 …… Clock oscillator, 4
1,42,56 …… Counter, 44,45,50,51,58 …… Decoder, 4
3 …… Data conversion circuit, 52,54 …… Data register, 57…
… Magnitude comparator, 62 …… switch, 63,6
4,65 …… Output terminal.

Claims (3)

(57) [Claims] 1. A data judging device for judging data transmitted by inversion of a logic level at a predetermined timing, an edge detection circuit detecting inversion of a logic level of the input signal, and a logic inversion of the input signal. Window control means for setting the data detection circuit to the active state at predetermined time intervals including the timing of: a specific time during the active state of the logic inversion detected while the edge detection circuit is in the active state Edge selection means for selecting a logical inversion edge detected at a time closest to the time, data output means for outputting logic information according to the logical inversion direction selected by the edge selection means, and an edge selection circuit. Delay means for delaying the output by the window control means for a fixed time from the time of the logic inversion. Data determination unit to. 2. An edge selecting means comprising: a clock oscillator for generating a clock having a constant frequency; a counter for counting clocks of the clock oscillator while the edge detection circuit is in an active state; And a data register group that holds the output of the decoder every time a logical inversion of an input signal sequence is detected by the edge detection circuit. Selecting means for selecting a logical inversion edge having a maximum value among outputs of the decoder stored in the data register group;
The data judging device according to claim 1, further comprising: 3. The edge selecting means includes: a clock oscillator for generating a clock having a constant frequency; a counter for counting clocks of the clock oscillator while the edge detection circuit is in an active state; A decoder that converts the value into a value that becomes maximum at a specific time and increases as the distance from the specific time increases, and a data register group that holds an output of the decoder every time a logical inversion of an input signal sequence is detected by the edge detection circuit. 2. The data judging device according to claim 1, further comprising: selecting means for selecting a minimum logical inversion edge from an output of said decoder stored in said data register group.