JP2522972B2 - Circuit for discriminating high-definition television signals - Google Patents

Description

The present invention relates to a discrimination circuit for a high-definition television (hereinafter abbreviated as HDTV) signal which is band-compressed by a multi-sampling method, and more particularly to an HDTV signal as described above. The present invention relates to a criticality discrimination circuit suitable for a dual-reception type HDTV receiver or the like that receives a signal and an NTSC signal.

(B) Conventional technology In the dual receiver type HDTV receiver as described above, it is necessary to determine whether the image receiving signal is an HDTV signal or an NTSCTV signal and switch the internal circuit according to the output of the determination. An HDTV signal discriminating circuit for such switching control is disclosed in, for example,
It is conceivable to utilize the detection output of the frame synchronization signal in the HDTV signal as disclosed in Japanese Patent Publication No. 221091 [H04N 7/13].

However, if the configuration is such that the discrimination output is generated immediately upon detection of the frame synchronization signal, malfunction due to noise or the like becomes a problem and cannot be put to practical use.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and an object of the present invention is to provide an HDTV signal discriminating circuit which can realize an accurate discriminating operation without being affected by noise. Aim.

(D) Means for Solving the Problems In the present invention, a frame pulse that is synchronized with a detection pulse generated each time a frame synchronization signal in an HDTV signal is detected and that creates a frame pulse with a slightly shorter period than the pulse A creation circuit, a gate pulse creation circuit that obtains the frame pulse to create a gate pulse that includes the detection pulse and small periods before and after the detection pulse, a gate circuit that gates and derives the detection pulse by the gate pulse, It is configured to include a counter that generates an output when a predetermined number of output pulses of the gate circuit are counted, and a circuit connection that obtains the output of the counter and generates a discrimination output of a high-definition television signal.

(E) Operation According to the above configuration, since the detection pulse of the frame synchronization signal is gated by the gate pulse created from the detection pulse of the preceding frame, noise is not erroneously counted as the detection pulse.

(F) Embodiment FIG. 1 shows an embodiment of the discrimination circuit according to the present invention. In the figure, (1) is an input terminal to which an A / D-converted HDTV signal is introduced, and (2) is to monitor a most significant digit in the HDTV signal to thereby change a frame synchronization signal in the signal. This circuit detects a frame synchronization signal, and this circuit generates one detection pulse (FIG. 2 (a)) each time the frame synchronization signal is detected once.

(4) is a first counter for generating a frame pulse in which the detection pulse (a) is applied as a reset input via an OR gate (3), and this counter counts clock pulses (CK) to determine a reset time. , An output pulse (FIG. 2 (b)) is generated after a lapse of a time (T ₁ ) slightly shorter than one frame period (T ₀ ), and the output, that is, the frame pulse (b) is output from the OR gate (3). The signal is applied as a reset input via an external device.

(6) is a second counter for counting the clock pulse (CK) and for generating a frame pulse (b) from the first counter (4) as a reset input via an OR gate (5) And
This counter has been reset for a certain period of time (T ₂ )
Output, that is, a gate pulse (FIG. 2 (c)) is generated.

(7) is an AND gate to which the gate pulse from the second counter (6) and the detection pulse (a) are inputted, and the output pulse of the AND gate (FIG. 2 (d))
However, on the one hand, it passes through a delay circuit (8) with a delay time (τ) and on the other hand passes through a direct path (9) and is input to an exclusive OR gate (10). These circuits (7) to (1)
0) constitutes a second pulse generation circuit (16),
As shown in FIG. 2 (e), two output pulses are generated from the exclusive OR gate (10) for one detection pulse (a).

In (13), the frame pulse (b) from the first counter (4) is supplied as an up input through an AND gate (11), and the output pulse (e) of the exclusive OR gate (10). Is a 4-bit up / down counter supplied as a down input, and the output of each bit is applied as each input of a 4-bit decoder (14).

The decode output (Q ₀ ) corresponding to the count “0” of the up / down counter (13) and the decode output (Q _F ) corresponding to the count “F” are provided by the AND gate (12).
The counter (13) is adapted to be applied as each other input, and the output of the most significant bit of the counter (13) is guided to the discrimination output terminal (15).

In this embodiment having such a structure, as can be seen from the above description, one frame is received at the time of receiving the HDTV signal.
One up-counting pulse (b) is input to one (11) of the AND gates (11) and (12), and two down-counting pulses (e) are input to the other (12). .
And the other AND gate (12) has a counter (1
Decode output (Q ₀ ) only when the count value of 3) is “1”
Therefore, the counter (13) alternately repeats the state of the count value "0" and "1". Therefore,
The discrimination output terminal (15) is held at the state of "0" (low level), which indicates that it is at the time of receiving the HDTV signal.

On the other hand, at times other than the time of receiving the HDTV signal (for example, at the time of receiving the NTSC signal), one (11) of the AND gates (11) and (12) has a frame pulse having a period slightly shorter than the one frame period shown in the figure. Although a pulse is input to the other (12), a pulse is not input, and the output is always "low". The up / down counter (13) counts up according to the frame pulse (b) from the AND gate (11), and when the count value becomes “F”, the AND gate (11) closes. Therefore, the count-up is stopped, and this state is maintained thereafter. Therefore, the discrimination output terminal (15) is in the state of "1" (high level) until the detection pulse (a) is generated from the frame synchronization signal detection circuit (2).

In addition, unlike the above embodiment, the AND gate (11)
The outputs of (12) can be replaced with each other and input to the up / down counter (13).

(G) Effect of the Invention According to the discrimination circuit of the present invention, the detection pulse of the frame synchronization signal is gated by the gate pulse created from the detection pulse of the preceding frame, and the detection pulse after the gate is counted by a predetermined number. Since it is sometimes determined that the signal is an HDTV signal, noise is not mistakenly determined to be the detection pulse, and therefore the HDTV signal can be accurately discriminated.

In addition, since it is configured by a combination of the counter and the logic gate, there is an advantage that it can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is an operation time chart of each part thereof. (4): First counter (frame pulse generation circuit),
(16): Second counter (gate pulse creation circuit), (1
3): Up / down counter, (14): Decoder.

Claims (1)

(57) [Claims] 1. A circuit for identifying and detecting a high-definition television signal band-compressed by a multiple sub-sampling method, wherein a detection pulse is generated each time a frame synchronization signal in the high-definition television signal is detected. A frame synchronization signal detection circuit, a frame pulse generation circuit that generates a frame pulse that is synchronized with the detection pulse and has a period slightly shorter than the pulse, and includes the detection pulse and the detection pulse and small periods before and after the detection. A gate pulse creating circuit for creating a gate pulse, a gate circuit for deriving by gated the detection pulse by the gate pulse, a counter for generating an output when a predetermined number of output pulses of the gate circuit are counted, and the counter And a circuit connection that produces a discriminant output of high-definition television signals. Discrimination circuit for quality television signals.