JP2834243B2 - Antistatic method in electron beam lithography - Google Patents

Antistatic method in electron beam lithography

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Publication number
JP2834243B2
JP2834243B2 JP33345189A JP33345189A JP2834243B2 JP 2834243 B2 JP2834243 B2 JP 2834243B2 JP 33345189 A JP33345189 A JP 33345189A JP 33345189 A JP33345189 A JP 33345189A JP 2834243 B2 JP2834243 B2 JP 2834243B2
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JP
Japan
Prior art keywords
electron beam
wafer
dielectric breakdown
insulating film
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP33345189A
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Japanese (ja)
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JPH03194915A (en
Inventor
一光 中村
博之 伊藤
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Hitachi Ltd
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Hitachi Ltd
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Publication of JPH03194915A publication Critical patent/JPH03194915A/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子線描画に係り、更に詳細には、半導体ウ
エハ表面に電子描画を行う場合の帯電防止方法に関す
る。
Description: BACKGROUND OF THE INVENTION The present invention relates to electron beam lithography, and more particularly to an antistatic method for performing electron lithography on a semiconductor wafer surface.

〔従来の技術〕[Conventional technology]

電子線描画装置を用いて、半導体ウエハ(以下、ウエ
ハと略称する)の表面に大規模集積回路等を形成する場
合、ウエハ表面に酸化膜等の絶縁膜が被覆されている
と、アース等の配慮がなされていない場合には、電子線
描画工程時に絶縁膜を通過した電荷がウエハ内に蓄積さ
れる。このような帯電現象は、ウエハの電位に変化をき
たし電子線描画に悪影響を与え、描画パターンに位置ず
れを生じさせる原因となる。
When a large-scale integrated circuit or the like is formed on the surface of a semiconductor wafer (hereinafter abbreviated as “wafer”) using an electron beam lithography apparatus, if an insulating film such as an oxide film is coated on the surface of the wafer, a ground or the like may be formed. If care is not taken, charges that have passed through the insulating film during the electron beam drawing process are accumulated in the wafer. Such a charging phenomenon causes a change in the potential of the wafer, adversely affects electron beam drawing, and causes a position shift in a drawn pattern.

そのため、従来より帯電防止策として種々を技術が提
案されている。
Therefore, various techniques have been conventionally proposed as antistatic measures.

例えば、特開昭57−13741号公報に開示されるよう
に、ウエハの側面(周縁)の絶縁膜のみを回転研磨子等
で除去して、ウエハ側面の絶縁膜除去部分を配線を介し
てアースさせたり、 特開昭58−103135号公報に開示されるように、電子線
描画装置のステージ制御系にプラズマイオンを放射し
て、基板上に帯電した負電荷を中和したり、 特開昭61−46019号公報に開示されたりするように、
ウエハの側面部に、イオン注入した電荷導電片を圧接し
て、基板上に蓄積された電荷を除去したり、 特開昭63−90130号公報に開示されるように、電極ピ
ンと接地ピンをウエハの表面絶縁膜に弾性部材の力で押
し付け、電子線描画を行う前に、これらのピン間で放電
を行わせて、絶縁膜を局部的に破壊し、同時に前記ピン
をウエハ表面に刺し込んでウエハをアースさせたりし
て、 電子線描画時の電荷蓄積を消去したり、低下させてい
る。
For example, as disclosed in Japanese Patent Laying-Open No. 57-13741, only the insulating film on the side surface (peripheral edge) of the wafer is removed by a rotary grinder or the like, and the portion of the insulating film removed on the side surface of the wafer is grounded via wiring. As disclosed in JP-A-58-103135, plasma ions are emitted to a stage control system of an electron beam lithography apparatus to neutralize negative charges charged on a substrate. As disclosed in JP 61-46019,
A charged conductive piece implanted with ions is pressed against a side surface of the wafer to remove charges accumulated on the substrate, or as disclosed in JP-A-63-90130, an electrode pin and a ground pin are connected to the wafer. By pressing against the surface insulating film with the force of an elastic member, before performing electron beam drawing, discharge is performed between these pins to locally destroy the insulating film and simultaneously stab the pins into the wafer surface. By grounding the wafer, charge accumulation during electron beam writing is eliminated or reduced.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

ところで、前述した従来技術は、回転研磨子や、プラ
ズマイオン発生装置や、イオン注入の電荷導電片や、放
電及びアース用のピン等の特別な器具や装置を必要とす
る。さらに、前記従来技術のうち、導電片やピン等を圧
接したり、刺し込んだりする場合には、ウエハ表面が損
傷し、損傷部分にごみ等が付着し、さらに絶縁膜が厚い
時等にウエハと導電片,ピン等とが接触不良を起こし、
アース不良が生じることもあった。
By the way, the above-mentioned prior art requires special instruments and devices such as a rotary grinder, a plasma ion generator, a charged conductive piece for ion implantation, and pins for discharging and grounding. Furthermore, in the prior art, when a conductive piece, a pin, or the like is pressed or stabbed, the wafer surface is damaged, dust or the like adheres to the damaged portion, and when the insulating film is thick, the wafer may be damaged. Causes poor contact with conductive pieces, pins, etc.
Poor grounding sometimes occurred.

本発明は、以上の点に鑑みてなされたもので、その目
的とするところは、特別な絶縁膜削除用の器具や電荷中
和装置等を必要とすることなく、しかもウエハ表面を傷
つけることなく、確実に電子線描画時の帯電現象を解消
させ、高精度な電子線描画を保証することにある。
The present invention has been made in view of the above points, and its purpose is to eliminate the need for a special device for removing an insulating film, a charge neutralizing device, and the like, and without damaging the wafer surface. Another object of the present invention is to reliably eliminate the charging phenomenon during electron beam drawing and to assure high-accuracy electron beam drawing.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的は、絶縁膜が被覆された半導体ウエハ表面に
電子ビームを照射して描画を行う電子線描画方式におい
て、 前記は導体ウエハ上の任意の箇所に電子ビームを照射
する第1のステップと、 前記第1のステップにより発生する前記半導体ウエハ
上の絶縁破壊箇所にアース用の部材を接触させる第2の
ステップを有することで達成される。
The above object is to provide an electron beam lithography system for irradiating an electron beam on a surface of a semiconductor wafer coated with an insulating film to perform drawing, wherein the first step of irradiating an arbitrary portion on the conductor wafer with the electron beam, This is achieved by including a second step of bringing a member for grounding into contact with a dielectric breakdown point on the semiconductor wafer generated in the first step.

〔作用〕[Action]

電子線描画を行うに際し、ウエハ面上の任意箇所にて
絶縁膜に予め電子ビームを照射すると、局所的な帯電現
象が発生する。ウエハに被覆された絶縁膜のうち、ウエ
ハ周縁(側面)にある絶縁膜は、被覆構造が比較的不完
全となりその膜厚が他の部分より薄くなっている。
When performing electron beam lithography, if an insulating film is previously irradiated with an electron beam at an arbitrary position on a wafer surface, a local charging phenomenon occurs. Among the insulating films coated on the wafer, the insulating film on the peripheral edge (side surface) of the wafer has a relatively incomplete coating structure and is thinner than other portions.

従って、電子線描画に際して、予めウエハの絶縁膜に
局部的な帯電現像を発生させると、ウエハ周縁とこれに
隣接するウエハ保持具との間で放電が生じ、ウエハ周縁
に絶縁破壊が発生する。
Therefore, when local electrification and development are generated in advance on the insulating film of the wafer at the time of electron beam writing, a discharge occurs between the peripheral edge of the wafer and the wafer holder adjacent thereto, and dielectric breakdown occurs on the peripheral edge of the wafer.

そして、この絶縁破壊部を介してウエハとウエハ保持
具(アース用部材)が接触することで、ウエハがアース
され、その後に電子線描画を実行した場合には、ウエハ
表面が常に同電位に保たれて、良好な電子線描画を行い
得る。
Then, the wafer is grounded by the contact between the wafer and the wafer holder (earth member) via the dielectric breakdown portion, and thereafter, when electron beam drawing is performed, the wafer surface is always kept at the same potential. It is possible to perform good electron beam writing.

〔実施例〕〔Example〕

本発明の実施例を図面により説明する。 An embodiment of the present invention will be described with reference to the drawings.

第1図は、本発明の帯電防止の一例を示す説明図、第
2図は、第1図の縦断面図、第3図は、本発明の適用対
象となる電子線描画装置のシステム構成図、第4図は、
そのフローチャートを示す。
FIG. 1 is an explanatory view showing an example of antistatic of the present invention, FIG. 2 is a longitudinal sectional view of FIG. 1, and FIG. 3 is a system configuration diagram of an electron beam drawing apparatus to which the present invention is applied. , FIG.
The flowchart is shown.

まず、第3図により電子線描画装置の全体構成につい
て説明する。
First, the overall configuration of the electron beam drawing apparatus will be described with reference to FIG.

第3図において、1は電子銃、2は絞り、3は収束用
の電子レンズ(第1レンズ)、4はブランキング電極、
5は絞り、6は収束用の電子レンズ(第2レンズ)、7
は偏向器、8はマーク検出用の反射電子検出器、9はウ
エハ、10はステージである。
In FIG. 3, 1 is an electron gun, 2 is an aperture, 3 is an electron lens for focusing (first lens), 4 is a blanking electrode,
5 is an aperture, 6 is a convergence electron lens (second lens), 7
Is a deflector, 8 is a backscattered electron detector for detecting a mark, 9 is a wafer, and 10 is a stage.

電子銃1から出力される電子ビームは、第1,第2のレ
ンズ3,6及び絞り2,5により所望の形状に制御され、偏向
器7で所定の描画パターン信号に基づき偏向制御されて
ウエハ9表面に照射される。16は偏向制御系である。
The electron beam output from the electron gun 1 is controlled to a desired shape by the first and second lenses 3 and 6 and the apertures 2 and 5, and is deflected by the deflector 7 based on a predetermined drawing pattern signal. 9 Irradiated on the surface. Reference numeral 16 denotes a deflection control system.

偏向器7で電子ビームが偏向される領域は、約3mmと
精度面からの制約がある。おのため、ウエハ9全面に所
定の描画パターンを形成するには、被描画領域ごとに、
レーザ測長器11,レーザ制御系13,サーボ制御系12を用い
てステージ10を移動させ、ウエハ上に配設されるマーク
を反射電子検出器8及びマーク検出系15を用いて検出し
て、高精度のウエハ位置決めを行う。
The area where the electron beam is deflected by the deflector 7 is about 3 mm, which is limited by accuracy. In order to form a predetermined drawing pattern on the entire surface of the wafer 9, for each drawing area,
The stage 10 is moved by using the laser length measuring device 11, the laser control system 13, and the servo control system 12, and the mark disposed on the wafer is detected by using the reflected electron detector 8 and the mark detection system 15, Performs highly accurate wafer positioning.

16は電子線描画装置のシステム全体をプログラム制御
するためのコンピュータ、17はブランカ制御系である。
16 is a computer for program-controlling the whole system of the electron beam lithography system, and 17 is a blanker control system.

次に本発明に係る帯電防止法の具体例について、第1
図,第2図により説明する。
Next, specific examples of the antistatic method according to the present invention will be described with reference to the first example.
This will be described with reference to FIG.

20は、ウエハ9を保持するためのカセット(ウエハ保
持具)で、ステージ10に搭載される。
Reference numeral 20 denotes a cassette (wafer holder) for holding the wafer 9, which is mounted on the stage 10.

ウエハ9は、例えばシリコンよりなり、その表面に絶
面膜として酸化シリコン膜(以下、絶縁膜とする)9Aが
被覆される。絶縁膜9Aは、数μmの膜厚としてある。
The wafer 9 is made of, for example, silicon, and its surface is coated with a silicon oxide film (hereinafter, referred to as an insulating film) 9A as a masked film. The insulating film 9A has a thickness of several μm.

絶縁膜9Aは、従来の技術の項でも述べたように、電子
線描画時の電子ビームにより電荷をウエハ面上に蓄積
(帯電)させて、パターンずれ等電子線描画精度に悪影
響を及ぼす原因となるため、本実施例では、次のように
して帯電防止策を講じている。
As described in the section of the prior art, the insulating film 9A causes the electron beam during electron beam writing to accumulate (charge) electric charges on the wafer surface, causing a pattern shift and other adverse effects on electron beam writing accuracy. Therefore, in this embodiment, an antistatic measure is taken as follows.

すなわち、電子線描画に際してステージを移動制御し
て、ウエハ面のうち、ウエハの製品として不用となる箇
所が電子ビームの照射位置にくるように位置決めを行
う。ここで不要箇所とは、ウエハ9を切り取った時に不
要となる箇所で、ウエハの面のうちウエハ周縁近くの部
位がこれにあたる。
In other words, the stage is controlled to move at the time of electron beam lithography, and positioning is performed so that a portion of the wafer surface that is not needed as a product of the wafer comes to the irradiation position of the electron beam. Here, the unnecessary portion is a portion that becomes unnecessary when the wafer 9 is cut out, and corresponds to a portion of the wafer surface near the wafer periphery.

次いで、前記ウエハ不要箇所に電子ビームB1を照射さ
せる。なお、第1図では、B1が絶縁破壊に使用する電子
ビーム、B2が電子線描画に使用する電子ビームとして図
示してある。
Next, the unnecessary portion of the wafer is irradiated with the electron beam B1. In FIG. 1, B1 is shown as an electron beam used for dielectric breakdown, and B2 is shown as an electron beam used for electron beam drawing.

ウエハ周縁の絶縁膜は、他の部分の膜厚よりも薄くな
る傾向があり、電子ビームB1の照射により絶縁膜9Aに局
部駅な帯電が生じると、ウエハ周縁の絶縁膜とカセット
間で放電が発生し、ウエハ周縁の絶縁膜の一部が絶縁破
壊する。
The insulating film around the wafer edge tends to be thinner than the other portions, and when the insulating film 9A is locally charged by the irradiation of the electron beam B1, a discharge is generated between the insulating film around the wafer edge and the cassette. Then, a part of the insulating film on the periphery of the wafer is broken down.

この絶縁破壊箇所にて、ウエハ9とカセット20とを接
触させれば、アースが可能となる。アース状態で電子線
描画を行えば、ウエハ表面は常に同電位に保てるので、
パターンずれのない高精度の電子線描画を実行できる。
If the wafer 9 and the cassette 20 are brought into contact with each other at this breakdown point, grounding becomes possible. If electron beam drawing is performed in the ground state, the wafer surface can always be kept at the same potential.
High-precision electron beam writing without pattern shift can be executed.

なお、電子線描画に使用する電子ビームB2は、通常は
30kvで、電流密度が1μA程度であるが、その前に実行
される絶縁破壊の電子ビームB1の電流密度をこれよりも
高くしておけば(例えば10倍程度)、絶縁破壊を速やか
に実行することができる。実験結果によれば、数μmの
酸化膜9Aがある場合、1秒以下で絶縁破壊が発生する。
The electron beam B2 used for electron beam drawing is usually
At 30 kv, the current density is about 1 μA. However, if the current density of the electron beam B1 for the dielectric breakdown performed before that is set higher than this (for example, about 10 times), the dielectric breakdown is quickly performed. be able to. According to the experimental result, when there is an oxide film 9A of several μm, dielectric breakdown occurs within 1 second or less.

また、絶縁破壊における電子ビーム照射の制御として
は、時間管理により行うか、或いはカセット20とアース
の間に電流計を接続し、絶縁破壊を電流計測で検知し
て、ビーム照射を終了させれば、合理的である。
In addition, as for the control of the electron beam irradiation in the dielectric breakdown, time control is performed, or if an ammeter is connected between the cassette 20 and the ground, the dielectric breakdown is detected by the current measurement, and the beam irradiation is terminated. , Is reasonable.

第4図は、電子線描画の作業工程を示すフローチャー
トで、ステップS1〜S5までが前記絶縁破壊工程を示し、
ステップS6〜S9までが電子線描画工程を示している。
FIG. 4 is a flowchart showing an operation process of electron beam drawing, wherein steps S1 to S5 show the dielectric breakdown process,
Steps S6 to S9 show the electron beam drawing process.

〔発明の効果〕〔The invention's effect〕

本発明によれば、電子線描画に使用する電子ビームを
用いて、描画の工程前にウエハの不要箇所に絶縁破壊を
発生させるといった方法により、ウエハをアースさせる
ので、特別な器具や装置を用いることなく、電子線描画
における帯電防止を図り得る。また、このような絶縁破
壊に要する時間は、極めて短時間で確実に行うことがで
き、しかも、ウエハ表面に傷をつけることなく実行でき
る。
According to the present invention, the wafer is grounded by using an electron beam used for electron beam lithography and a method of causing dielectric breakdown at an unnecessary portion of the wafer before the drawing process, so that a special tool or device is used. Without this, it is possible to prevent electrification in electron beam lithography. Further, the time required for such dielectric breakdown can be ensured in an extremely short time, and can be performed without damaging the wafer surface.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、本発明の帯電防止の一例を示す説明図、第2
図は、第1図の縦断面図、第3図は、本発明の適用対象
となる電子線描画装置のシステム構成図、第4図は、そ
のフローチャートである。 B1……絶縁破壊用電子ビーム、B2……電子線描画用電子
ビーム、9……半導体ウエハ、9A……絶縁膜、20……ウ
エハ保持具(カセット)。
FIG. 1 is an explanatory view showing an example of antistatic of the present invention, FIG.
1 is a longitudinal sectional view of FIG. 1, FIG. 3 is a system configuration diagram of an electron beam drawing apparatus to which the present invention is applied, and FIG. 4 is a flowchart thereof. B1 ... Electron beam for dielectric breakdown, B2 ... Electron beam for electron beam drawing, 9 ... Semiconductor wafer, 9A ... Insulating film, 20 ... Wafer holder (cassette).

フロントページの続き (56)参考文献 特開 昭57−193030(JP,A) 特開 昭58−31527(JP,A) 特開 昭57−13741(JP,A) 特開 平2−143430(JP,A) 特開 昭60−74521(JP,A) 特開 昭54−64477(JP,A) 特開 平3−166714(JP,A) 特開 平3−30416(JP,A) 特開 昭58−103135(JP,A) 特開 昭58−86727(JP,A) 特開 平2−237132(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/027Continuation of the front page (56) References JP-A-57-193030 (JP, A) JP-A-58-31527 (JP, A) JP-A-57-13741 (JP, A) JP-A-2-143430 (JP) JP-A-60-74521 (JP, A) JP-A-54-64477 (JP, A) JP-A-3-166714 (JP, A) JP-A-3-30416 (JP, A) 58-103135 (JP, A) JP-A-58-86727 (JP, A) JP-A-2-237132 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/027

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁膜が被覆された半導体ウエハ表面に電
子ビームを照射して描画を行う電子線描画方式におい
て、 前記半導体ウエハ上の任意の箇所に電子ビームを照射す
る第1のステップと、 前記第1のステップにより発生する前記半導体ウエハ上
の絶縁破壊箇所にアース用の部材を接触させる第2のス
テップを有することを特徴とする電子線描画における帯
電防止方法。
1. An electron beam lithography system for irradiating an electron beam onto a surface of a semiconductor wafer coated with an insulating film to perform drawing, wherein a first step of irradiating an arbitrary portion on the semiconductor wafer with an electron beam; 2. A method for preventing electrification in electron beam lithography, comprising a second step of bringing a member for grounding into contact with a dielectric breakdown location on the semiconductor wafer generated in the first step.
【請求項2】第1請求項において、前記絶縁破壊のため
の電子ビームは、電子線描画時に使用する電子ビームよ
りも電流密度を高くする電子線描画における帯電防止方
法。
2. A method according to claim 1, wherein said electron beam for dielectric breakdown has a higher current density than an electron beam used for electron beam drawing.
【請求項3】第1請求項又は第2請求項において、前記
絶縁破壊のための電子ビーム照射は、時間管理により行
うか、或いは半導体ウエハ保持具とアースの間の電流計
を接続して、電流計測で絶縁破壊を検知した時にビーム
照射を終了させる電子線描画における帯電防止方法。
3. The method according to claim 1, wherein the irradiation of the electron beam for the dielectric breakdown is performed by time management or by connecting an ammeter between the semiconductor wafer holder and the ground. An antistatic method in electron beam lithography that terminates beam irradiation when dielectric breakdown is detected by current measurement.
JP33345189A 1989-12-22 1989-12-22 Antistatic method in electron beam lithography Expired - Lifetime JP2834243B2 (en)

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