JP2832637B2 - Power supply and its accessories - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device and its auxiliary devices, and more particularly to a power supply device for controlling various power supplies of an image processing apparatus and its auxiliary devices.

[Conventional technology]

Conventionally, the electric components of a copier printer, which is an image processing apparatus, include a sequence controller circuit centered on a microprocessor that controls the entire print sequence, and a DC controller.
Since various components such as a power source, an exposure power source, and a high voltage power source such as charging were independent, there was a limit to miniaturization and cost reduction.

Therefore, the above-mentioned components, that is, a microprocessor, a ROM, a RAM memory and a digital peripheral circuit, a D / A converter, a comparator, a control circuit of a power supply system, and the like are integrated on one chip, and one or a small number of printed circuit boards are integrated. There is a proposal to form above.

One of these proposals is a power control register, which performs various settings for power control. Conventionally, the register is set only when the power is turned on.

[Problems to be solved by the invention]

However, in the conventional power supply device, the output voltage is
For example, it is possible to reduce the power consumption during standby by changing the status to during copying or during standby. However, there are cases where the register value needs to be changed corresponding to the output voltage due to the characteristics of the transformer.

The present invention has been made in order to solve the problems of the conventional example as described above, and a device capable of changing a register value in accordance with an output voltage and performing optimal control has been made into a single chip.
It is an object of the present invention to provide a power supply device capable of reducing a voltage consumption according to an output voltage and an auxiliary device thereof.

[Means for solving the problem]

Therefore, in the present invention, an analog comparator that detects a DC output voltage obtained by rectifying a predetermined winding output of a converter transformer that converts a DC to an AC by driving a switching element on a primary side and compares the output with a desired value is provided. Up / down control by the output of the analog comparator
A U / D control circuit, a U / D counter that can be switched between counting up and down by an output of the U / D control circuit, and a synchronization that generates a synchronization pulse at a predetermined level in an output waveform of a predetermined winding of the converter transformer. A detection circuit, a counter that loads the value of the U / D counter at one of timings of generation of the synchronization pulse and a count-over signal generated by itself, and an output value of the counter,
A first digital comparator for comparing with a predetermined first set value; an output value of the U / D counter;
A second digital comparator for comparing the set value of the first digital comparator with the second digital comparator, and controlling the conduction timing of the switching element by the output of the first digital comparator; The up / down operation of the / D counter is limited, the desired value to be compared by the analog comparator is changed to a plurality of values at a predetermined timing, and the first and second set values are each made variable. The power supply device is characterized.

When the output value of the counter is smaller than the third set value, the third digital comparator inhibits the counter from loading the output value of the U / D counter with the output signal of the synchronization detection circuit, The desired value set in the comparator is changed to a plurality of values at a predetermined timing,
Further, the third set value for setting the load operation prohibition period is made variable.

Further, a latch circuit which can latch and read the third comparator output is added.

Each of the above-described analog comparator and U / D control circuit, U / D counter, counter, and three digital comparators, a D / A converter, and a CPU and a ROM, a RAM, and a timer for controlling the entire operation. And a circuit on a single chip.

Further, an object of the present invention is to achieve the above object by providing an auxiliary device having a step-down transformer for detecting a voltage of an AC power supply that rectifies the above power supply device and supplies DC power. .

[Action]

With the above configuration, the power supply device according to the present invention compares the detection value of the predetermined DC output voltage in the converter transformer with the desired value by the analog comparator,
The U / D control circuit switches the count up and down of the U / D counter by the output of the comparator to control the count of the U / D counter.

The counter detects the synchronization pulse generated at a predetermined level from the output waveform of the converter transformer by one of a synchronization pulse generated at a predetermined level and its own countover signal.
Load U / D counter value.

The first digital comparator compares the value of the counter with a first set value, and controls the conduction timing of a switching element that drives the primary side of the converter transformer based on the output to adjust the output to a predetermined DC output. I do.

The second digital comparator compares the value of the U / D counter with a second set value, limits the up / down operation of the U / D counter with this output, and sets the desired value and the first and second values. Change the setting values according to the instruction of the CPU.

When the output value of the counter is smaller than the third set value, the third digital comparator stops loading the counter with the output value from the U / D counter in response to the output signal of the synchronization detection circuit. At the same time, a plurality of desired values and set values are changed.

Further, a latch circuit is provided to latch the output value of the second digital comparator and read the result.

The power supply having the above configuration includes a CPU and a ROM,
It is formed on one chip together with RAM and timer.

By separately providing a step-down transformer, and as an auxiliary device for detecting the fluctuation of the AC power input to the power supply device,
Each of the set values can be set to a parameter corresponding to a change in the supply voltage.

〔Example〕

FIG. 1 is a circuit diagram of a power supply device according to a first embodiment of the present invention.
FIG. 2 is a timing chart of the power supply device shown in FIG.

The power supply device according to the present embodiment has a CPU (central processing unit), a ROM, a RAM, a timer (not shown), etc. (not shown) used for an electrophotographic copying machine, a printer, and the like.
Indicates the configuration range of the IC chip.

In the figure, what is indicated by T1 is a converter transformer. Primary winding N1 of converter transformer T1 is connected to power supply voltage _Vcc . The other end of the primary winding N1 is connected to a collector of a transistor Tr1 which is a switching element. The emitter of the transistor Tr1 is grounded, and a capacitor C1 and a diode D1 are connected between the collector and the ground. Here, the capacitor C1 resonates with the primary winding N1 to perform effective voltage conversion.
The diode D1 is for protecting the transistor Tr1.
By switching of the transistor Tr1, a desired voltage is generated in the secondary winding N2 according to the turn ratio. In the present invention, the detection winding N3 is provided. One end of the detection winding N3 is grounded, and the other end is connected to the input of the synchronization detection circuit 4. The output of the synchronization detection circuit 4 is connected to the preload terminal of the counter 3 via the gate 8 as a timing synchronization signal a1. When the signal a2 enters the preload terminal, the counter 3 is forcibly generating an underflow, and the underflow output is connected to the load terminal of the counter 3 via the load control circuit 11. In the figure, X,
Y and Z are outputs of a register (not shown) accessed from the CPU with the first, second, and third set values, respectively. W is CP
This is an analog output which is a desired value of a D / A converter (not shown) set from U.

The counter 3 is driven by an oscillation circuit (not shown) that generates a frequency sufficiently higher than the resonance frequency. Counter 3
A U / D counter 6 driven at a frequency sufficiently lower than the oscillation frequency is connected to a data input terminal for setting data input when a load signal is input. The U / D counter 6 includes an output of an analog comparator 7 which detects an output obtained by rectifying and smoothing the output of the output winding N4 of the converter transformer T1 by a diode D2 and a capacitor C3, and a comparator which is a second digital comparator described later. The count is counted up or down by a U / D control circuit 12 which generates an up / down signal and a clock from the output of the load control circuit 9 and the load control circuit 11. The output of the counter 3 is connected to comparators 2 and 10 which are first and third digital comparators. The comparator 2 which is a first digital comparator compares the counter 3 with a set value input X which is a first set value. Generate a pulse signal. The driver 1 drives the transistor Tr1 by the pulse signal.

Comparator 10 which is the third digital comparator
Turns on / off the gate 8 which compares the output value of the counter 3 with the set value Z which is the third set value and outputs the output of the synchronization detection circuit 4 to the preload terminal of the counter 3. The comparator 9 compares the output value of the U / D counter 6 with the set value Y, which is the second set value, and inputs the result to the U / D control circuit 12.

Next, the operation in the above configuration will be described with reference to the timing chart shown in FIG.

The waveform indicated by FBV indicates a flyback voltage generated in the comparator transformer T1. First, when the value of the counter 3 represented by c is larger than the set value X represented by X in the figure, the transistor Tr1 is turned on by the driving signal e of the driver 1 by the comparison of the comparator 2,
As a result, the voltage _Vcc is applied to the primary winding N1. Next, when the counter 3 counts down and becomes smaller than the set value X, the output of the comparator 2 is inverted, thereby turning off the transistor Tr1. As a result, the voltage of the converter transformer T1 and the capacitor C1 resonates, and a flyback voltage FBV as shown in the figure is generated in each winding of the converter transformer T1. The flyback voltage FBV is detected by the synchronization detection circuit 4, a detection signal a ₁ is generated at the time of falling, and a preload signal a ₂ is input to the counter 3 via the gate 8.

Counter 3 generates forcibly underflow by preload signal a _2. Even if the preload signal is not generated for some reason, the counter 3 generates an underflow when it tries to count down to 0 or less (shown in FIG. 2A). When an underflow is generated,
The load signal h is input to the counter 3 via the load control circuit 11, the output value of the U / D counter 6 is loaded to the counter 3, the transistor Tr1 is turned on again, and the above operation is repeated as one cycle.

The comparator 10 outputs the output of the counter 3 and the set value Z.
Is opened and closed. It also as a timing synchronizing pulse detection signal a ₁ by noise or the like generated by other than the desired timing, minimum OFF period (shown in Figure 2 c.), I.e., to ensure the count value X-Z Work for. This reduces the flyback voltage
The switching Tr1 is prevented from turning on before the voltage does not reach OV, and the transistor Tr1 is prevented from being destroyed. In FIG. 2, a symbol b indicates a timing synchronization signal other than the desired timing.

On the other hand, the U / D control circuit 12 generates an up / down signal and a clock from the output of the comparator 9 and the load signal h of the load control circuit 11, and outputs an output signal d and a clock signal to the U / D counter 6. This generally means that unless up / down is performed at an appropriate timing synchronized with the load signal h,
Since there is a possibility that indefinite data during the change may be loaded into the counter 3, up / down switching is performed at the rise of the load signal h, and the U / D counter 6 is driven at the fall. U / D the value of the counter 6 is greater the longer the ON time of the transformer T ₁ output voltage rises, also small and the output voltage drops. Therefore, sequentially
The count value of the U / D counter 6 is counted up. When the output voltage _Vout becomes a desired value, that is, w set in the analog comparator 7, the output of the analog comparator 7 repeats up and down.

Further, the comparator 9 regulates the upper limit of the U / D counter 6 by comparing it with a set value Y which is a second set value. This in extremely pulse period is increased, a large current flows through the transistor Tr1 and transformer T ₁ is saturated, to prevent the destruction. When the comparator 9 becomes active, the output d of the U / D control circuit 12 is forcibly set to the down mode.

As described above, during printing, the desired value w is set to a voltage (usually 24 V is often selected) supplied to components necessary for the sequence operation such as a copying machine, a relay of a printer, a solenoid, and a motor. . However,
24V is not necessarily required during standby. Rather, it is better to keep this voltage low from the viewpoint of power consumption and temperature rise of the power supply circuit. The present invention is a CPU (not shown)
By changing the desired value w set in the D / A converter (not shown) from, the output voltage can be easily varied.

However, when the output is set to a low voltage, for example, the set value Y defining the upper limit of the U / D counter 6 can be set lower than the setting during printing. Because it can be said that the set value Y specifies the maximum value of the power transmitted to the output side, the power on the output side is low at the time of low voltage, and it is not necessary that the setting be the same as during printing. Consumption of the same amount of power as during printing at low power means that some abnormality has already occurred. From the viewpoint of protecting the output side, it is necessary to keep the upper limit of the transmitted power low. In addition, when the voltage is low, the load state changes, the flyback waveform changes, and the first and third set values X and Z may need to be changed.

For this reason, the output voltage desired value w is changed to a plurality of values at a predetermined timing, and the set values of the power control register (not shown), that is, the first, second, and third set values X, Y, Z Can be prevented from being abnormally operated by changing the settings to the optimum values.

Second Embodiment FIG. 3 is a circuit diagram of a second embodiment according to the present invention. Note that the same (corresponding) components as those of the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted.

As described in the first embodiment, U /
The upper limit Y is defined by the second set value of the D counter 6,
Reaching the upper limit Y may indicate that some abnormality has occurred on the output side. Therefore, in this embodiment, a configuration is adopted in which a latch circuit 13 for latching the output of the comparator 9 and reading it from a CPU (not shown) is added. With such a configuration, the CPU can know whether the U / D counter 6 has reached the upper limit Y, and can display a message, for example. When the CPU confirms that the upper limit has been reached, the latch is cleared.

Third Embodiment FIG. 4 is a circuit diagram of a third embodiment according to the present invention. It should be noted that the first and second embodiments shown in FIGS.
The same (corresponding) components as those described above are denoted by the same reference numerals, and redundant description will be omitted.

The AC input for supplying DC power by rectifying the primary winding N1 of the converter transformer T1 described in the first embodiment is connected to another AC input.
By providing a new step-down transformer T2 for inputting the next winding N5, rectifying and smoothing the output of the secondary winding N6 of this transformer T2, taking this DC output into a CPU (not shown), and performing A / D conversion, This is an attached device of the power supply device that can detect the input voltage of the AC power supply which is the input of the present device.

Therefore, by using this detection output, it is possible to set an optimum parameter as the above-mentioned set value according to the AC power supply input voltage.

〔The invention's effect〕

As described above, according to the present invention, an analog comparator that compares an output voltage of a predetermined winding of a converter transformer with a desired value and a first digital comparator that compares the output voltage with a first set value corresponding to the desired value And a second digital comparator for comparing with the second set value, and a third digital comparator for comparing with the third set value. Voltage can be controlled.

When the output value of the counter to be compared by the third digital comparator is smaller than the third set value, loading of data is prohibited, and desired values and various set values as various parameters can be varied. To prevent the switching element from being turned on before the voltage does not reach OV, thereby preventing the destruction of the switching element. Further, the desired value and each set value can be changed at an optimal timing.

The U / D control circuit sets the second set value to, for example, an upper limit value of a desired value, and keeps the output constant until the output value of the U / D counter reaches the upper limit value. Output can be controlled.

By reading a comparison result between the output value of the U / D counter indicating the output power value of the power supply and the second set value (upper limit value), it is possible to know the occurrence state of the abnormality.

The power supply device described above can be provided as a one-chip IC.

Further, by providing the auxiliary device for detecting the voltage of the AC power supply supplied to the power supply device, it is possible to set the optimal parameters for the respective set values with respect to the desired values according to the change of the AC power input.

With the above effects, for example, as a power supply device of a copying machine, two types of output voltages during printing and during standby can be obtained.
At the same time, by changing the power control parameters to optimal values,
Low power consumption can be achieved while ensuring reliable operation, and the reliability of the circuit can be improved by reducing the amount of heat generation.

[Brief description of the drawings]

1 is a circuit diagram of a power supply device according to a first embodiment of the present invention, FIG. 2 is a timing diagram of the power supply device shown in FIG. 1, FIG. 3 is a circuit diagram of a second embodiment according to the present invention, and FIG. FIG. 11 is a circuit diagram of the third embodiment. In the drawings, the same reference numerals indicate the same (corresponding) components. 2 First digital comparator 3 Counter 4 Synchronization detection circuit 6 U / D counter 7 Analog comparator 9 Second digital comparator 10 Third digital comparator 12 U / D control circuit 13 Latch circuit T ₁ Converter transformer T ₂ Step-down transformer Tr 1 Switching element (switching transistor) A IC chip X First set value input Y Second Setting value input Z... Third setting value input w... Desired value input In the drawings, the same or corresponding parts are represented by the same reference numerals.

Claims (5)

(57) [Claims] 1. An analog comparator for detecting a DC output voltage obtained by rectifying a predetermined winding output of a converter transformer for converting a DC to an AC by driving a switching element on a primary side and comparing the output with a desired value; A U / D control circuit for up / down control by an output of a comparator;
A U / D counter that can be switched between count-up and count-down by an output of the / D control circuit, a synchronization detection circuit that generates a synchronization pulse at a predetermined level in an output waveform of a predetermined winding of the converter transformer, and a generation of the synchronization pulse. A counter for loading the value of the U / D counter at one of a timing and a count-over signal generated by itself, and a first comparing an output value of the counter with a predetermined first set value. Digital comparator and the U / D
A second digital comparator for comparing an output value of the counter with a predetermined second set value; controlling a conduction timing of the switching element by an output of the first digital comparator; 2
The output of the digital comparator limits the up / down operation of the U / D counter, changes the desired value to be compared by the analog comparator to a plurality of values at a predetermined timing, and performs the first and second operations. A power supply device, wherein a set value of a digital comparator is made variable. And a third digital comparator for prohibiting the counter from loading the output value of the U / D counter into the counter by an output signal of the synchronization detecting circuit when the output value of the counter is smaller than the third set value. 2. The power supply device according to claim 1, wherein the desired value is changed to a plurality of values at a predetermined timing, and the third set values for setting the load operation prohibition period are respectively changed. 3. A circuit according to claim 1, further comprising a latch circuit for latching and reading the output of the second comparator.
The power supply as described. 4. The analog comparator according to claim 1,
D control circuit, U / D counter, counter, synchronization detection circuit, 3
A power supply device comprising, on a single chip, each of a plurality of digital comparators and a digital circuit of a CPU, a ROM, a RAM, and a timer for controlling the entire operation. 5. An auxiliary device according to claim 1, further comprising a step-down transformer for detecting a voltage of an AC power supply for rectifying and supplying DC power.