JP2830737B2 - Lead frame with bus bar and semiconductor device - Google Patents

Lead frame with bus bar and semiconductor device

Info

Publication number
JP2830737B2
JP2830737B2 JP6091138A JP9113894A JP2830737B2 JP 2830737 B2 JP2830737 B2 JP 2830737B2 JP 6091138 A JP6091138 A JP 6091138A JP 9113894 A JP9113894 A JP 9113894A JP 2830737 B2 JP2830737 B2 JP 2830737B2
Authority
JP
Japan
Prior art keywords
bus bar
burr
lead
lead frame
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6091138A
Other languages
Japanese (ja)
Other versions
JPH07297346A (en
Inventor
篤 大高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP6091138A priority Critical patent/JP2830737B2/en
Publication of JPH07297346A publication Critical patent/JPH07297346A/en
Application granted granted Critical
Publication of JP2830737B2 publication Critical patent/JP2830737B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はバスバー付リードフレー
ムおよび半導体装置に係り、特にボンディングワイヤの
バスバーとの接触事故をなくすようにしたものに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame with a bus bar and a semiconductor device, and more particularly to a device for preventing a bonding wire from coming into contact with a bus bar.

【0002】[0002]

【従来の技術】リードフレームのなかには、インナリー
ドの内側に電源及び接地用のバスバーを設けているバス
バー付リードフレームがある。
2. Description of the Related Art Among lead frames, there is a lead frame with a bus bar in which power and ground bus bars are provided inside inner leads.

【0003】通常、このバスバー付リードフレームをプ
レスで打ち抜き加工する場合、切口面はパンチ側がだれ
込み、ダイ側にバリが生じる。そこで、ボンディングエ
リアの平坦度を確保するために、図3に示すように、イ
ンナリード2のボンディングエリア面2aをだれ込み6
のないバリ側に取ることが多い。その場合、当然プレス
の打抜き方向がインナリード2およびバスバー1で一定
なので、バスバー1もインナリード2と同じ側にバリ
7、だれ込み6の生じる断面形状となる。
Usually, when this lead frame with a bus bar is punched by a press, the cut surface is dripped on the punch side and burrs are generated on the die side. Therefore, in order to ensure the flatness of the bonding area, as shown in FIG.
It is often taken on the burr side without any. In this case, since the pressing direction of the press is naturally constant between the inner lead 2 and the bus bar 1, the bus bar 1 also has a cross-sectional shape in which burrs 7 and drooping 6 occur on the same side as the inner lead 2.

【0004】このようにインナリード2のボンディング
エリア面2aの平坦度を優先して抜き方向を決定する
と、インナリード2の上側にバリ7が来るが、バスバー
1の抜き方向も同様であるためバスバー1の上側にもバ
リ7が来る。
When the pulling direction is determined by giving priority to the flatness of the bonding area surface 2a of the inner lead 2, the burr 7 comes above the inner lead 2, but the pulling direction of the bus bar 1 is the same. The burr 7 also comes above the 1.

【0005】しかし、半導体チップ4の上に絶縁フィル
ム3を介してリードフレームを接着するLOC(Lea
d On Chip)タイプでは、インナリード2から
バスバー1を越えて半導体チップ4にボンディングワイ
ヤ5をループ状に張るので、バスバー1のバリ7が少し
でもボンディングワイヤ5と接触しただけで短絡してし
まうという不都合がある。バリを一定に管理することは
難しく、またチップ上のレジンの厚さは非常に薄く、こ
の寸法内でワイヤボンディングを行なわなれけばなら
ず、大きなループを描けないので、常に不良の要因がつ
きまとうことになる。
However, a LOC (Lea) bonding a lead frame on the semiconductor chip 4 via the insulating film 3 is used.
In the (d On Chip) type, since the bonding wire 5 is looped from the inner lead 2 to the semiconductor chip 4 over the bus bar 1, the burr 7 of the bus bar 1 is short-circuited even if it comes into contact with the bonding wire 5 even a little. There is an inconvenience. It is difficult to control burrs consistently, and the resin thickness on the chip is very thin, wire bonding must be performed within this dimension, and large loops cannot be drawn, so there is always a cause for failure Will be.

【0006】そこで、抜き方向をすべて反対にし、図4
に示すように、インナリード2の上側、及びバスバー1
の上側にだれ面が来るようにして、バスバー1のボンデ
ィングワイヤが接触し得る部分をだらすようにする。す
ると、インナリード2のボンディングエリア面にだれ込
み6がかかってしまい、この抜きだれを解消して平坦度
を出すためにインナリード2に深くコイニング部2bを
入れなければならない。
[0006] Therefore, all the pulling directions are reversed, and FIG.
, The upper side of the inner lead 2 and the bus bar 1
Of the bus bar 1 so that the portion of the bus bar 1 to which the bonding wire can come into contact is loosened. Then, a droop 6 is applied to the bonding area surface of the inner lead 2, and the coining portion 2 b must be deeply inserted into the inner lead 2 in order to eliminate the dripping and obtain a flatness.

【0007】しかし仕様上、リードに絶縁フィルムを貼
る製品であるため、リードにコイニングの段差が出来る
ことはフィルムの貼付け上好ましくなく、工程が増える
ことからも良策とは言えない。
[0007] However, due to the specification, since the product is a product in which an insulating film is attached to the lead, it is not preferable that a step of coining is formed on the lead in terms of attaching the film, and the number of steps is increased.

【0008】なお、バスバー上に絶縁材を被覆するバス
バーコート法もあるが、この方法も被覆工程が増加する
ため好ましくない。
There is also a bus bar coating method for coating an insulating material on a bus bar, but this method is also not preferable because the number of coating steps increases.

【0009】[0009]

【発明が解決しようとする課題】上述したように従来の
バスバー付リードフレームにあっては、リードの抜き方
向が一定の場合、抜き方向が正方向だとバスバーとボン
ディングワイヤとの接触による短絡事故が懸念される。
これに対して逆方向だとコイニング工程が必要となる
上、コイニングにより形成される段差はフィルム貼付け
上好ましくなかった。
As described above, in a conventional lead frame with a bus bar, if the lead is pulled out in a fixed direction, if the pulling out direction is a positive direction, a short circuit accident occurs due to the contact between the bus bar and the bonding wire. Is concerned.
On the other hand, if the direction is reversed, a coining step is required, and the step formed by coining is not preferable in attaching the film.

【0010】本発明の目的は、前記した従来技術の欠点
を解消し、ワイヤボンディング時に短絡事故のないバス
バー付リードフレームおよび半導体装置を提供すること
にある。
It is an object of the present invention to provide a lead frame with a bus bar and a semiconductor device which eliminates the above-mentioned drawbacks of the prior art and does not cause a short circuit accident during wire bonding.

【0011】[0011]

【課題を解決するための手段】本発明のバスバー付リー
ドフレームは、インナリードのバリの出る方向と、バス
バーのバリの出る方向とが逆になるようにプレス加工さ
れたものである。
The lead frame with a bus bar according to the present invention is formed by press working so that the direction in which the burrs of the inner leads come out and the direction in which the burrs of the bus bar come out are opposite.

【0012】また、本発明の半導体装置は、インナリー
ドのバリの出る方向と、バスバーのバリの出る方向とが
逆になるようにプレス加工されたバスバー付リードフレ
ームと、上記バスバー付リードフレームに、そのインナ
リードのバリの出る面を上にし、バスバーのバリの出る
面を下にして、絶縁フィルムを介して接着された半導体
チップと、該半導体チップとインナリードとをバスバー
を越えてワイヤボンドするボンディングワイヤとを備え
たものである。
Further, the semiconductor device according to the present invention includes a lead frame with a bus bar which is pressed so that a direction in which burrs of inner leads protrude and a direction in which burrs of bus bars protrude are opposite to each other. With the burr of the inner lead facing up and the burr of the bus bar facing down, the semiconductor chip bonded via an insulating film and the semiconductor chip and the inner lead are wire-bonded over the bus bar. And a bonding wire.

【0013】[0013]

【作用】打抜き方向を一部異にして、インナリードのバ
リの出る方向と、バスバーのバリの出る方向とが逆にな
るようにリードフレームがプレス加工されていると、バ
スバーを越えてインナリードと半導体チップとをワイヤ
ボンディングする場合、インナリードのバリの出る面を
上にし、バスバーのバリの出る面を下にすれば、ボンデ
ィングワイヤが接近するバスバーの上面がだれ面となっ
ているので、ボンディングワイヤがバスバーに接触して
短絡することが大幅に減少する。また、インナリードの
バリの出る面が上になっているので、コイニング加工を
しなくてもボンディングエリア面に平坦面が得られる。
[Function] If the lead frame is pressed so that the burrs of the inner lead and the burrs of the bus bar are opposite to each other with the punching direction partially different, the inner lead can be moved beyond the bus bar. When wire bonding the semiconductor chip with the semiconductor chip, if the burr of the inner lead is on the top and the burr of the bus bar is on the bottom, the upper surface of the bus bar to which the bonding wire approaches is a whol surface. Short-circuiting of the bonding wire to the bus bar is greatly reduced. Further, since the surface of the inner lead from which the burr is formed is on the upper side, a flat surface can be obtained on the bonding area surface without coining.

【0014】[0014]

【実施例】以下、本発明の実施例を説明する。図1は半
導体チップ上に搭載されたバスバー付リードフレームの
要部断面図を示す。このバスバー付リードフレームは、
信号用リードを構成するインナリード2の内側に、さら
に電源及び接地用のバスバーを1設けている。その形成
に当ってはプレス加工法が採用されるが、バスバー1
と、インナリード2を含むその他のリードとは、そのプ
レス打抜き方向を変えてある。
Embodiments of the present invention will be described below. FIG. 1 is a sectional view of a main part of a lead frame with a bus bar mounted on a semiconductor chip. This lead frame with busbar is
Inside the inner lead 2 constituting the signal lead, a bus bar for power supply and ground is further provided. A press working method is adopted in forming the bus bar 1
And the other leads including the inner lead 2 have different press punching directions.

【0015】インナリード2を抜くときは通常の正方向
打ち抜きで行い、バスバー1を形成する抜きのみ逆抜き
方向でプレスする。すると、図1のように、バスバー付
リードフレームとして、インナリード2のバリ7の出る
方向と、バスバー1のバリ7の出る方向とが逆になる断
面形状が得られる。
When the inner lead 2 is to be pulled out, normal punching in the normal direction is performed, and only the punching for forming the bus bar 1 is pressed in the reverse punching direction. Then, as shown in FIG. 1, a cross-sectional shape in which the direction in which the burrs 7 of the inner leads 2 protrude and the direction in which the burrs 7 of the bus bar 1 protrude is obtained as a lead frame with a bus bar.

【0016】逆抜きを行なうためには、金型を構成する
下型にパンチを立て、上型のストッパにダイを組み込ん
で一部金型を逆構造にする。その他は通常通りの型構造
とする。
In order to perform reverse punching, a punch is erected on a lower die constituting a die, and a die is incorporated into a stopper of the upper die to partially reverse the die. Others have the usual mold structure.

【0017】そして、図2に示すように、リードフレー
ム材をプレス打抜きする際、抜きの板取りとしては、ま
ずバスバー1を除くインナリード2等の周りの打抜き形
状部分8を正抜きして、インナリード2等を形成する
(図2(a))。このときインナリード2等は側面のみ
ならず先端面も抜くが、バスバー1となるべき部分につ
いてはバスバーより広めに残しておく。次いでバスバー
1の両脇の打抜き形状部分9を逆抜する(図2
(b))。なお、リードとバスバーとを逆の順序で抜い
てもよい。このように順次抜きを入れると、最終的に図
2(c)に示すバスバー付リードフレーム製品が得られ
る。
Then, as shown in FIG. 2, when the lead frame material is press-punched, first, a punched shape portion 8 around the inner lead 2 and the like except for the bus bar 1 is punched out. The inner leads 2 and the like are formed (FIG. 2A). At this time, not only the side surface but also the tip surface of the inner lead 2 and the like are removed, but the portion to be the bus bar 1 is left wider than the bus bar. Next, the punched portions 9 on both sides of the bus bar 1 are reversely punched (FIG. 2).
(B)). Note that the lead and the bus bar may be pulled out in reverse order. By sequentially removing the lead frames, a lead frame product with a bus bar shown in FIG. 2C is finally obtained.

【0018】本実施例では、バスバー1についてパンチ
を下から入れているため、バスバーは図1に示すように
逆の断面形状となる。リードフレームは製品の使い勝手
上、どちらを上に向けることもできるが、逆抜きとした
バスバー1を、上側にだれ込み6をもつダレ面が、下側
にバリ7をもつバリ面が来るように向ける。すると、正
抜きとしたインナリード2は、バリ7の出る方向が上側
となり、だれ込み6が来るだれ面が下側になる。
In this embodiment, since the punch is inserted from below the bus bar 1, the bus bar has an inverted cross-sectional shape as shown in FIG. Either of the lead frames can be turned upward for ease of use of the product. However, the bus bar 1 that has been drawn upside down should be so that the sagged surface with the sag 6 on the upper side and the burr surface with the burr 7 on the lower side come. Turn. Then, in the inner lead 2 that has been positively removed, the direction in which the burr 7 comes out is on the upper side, and the surface on which the burr 6 comes is on the lower side.

【0019】この状態のリードフレームを、絶縁フィル
ム3を介して半導体チップ4に接着する。そして、半導
体チップ4のボンディングパッドとインナリード2とを
バスバー1を越えてワイヤボンディングすると、ボンデ
ィングワイヤ5が最も接近するバスバー1の上面のエッ
ジにバリが来ないようにしてあるので、ボンディングワ
イヤ5とバスバー1との距離を大きく取ることができ、
ボンディングワイヤ5がバスバー1に接触して短絡する
ことが大幅に減少する。また、インナリード2のボンデ
ィングエリア面は平坦なバリ面となっているので、ボン
ディングエリア面の平坦度をコイニングを深く入れなく
ても確保できる。コイニング工程もバスバーコーティン
グも必要なくなるので作業性が向上する。
The lead frame in this state is bonded to the semiconductor chip 4 via the insulating film 3. When the bonding pad of the semiconductor chip 4 and the inner lead 2 are wire-bonded beyond the bus bar 1, no burrs come to the upper edge of the bus bar 1 where the bonding wire 5 comes closest. And the distance between the bus bar 1 and the
The short-circuit of the bonding wire 5 coming into contact with the bus bar 1 is greatly reduced. Further, since the bonding area surface of the inner lead 2 is a flat burr surface, the flatness of the bonding area surface can be ensured without deeply coining. Since no coining step and no bus bar coating are required, workability is improved.

【0020】[0020]

【発明の効果】本発明によれば、インナリードのバリの
出る方向と、バスバーのバリの出る方向とが逆になるよ
うにプレスしてあるので、インナリードのバリ面を上
に、バスバーのだれ面を下にすれば、コイニングをいれ
なくてもインナリードのボンディングエリア面の平坦度
が確保でき、かつバスバーのエッジがだれることによっ
てボンディングワイヤとバスバーとの短絡の危険を有効
に回避できる。
According to the present invention, since the direction in which the burrs of the inner leads come out and the direction in which the burrs of the bus bars come out are reversed, the burr surface of the inner leads is placed upward, and If the surface is lowered, the flatness of the inner lead bonding area surface can be secured without coining, and the risk of short-circuiting between the bonding wire and the bus bar due to the drooping edge of the bus bar can be effectively avoided. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のバスバー付リードフレームおよび半導
体装置の実施例を説明するためのインナリードとバスバ
ーの断面図である。
FIG. 1 is a sectional view of an inner lead and a bus bar for describing an embodiment of a lead frame with a bus bar and a semiconductor device according to the present invention.

【図2】本実施例に係るリードおよびバスバーを形成す
る抜き形状の板取り図である。
FIG. 2 is a plan view of a punched shape for forming a lead and a bus bar according to the present embodiment.

【図3】従来例のバリ面が共に上側にあるインナリード
とバスバーの断面図である。
FIG. 3 is a cross-sectional view of an inner lead and a bus bar, both of which have a burr surface on the upper side in a conventional example.

【図4】従来例のだれ面が共に上側にあるインナリード
とバスバーの断面図である。
FIG. 4 is a cross-sectional view of an inner lead and a bus bar, both of which have a drooping surface on the upper side in a conventional example.

【符号の説明】[Explanation of symbols]

1 バスバー 2 インナリード 3 絶縁フィルム 4 半導体チップ 5 ボンディングワイヤ 6 だれ込み 7 バリ 8 正方向の打抜き形状部分 9 逆方向の打抜き形状部分 DESCRIPTION OF SYMBOLS 1 Bus bar 2 Inner lead 3 Insulating film 4 Semiconductor chip 5 Bonding wire 6 Burr 7 Burr 8 Forward punched part 9 Reverse punched part

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 23/50 H01L 21/60 301──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/50 H01L 21/60 301

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】インナリードのバリの出る方向と、バスバ
ーのバリの出る方向とが逆になるようにプレス加工され
たことを特徴とするバスバー付リードフレーム。
1. A lead frame with a bus bar, characterized in that the lead frame is pressed so that the direction of the burr of the inner lead and the direction of the burr of the bus bar are reversed.
【請求項2】インナリードのバリの出る方向と、バスバ
ーのバリの出る方向とが逆になるようにプレス加工され
たバスバー付リードフレームと、上記バスバー付リード
フレームに、そのインナリードのバリの出る面を上に
し、バスバーのバリの出る面を下にして、絶縁フィルム
を介して接着された半導体チップと、該半導体チップと
インナリードとをバスバーを越えてワイヤボンディング
するボンディングワイヤとを備えたことを特徴とする半
導体装置。
2. A lead frame with a bus bar which is pressed so that the direction of the burr of the inner lead and the direction of the burr of the bus bar are opposite to each other. A semiconductor chip adhered via an insulating film, with a surface on which the burrs emerge from the surface facing up and a surface from which burrs emerge from the bottom facing down, and a bonding wire for wire bonding the semiconductor chip and the inner lead over the bus bar. A semiconductor device characterized by the above-mentioned.
JP6091138A 1994-04-28 1994-04-28 Lead frame with bus bar and semiconductor device Expired - Fee Related JP2830737B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6091138A JP2830737B2 (en) 1994-04-28 1994-04-28 Lead frame with bus bar and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6091138A JP2830737B2 (en) 1994-04-28 1994-04-28 Lead frame with bus bar and semiconductor device

Publications (2)

Publication Number Publication Date
JPH07297346A JPH07297346A (en) 1995-11-10
JP2830737B2 true JP2830737B2 (en) 1998-12-02

Family

ID=14018176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6091138A Expired - Fee Related JP2830737B2 (en) 1994-04-28 1994-04-28 Lead frame with bus bar and semiconductor device

Country Status (1)

Country Link
JP (1) JP2830737B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6260593B2 (en) 2015-08-07 2018-01-17 日亜化学工業株式会社 Lead frame, package, light emitting device, and manufacturing method thereof
JP6394634B2 (en) 2016-03-31 2018-09-26 日亜化学工業株式会社 Lead frame, package, light emitting device, and manufacturing method thereof

Also Published As

Publication number Publication date
JPH07297346A (en) 1995-11-10

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