JP2827487B2 - A / D converter - Google Patents
A / D converterInfo
- Publication number
- JP2827487B2 JP2827487B2 JP25771390A JP25771390A JP2827487B2 JP 2827487 B2 JP2827487 B2 JP 2827487B2 JP 25771390 A JP25771390 A JP 25771390A JP 25771390 A JP25771390 A JP 25771390A JP 2827487 B2 JP2827487 B2 JP 2827487B2
- Authority
- JP
- Japan
- Prior art keywords
- msec
- converter
- integration
- conversion
- bar graph
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明はA/D変換装置に関し、更に詳しくは、ディジ
タル表示とアナログバーグラフ表示を同時に行うように
構成された電子メータで用いられる２重積分型A/D変換
器の商用電源周波数ノイズに対する特性の改善に関す
る。DETAILED DESCRIPTION OF THE INVENTION <Industrial application field> The present invention relates to an A / D converter, and more particularly, to a dual-purpose A / D converter used in an electronic meter configured to simultaneously perform digital display and analog bar graph display. The present invention relates to improvement of characteristics of an integrating A / D converter with respect to commercial power frequency noise.
＜従来の技術＞ 従来から用いられてきた機械的なメータに代わるもの
として、ディジタル表示とアナログバーグラフ表示を同
時に行うように構成された電子メータが実用化されてい
る。<Related Art> As an alternative to a mechanical meter conventionally used, an electronic meter configured to simultaneously perform digital display and analog bar graph display has been put to practical use.
第２図はこのような電子メータの一例を示すブロック
図である。積分器Ｉを構成する演算増幅器１の反転入力
端子には基準電圧＋Vrefがスイッチ２及び抵抗３を介し
て入力されるとともに、基準電圧−Vref,被測定電圧Vx
及びアース電圧がスイッチ２及び抵抗４を介して入力さ
れる。該演算増幅器１の非反転入力端子はアースに接続
され、反転入力端子と出力端子の間にはコンデンサ５と
スイッチ６が並列に接続されている。該演算増幅器１の
出力端子はコンパレータを構成する演算増幅器７の反転
入力端子に接続されている。該演算増幅器７の非反転入
力端子はアースに接続され、出力端子はA/D変換器８に
接続されている。A/D変換器８の出力信号はバーグラフ
表示器９に入力されるとともに平均化回路10にも入力さ
れる。該平均化回路10の出力信号はディジタル表示器11
に入力される。FIG. 2 is a block diagram showing an example of such an electronic meter. The reference voltage + Vref is input to the inverting input terminal of the operational amplifier 1 constituting the integrator I via the switch 2 and the resistor 3, and at the same time, the reference voltage -Vref and the measured voltage Vx
And the ground voltage are input via the switch 2 and the resistor 4. The non-inverting input terminal of the operational amplifier 1 is connected to the ground, and a capacitor 5 and a switch 6 are connected in parallel between the inverting input terminal and the output terminal. An output terminal of the operational amplifier 1 is connected to an inverting input terminal of an operational amplifier 7 constituting a comparator. The non-inverting input terminal of the operational amplifier 7 is connected to the ground, and the output terminal is connected to the A / D converter 8. The output signal of the A / D converter 8 is input to a bar graph display 9 and also to an averaging circuit 10. The output signal of the averaging circuit 10 is
Is input to
第３図はこのように構成された装置の動作説明図であ
る。まず、時間t1で基準電圧−Vrefの積分を行い、続く
時間t2で基準電圧＋Vrefの逆積分を行う。この積分は積
分器のオフセットの影響を除去するために行うものであ
る。そして、所定時間経過後、時間t3で基準電圧−Vref
と被測定電圧Vxとの加算電圧の積分を行い、続く時間t4
で基準電圧＋Vrefの逆積分を行う。バーグラフ表示器９
はA/D変換器８での毎回のA/D変換結果を逐次更新しなが
ら表示する。一方、ディジタル表示器11は、A/D変換器
８での複数回のA/D変換結果を平均化回路10で平均化し
て精度を上げて表示する。FIG. 3 is an explanatory diagram of the operation of the device configured as described above. First, the integration of the reference voltage -Vref at time t 1, an inverse integration of the reference voltage + Vref at subsequent time t 2. This integration is performed to eliminate the influence of the offset of the integrator. Then, the reference voltage -Vref by after a predetermined time, the time t 3
And the measured voltage Vx are integrated, and the subsequent time t 4
Performs inverse integration of the reference voltage + Vref. Bar graph display 9
Displays the result of each A / D conversion in the A / D converter 8 while sequentially updating the result. On the other hand, the digital display 11 averages the result of the A / D conversion performed by the A / D converter 8 a plurality of times by the averaging circuit 10 and displays the result with higher precision.
ところで、このような装置において、バーグラフ表示
の応答性を向上させるためには積分時間t1,t3を短くす
ることが考えられる。By the way, in such a device, it is conceivable to shorten the integration times t 1 and t 3 in order to improve the response of the bar graph display.
＜発明が解決しようとする課題＞ しかし、これら積分時間t1,t3を短くすると、商用電
源周波数50Hz,60Hzのノイズの影響をうけてディジタル
表示器11の指示値がふらついてしまうという問題があ
る。<Problems to be Solved by the Invention> However, when these integration times t 1 and t 3 are shortened, there is a problem that the indicated value of the digital display 11 fluctuates due to the influence of the noise of the commercial power supply frequency of 50 Hz and 60 Hz. is there.
本発明はこのような点に着目してなされたものであ
り、その目的は、商用電源周波数のノイズの影響をうけ
ることなく安定したディジタル表示がえられ、同時に高
速なバーグラフ表示も得られるA/D変換装置を提供する
ことにある。The present invention has been made in view of such a point, and an object thereof is to obtain a stable digital display without being affected by noise of a commercial power supply frequency and at the same time obtain a high-speed bar graph display. / D conversion device is provided.
＜課題を解決するための手段＞ 上記課題を解決する本発明は、 ２重積分によりA/D変換を行って毎回のA/D変換結果を
バーグラフ表示し、複数回のA/D変換結果を平均化して
ディジタル表示するA/D変換装置において、 前記バーグラフ表示のための積分を Ｔ［msec］（＜100msec） で行い、 前記ディジタル表示として 100［msec］/T［msec］＝ｎ（n;整数） で表されるｎ回の積分を等間隔に（ｎ−１）×100［mse
c］間で行いこれらｎ回のA/D変換結果の平均値を表示す
ることを特徴とするものである。<Means for Solving the Problems> The present invention for solving the problems described above performs A / D conversion by double integration, displays a bar graph of each A / D conversion result, and displays a plurality of A / D conversion results. In the A / D converter for averaging and digitally displaying, the integration for the bar graph display is performed at T [msec] (<100 msec), and the digital display is 100 [msec] / T [msec] = n ( n; Integer) is integrated at equal intervals into (n-1) × 100 [mse
c], and the average value of the n times of A / D conversion results is displayed.
＜作用＞ 本発明のA/D変換装置において、商用電源周波数50Hz
（周期20msec）,60Hz（周期16.7msec）からのノイズを
除去できる最小の積分時間は周期の最小公倍数である10
0msecである。従って、バーグラフ表示の高速応答性を
得るための積分時間をＴ［msec］（＜100msec）に設定
した場合、100［msec］/T［msec］＝ｎ（n;整数）回の
積分を等間隔に（ｎ−１）×100［msec］間で行いこれ
らｎ回のA/D変換結果の平均値をディジタル表示するこ
とにより、商用電源周波数からのノイズを除去できて高
精度の変換結果が得られる。<Operation> In the A / D converter of the present invention, the commercial power frequency is 50 Hz.
(Period 20 msec), the minimum integration time that can remove noise from 60 Hz (period 16.7 msec) is the least common multiple of the period 10
0 msec. Therefore, when the integration time for obtaining the high-speed response of the bar graph display is set to T [msec] (<100 msec), integration of 100 [msec] / T [msec] = n (n; integer) times is performed. By performing an interval of (n-1) × 100 [msec] and digitally displaying the average value of these n-time A / D conversion results, noise from the commercial power supply frequency can be removed, and a high-precision conversion result can be obtained. can get.
＜実施例＞ 以下、図面を参照して本発明の実施例を詳細に説明す
る。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例の動作を示す説明図であ
り、積分回数ｎ＝5,積分時間Ｔ＝20msecの場合を示して
いる。FIG. 1 is an explanatory diagram showing the operation of one embodiment of the present invention, and shows a case where the number of integrations n = 5 and the integration time T = 20 msec.
この場合、バーグラフ用の高速出力は周期80msecで得
られ、ディジタル表示用の高精度出力は５回の平均を求
めることにより400msec周期で得られる。In this case, a high-speed output for a bar graph is obtained at a period of 80 msec, and a high-precision output for a digital display is obtained at a period of 400 msec by averaging five times.
そして、積分時間Ｔは20msecで５回の積分の合計は10
0msecであり、100msecの周期で考えると互いに位相が異
なって重なり合わないため商用電源周波数50Hz,60Hzか
らのノイズ成分を除去できて高精度の変換結果が得られ
る。The integration time T is 20 msec and the total of the five integrations is 10
Since the phase is different from each other and does not overlap when considered in a cycle of 100 msec, noise components from commercial power supply frequencies of 50 Hz and 60 Hz can be removed, and a highly accurate conversion result can be obtained.
＜発明の効果＞ 以上詳細に説明したように、本発明によれば、１個の
A/D変換器で商用電源周波数のノイズの影響をうけるこ
となく安定した高分解能のディジタル表示出力が得ら
れ、同時に高速で分解能の低いバーグラフ表示も得られ
るA/D変換装置を提供できる。<Effects of the Invention> As described in detail above, according to the present invention, one
It is possible to provide an A / D converter that can obtain a stable high-resolution digital display output without being affected by the noise of the commercial power supply frequency by the A / D converter, and at the same time obtain a high-speed and low-resolution bar graph display.
第１図は本発明の一実施例の動作を示す波形図、 第２図は従来から用いられているA/D変換装置の一例を
示す構成図、 第３図は従来のA/D変換装置の動作を示す波形図であ
る。 Ｉ……積分器、1,7……演算増幅器 2,6……スイッチ、3,4……抵抗 ５……コンデンサ、８……A/D変換器 ９……バーグラフ表示器 10……平均化回路 11……ディジタル表示器FIG. 1 is a waveform diagram showing the operation of an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of a conventional A / D converter, and FIG. 3 is a conventional A / D converter. FIG. 6 is a waveform chart showing the operation of FIG. I ... Integrator, 1,7 ... Operational amplifier 2,6 ... Switch, 3,4 ... Resistance 5 ... Capacitor, 8 ... A / D converter 9 ... Bar graph display 10 ... Average Circuit 11 …… Digital display
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H03M 1/00 - 1/88 G01R 19/00──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. 6 , DB name) H03M 1/00-1/88 G01R 19/00
Claims (1)
変換結果をバーグラフ表示し、複数回のA/D変換結果を
平均化してディジタル表示するA/D変換装置において、 前記バーグラフ表示のための積分を Ｔ［msec］（＜100msec） で行い、 前記ディジタル表示として 100［msec］/T［msec］＝ｎ（n;整数） で表されるｎ回の積分を等間隔に（ｎ−１）×100［mse
c］間で行いこれらｎ回のA/D変換結果の平均値を表示す
ることを特徴とするA/D変換装置。1. A / D conversion by performing A / D conversion by double integration
In an A / D converter that displays a conversion result as a bar graph, averages a plurality of A / D conversion results, and digitally displays the result, the integration for the bar graph display is performed in T [msec] (<100 msec). In the digital display, 100 times [msec] / T [msec] = n (n; integer) n times integration is performed at regular intervals (n−1) × 100 [mse
c], and an average value of these n A / D conversion results is displayed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25771390A JP2827487B2 (en) | 1990-09-27 | 1990-09-27 | A / D converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25771390A JP2827487B2 (en) | 1990-09-27 | 1990-09-27 | A / D converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04135322A JPH04135322A (en) | 1992-05-08 |
| JP2827487B2 true JP2827487B2 (en) | 1998-11-25 |
Family
ID=17310078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25771390A Expired - Fee Related JP2827487B2 (en) | 1990-09-27 | 1990-09-27 | A / D converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2827487B2 (en) |
-
1990
- 1990-09-27 JP JP25771390A patent/JP2827487B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04135322A (en) | 1992-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2793910B2 (en) | Analog / digital converter with noise reduction effect | |
| US4357600A (en) | Multislope converter and conversion technique | |
| JPH0447269B2 (en) | ||
| JP3548887B2 (en) | Method and apparatus for measuring insulation resistance | |
| EP0693692A2 (en) | Voltage and resistance synthesizer using pulse width modulation | |
| JP2827487B2 (en) | A / D converter | |
| EP0862060A2 (en) | RMS converter using digital filtering | |
| JP3281163B2 (en) | Current measuring device and method | |
| JPS62165281A (en) | Integration circuit | |
| JPH0637341Y2 (en) | Insulation resistance tester | |
| JPS6256467B2 (en) | ||
| JPS62148882A (en) | Time measuring instrument | |
| JP3047244B2 (en) | Digital display | |
| Malarić et al. | Scaling of resistance standards in the primary electromagnetic laboratory of Croatia | |
| JP3120205B2 (en) | Period and average current measuring device | |
| JPH03274470A (en) | Power measuring apparatus | |
| JPH06324096A (en) | Universal counter | |
| JPH0348540Y2 (en) | ||
| JPH0313741Y2 (en) | ||
| JPH0426251B2 (en) | ||
| JP3221595B2 (en) | AC electricity-DC voltage converter | |
| JP3258460B2 (en) | Data output method for measuring instruments | |
| KR890004657Y1 (en) | Display circuit of analog/digital conversion | |
| JP2512362B2 (en) | Element measuring device | |
| JPH0798336A (en) | Sampling type measuring device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |