JP2823202B2 - Imaging device - Google Patents

Description

The present invention relates to an imaging device used for a television camera or the like.

(B) Conventional technology In recent years, with the improvement of semiconductor integrated circuit technology, a CCD image sensor having as many as 400,000 pixels has been developed, and as a result, a television camera which is lightweight and small and has high resolution has been realized.

Such an image sensor such as a CCD image sensor is described in detail in, for example, a book entitled "CCD Camera Technology" published by Radio Engineering Co., Ltd. (November 3, 1986).

In an imaging device such as a television camera using a CCD image sensor, various operation timings of the sensor are created based on a television synchronization signal, and the sensor is pulse-driven based on the timing.

When constructing such a drive circuit for a two-dimensional CCD image sensor, it has conventionally been desired to realize the drive circuit and the television synchronization signal circuit in a semiconductor integrated circuit device that is integrated into one chip. However, defects such as generation of beats due to the difference between the two oscillation sources and generation of vertical stripes in the reproduced image due to power supply noise due to the operation of the counter circuit, etc., have been obstacles to one chip.

The occurrence of a beat, which is one of the defects associated with the integration of the drive system circuit and the synchronization signal system circuit into one chip as described above, can be eliminated by using the same oscillation source. It is difficult to eliminate the vertical stripes in the reproduced image due to the above.

FIG. 3 shows such a conventional counter configuration. H in FIG.
The counter (11) is configured to count the source oscillation CLK with a binary counter, and when one horizontal scanning line period H is reached,
The output of the reset decoder (12) will reset the counter (11).

The second counter (13) is a counter for setting a blanking period of the horizontal scanning line period H. The output of the second counter (13) is decoded by a second decoder (14). An H blanking signal, an H synchronizing signal, a horizontal scanning line signal, and the like can be obtained from the respective outputs A, B, C,.

In the conventional circuit of FIG. 3, the first counter (11)
, The relationship between the value of each bit, its changing point, and the difference between the changing points is as shown in the table below.

As shown in the above table, the change point of the binary counter itself has periodicity, so that the amount of through current at the change point of each bit also exhibits periodicity. Therefore, as a result of the noise of the through current affecting the drive system circuit, the noise appears as vertical stripe noise in the image signal output from the CCD image sensor. or,
Due to the structure of the binary counter itself, the through current generated in the combinational circuit portion of the decoder configuration for combining the outputs of the multi-stage flip-flops increases, which leads to an increase in the amount of noise.

(C) Problems to be Solved by the Invention The present invention is to provide an imaging apparatus that can suppress generation of noise in a reproduced image even when a synchronization signal system circuit and a drive system circuit are configured as a one-chip timing IC. .

(D) Means for Solving the Problems A timing IC having a configuration in which a driving system circuit for driving an image sensor and a television synchronization signal system circuit are integrated into one chip.
In the image pickup apparatus equipped with the above, the first apparatus of the present invention is a television synchronous signal system circuit of the timing IC,
The following configuration is provided.

A non-binary counter such as a polynomial counter, a ripple counter, and a Johnson counter that counts a basic clock in an H period of the horizontal scanning line period, and a decoder that decodes a count value of the counter and generates various synchronization signals in the H period of the horizontal scanning line period.

The second device of the present invention includes a television synchronization signal circuit of the timing IC,
The following configuration is provided.

A counter that counts a basic clock in a horizontal scanning line period H period, and a decoder that operates outside the video valid period and decodes the count value of the counter to generate various synchronization signals in the horizontal scanning line period H period.

(*) Operation According to the first aspect of the present invention, since a non-binary counter such as a polynomial counter is used as the H counter of the timing IC, the change point of the counter value has no periodicity, and as a result, the reproduced image is not displayed. Noise, particularly vertical stripe noise, can be suppressed.

According to the second aspect of the present invention, since the decoder for decoding the H counter of the timing IC is operated outside the video effective period,
The decoder does not operate during the video effective period, and the operation noise of the decoder appears during this period.

(F) Embodiment FIG. 2 shows an IC configuration system of an imaging device according to the present invention.
FIG. 1 shows the configuration of the H counter employed in the device of the present invention.

In FIG. 2, (1) is a timing IC in which a television synchronizing signal generation circuit (1s) and a CCD drive timing generation circuit (1d) are formed in one chip. (2) is a CCD driver IC, (3) is a CCD image sensor, and the driver IC (2) controls the CCD image sensor (3) according to a timing signal from the CCD drive timing generation circuit (1d) of the timing IC (1). Drive. (4) is a process IC for performing signal processing such as sample hold, synchronization signal addition, and gamma correction on the image signal from the CCD image sensor (3), and outputs a video signal.

In the synchronization signal generating circuit (1s) of the timing IC (1) of the device of the present invention, instead of the H counter as shown in FIG.
The H counter illustrated in FIG. 1 is used.

That is, in FIG. 1, the H counter (15) has a configuration in which the source oscillation CLK is counted by a polynomial counter. When one horizontal scanning line period H is reached, the output of the reset decoder (16) is changed to this counter (15). Will be loaded with the initial value.

Further, the second decoder (17) decodes the count value of the polynomial counter (15) and outputs the H return signal, H synchronization signal, horizontal scan line signal, Are output. Of these outputs, a signal for identifying a video effective period, for example, an H retrace signal A is used and connected to the enable of the decoder (17), and only the operation of the decoder (17) during the H retrace period is permitted. I do. In this case, the video effective period is set to the horizontal scanning period. However, since there is an invalid period extending to 20H including the blanking period, a signal for identifying the invalid period can be used instead of the signal A described above. .

The first feature of the present invention in the configuration of the H counter shown in FIG. 1 resides in that a polynomial counter is used. The value of this counter (15), its changing point, and the difference between the changing points are different from each other. Is shown in the table below.

As is clear from the above table, the number of changing points of the polynomial counter has a gentle fluctuation and no clear periodicity. Therefore, even if there is noise of the through current at the change point,
Since this is dispersed, it cannot be vertical stripe noise, and the influence of the noise does not stand out.

Further, this polynomial counter does not require a decoder configuration that requires a large number of gates for combining the outputs of flip-flops unlike a binary counter, so that it is possible to avoid the generation of noise due to a through current in the decoder section.

In the above-described embodiment, the polynomial counter has been exemplified. However, a decoder configuration which is a combination circuit of the outputs of the multi-stage flip-flop is not required, or this is extremely small, and the cycle of the count value changes. As long as the counter has no property, a ripple counter other than a binary counter, a Johnson counter, or the like can be used.

The second feature of the present invention in the configuration of the H counter shown in FIG. 1 is that the decoder (17) is operated only outside the video effective period, so that the operation of the decoder (17) is performed. However, even if the through current causes noise, it is limited only to the horizontal blanking period or the image invalidation period including the period.

Therefore, the above-described noise does not appear in the image area of the television monitor where the image is actually displayed, and a high-quality reproduced image is obtained.

(G) Effect of the Invention As described above, the imaging apparatus of the present invention uses a polynomial counter as the H counter, or operates the decoder that decodes the output of the H counter only outside the video effective period. Therefore, even if the synchronization signal system circuit including the H counter and the driving system circuit of the image sensor are configured as a one-chip timing IC, vertical stripes or other general noise due to the H counter operation or the decoder operation can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an H counter of the imaging apparatus according to the present invention, FIG. 2 is a system configuration diagram of the imaging apparatus of the present invention, and FIG. 3 is a circuit diagram of an H counter of the conventional apparatus. (1): timing IC, (1d): CCD drive timing generation circuit, (1s): television synchronization signal, (3)
…… CCD image sensor, (15) …… H counter, (1
6) (17)… Decoder.

Claims (2)

(57) [Claims] A CCD image sensor, a driver IC for driving the image sensor, a process IC for generating a video signal from an output of the image sensor, and a timing signal for determining a drive timing of the image sensor. And a timing IC in which a synchronization signal system circuit for generating a television synchronization signal based on a basic clock is provided on a single chip, wherein the synchronization signal system circuit of the timing IC is constant. A non-binary counter such as a polynomial counter, a ripple counter, and a Johnson counter that counts a basic clock of a period; a first decoder that decodes a count value of the non-binary counter and generates various synchronization signals for each horizontal scanning period; The count value of the non-binary counter reaches a value indicating one horizontal scanning period The initializing the non-binary counter 2
An imaging apparatus comprising: 2. A CCD image sensor, a driver IC for driving the image sensor, a process IC for generating a video signal from an output of the image sensor, and a timing signal for determining a drive timing of the image sensor. And a timing IC in which a synchronization signal system circuit for generating a television synchronization signal based on a basic clock is provided on a single chip, wherein the synchronization signal system circuit of the timing IC is constant. A non-binary counter such as a polynomial counter, a ripple counter, and a Johnson counter that counts the basic clock of the cycle, and decodes the count value during a period in which the count value of the non-binary counter is a value corresponding to outside the video validity period and horizontally A first decoder for generating various synchronization signals for each scanning period; Second count value of the counter is the non-binary counter is initially set for each reaches a value that indicates one horizontal scanning period
An imaging apparatus comprising: