JP2823039B2 - Image temporary storage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temporary image storage device for temporarily storing moving image information such as television images, that is, image information for each frame.

[0002]

2. Description of the Related Art Conventionally, this type of temporary image storage device is roughly classified into a device using a medium such as a video tape for recording image information and a random access memory (hereinafter referred to as a RAM) for storing image information. ) And those using an electrical buffer.

The former is disclosed, for example, in JP-A-1-285
As disclosed in Japanese Patent Application Publication No. 068 and the like, an endless tape is used to perform recording for a fixed period, and recording can be performed for a fixed period around the tape. This is to prevent the image from being missed by performing endless recording for a certain period in advance. Further, it has been considered to immediately take out an image from the time when the user stops midway. For example, in JP-A-4-123366,
It has a large number of heads for playing video tapes, measures the indentation time, and selects the head closest to the position of the tape recorded at that time as the playback head, so that the video from the inset scene can be short I am getting in. However, when using a video tape recorder, it takes a lot of time to rewind the tape. Since a mechanical drive system is used when recording is started, a time lag is unavoidable. That is, it is difficult to extract the desired image information from the moment it comes out. In addition, it is difficult to reduce the size of the device due to the space occupied by the video tape and the mechanical mechanism for recording and reproducing the video tape.

On the other hand, when the latter electric buffer such as a RAM is used, the memory time lag is almost eliminated because of the electric time lag.

[0005]

However, when an electrical buffer such as a RAM is used, even if the image information is short, the amount of information is large.
For example, a large-capacity buffer is required to store the data in the buffer, and the apparatus becomes expensive. In addition, Japanese Unexamined Patent Publication
As described in JP-A-61859, there is an example in which the amount of information that can be stored without increasing the capacity of a buffer is increased by applying an information compression technique to reduce the amount of information, but the effect is not enough. is there.

It is an object of the present invention to provide an inexpensive image temporary storage device having a simple, small-sized structure, as well as a tape-type problem such as a time lag.

[0007]

According to the present invention, there is provided an image temporary storage device having a buffer for sequentially storing each of sequentially input image information for each frame in each buffer storage area indicated by an address. The address is generated randomly, and the image information is sequentially stored in a buffer storage area indicated by the address so as to be overwritable, while the image information stored in each buffer storage area when a request to read from the buffer is received. A buffer control means for sequentially reading out image information so as to read out the image information read immediately before in order of image information invalidated by overwriting in the order of oldest. A temporary storage device is obtained.

According to the present invention, the buffer storage area includes an image storage area for storing the image information and an IP storage area for storing IP count information indicating an IP count value indicating the storage order of the image information. The IP count information and the image information are stored as a pair, and the number of the addresses is m + 1 (m is a natural number), and the buffer control means generates a random number. An address generation circuit for randomly generating an address based on a random number and storing the image information in the image storage area of the buffer storage area indicated by the address so that the image information can be overwritten; and storing the image information in the buffer In the storage mode, an IP card that repeatedly counts up the 0th to n-th (n is a natural number satisfying n> m) IP count values An address memory circuit comprising: a counter and an address memory for sequentially storing each address from the address generation circuit as address information in the 0th to nth address storage areas provided corresponding to the IP count values; An encoder that encodes the IP count value counted up by the address memory circuit as IP count information and stores the IP count information in the IP storage area of the buffer storage area indicated by the address generated by the address generation circuit; The IP count information stored in the IP storage area of the buffer storage area indicated by the generated address is decoded to be the IP count value, and the address information stored in the address storage area indicated by the IP count value is calculated. A decoder to invalidate and read from the buffer A mode setting circuit for outputting a read request signal to the effect to the address memory circuit to set the address memory circuit to a read mode in which the image information is read from the buffer. In the method, the address information stored in each of the address storage areas corresponding to each IP count value is counted up from the IP count value when the read request signal is input, and the address information is sequentially output. The address information is sequentially input from the memory circuit, and when the address information is valid, the image information is read out from the image storage area at the address indicated by the address information, and when the address information is invalid, the immediately preceding input is performed. Reads the image information from the image storage area at the address indicated by the address information The image temporary storage device having the timing circuit for performing the above operation is obtained.

[0009] The decoder may invalidate the address information stored in the address storage area by storing specific information different from the address information in the address storage area instead of the address information. .
The mode setting circuit further includes a memory for storing an IP count value corresponding to image information to be read first in the read mode in a storage mode in advance, and a memory together with the read request signal when the read mode is started. To output the IP count value to the address memory circuit, and reset the IP counter to the IP count value. A compression circuit for compressing the sequentially input normal density image information within the frame and outputting the compressed information to the buffer; expanding the intraframe compressed image information from the buffer within the frame and outputting the same as the normal density image information And a decompression circuit that performs the processing. An analog / digital conversion circuit which digitizes analog image information which is sequentially input and outputs the digitized image information to the compression circuit; and a digital which converts digitized image information from the decompression circuit to analog and outputs the analog image information. / Analog conversion circuit.

[0010]

According to the present invention, rather than storing all of the sequentially input image information for each frame, the older the temporally out of the image information, the smaller the importance is. By performing metabolic storage in which old image information with a long time is reduced so as to be thinned out to some extent, long-term storage can be realized even with a small-capacity buffer. Of course, by using an electrical buffer such as a RAM that does not use a drive system, it is possible to start recording instantaneously. It can be played back.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A temporary image storage device according to an embodiment of the present invention will be described below with reference to the drawings. In this embodiment,
An example will be described in which the present apparatus is connected to a TV tuner and TV image information, that is, image information that is analog, normal density, and frame-by-frame is temporarily stored.

FIG. 1 is a block diagram showing an image temporary storage device according to this embodiment. In FIG. 1, an input side of an image temporary storage device 10 is connected to a tuner 30 that outputs a television image connected to an antenna 20 that converts a television wave into an electric signal. On the other hand, the output side is the display 4
Connected to 0. In the present apparatus, a video camera or the like other than the tuner may be connected to the input side, or a VTR or a personal computer for image information processing other than the display may be connected to the output side.

The image temporary storage device 10 is an analog / digital converter that digitizes and outputs analog, normal density, and frame-by-frame image information sequentially input from the tuner 30.
A digital conversion circuit (hereinafter referred to as ADC) 11 and an AD
A compression circuit 12 for compressing the image information of each frame of the normal density from C11 within the frame and outputting the compressed information, and sequentially stores the compressed image information of each frame from the compression circuit 12 in each buffer storage area indicated by the address. A buffer 13 for storing and an address are randomly generated,
While the image information is sequentially stored in the buffer storage area indicated by this address so as to be overwritable, when the request to read from the buffer 13 is received, the image information stored in the buffer storage area is overwritten in the oldest order and overwritten. Buffer control means 15 for sequentially reading out the image information so as to read out the image information read immediately before instead of the image information invalidated thereby, and a buffer 13
A decompression circuit 14 for decompressing intra-frame compressed image information for each frame and outputting it as normal density and per-frame image information, and a digitized normal density and per-frame image from the decompression circuit 14 It has a digital / analog conversion circuit (hereinafter referred to as DAC) 16 for converting information into analog and outputting it as analog, normal density, and image information for each frame.

The ADC 11 is unnecessary if the tuner 30 and the like are of a digital output type. The compression circuit 12
It is not necessary. The decompression circuit 14 includes the compression circuit 12
It is unnecessary if there is no. The DAC 16 is connected to the display 4
This is unnecessary if 0 or the like is a digital input type. Further, the ADC 11 and the DAC 16 may be configured by a personal computer.

The buffer storage area of the buffer 13 is:
As will be described later, the image storage area includes an image storage area for storing image information and an IP storage area for storing IP count information indicating an IP count value indicating a storage order of the image information.
The IP count information and the image information are stored in pairs. Further, the address is m + 1 (m is
A natural number, but in practice m is a very large number).

The buffer control means 15 includes a random number generation circuit 1
An address generation circuit 152 for randomly generating addresses sequentially based on a random number generated by 51 and storing the image information in the image storage area of the buffer storage area indicated by the address so as to be overwritable, and storing the image information in the buffer 13 In the storage mode for performing the above, an IP counter that repeatedly counts up the 0th to nth (n is a natural number satisfying n> m, but at least (n> 2 · m) is effective) IP count values And an address memory for sequentially storing each address from the address generation circuit 152 as address information in the 0th to nth address storage areas provided corresponding to each IP count value.
53 and the IP count value counted up by the address memory circuit 153 are encoded as IP count information,
Encoder 1 for storing in the IP storage area of the buffer storage area indicated by the address generated by address generation circuit 152
54 and the IP stored in the IP storage area of the buffer storage area indicated by the address generated by the address generation circuit 152.
The count information is decoded into an IP count value,
A decoder 155 for invalidating the address information stored in the address storage area indicated by the P count value, and a read request signal to read from the buffer are output to the address memory circuit 153, and the address memory circuit 153 is buffered. 13 and a mode setting circuit 156 for setting a read mode for reading image information.

In the read mode, the address memory circuit 153 counts up from an IP count value when a read request signal is input and sequentially outputs address information stored in each address storage area corresponding to each IP count value. It is.

Further, the present apparatus sequentially inputs address information from the address memory circuit, and when the address information is valid, causes the image information to be read from the image storage area of the address indicated by the address information, while the address information is invalid. In the case of (1), there is provided a timing circuit 157 for reading out the image information from the image storage area of the address indicated by the address information inputted immediately before.

FIGS. 2A to 2C show an address memory circuit 153 (its address information storage area) and a buffer 1.
3 is a diagram conceptually illustrating FIG. Hereinafter, FIG.
The method of address management in this device will be described with reference to FIGS.

First, in the storage mode, referring to FIG. 2A, the IP count value of the address memory circuit 153 is 78 now. Address information “25” indicating the address 25 generated by the address generation circuit 152 at this time is stored in the corresponding address information storage area. Address 25 generated by address generation circuit 152
Is also input to the buffer 13. However, immediately before this, the IP count information “3” is already stored in the IP storage area at the address 25 of the buffer 13 and the image information “FL3” is stored in the image storage area.

In FIG. 2B, the encoder 154
Encodes the IP count value 78 into IP count information “78” and stores it in the IP storage area of the buffer 13 indicated by the address 25 generated by the address generation circuit 152. At the same time, the image information “FL78” output from the compression circuit 12 at this time is stored in the image storage area indicated by the address 25. That is, apparently, on the old IP count information “3” and the image information “FL3”,
New IP count information “78” and image information “F”
L78 "is overwritten. At the same time (actually before overwriting), the decoder 155 sends the old IP address of the address 25 of the buffer 13 as shown in FIG.
The count information “3” is decoded into an IP count value 3, and the address information “25” stored in the address information storage area of the address memory circuit corresponding to the IP count value 3 is converted to, for example, address information “99”.
(Set in advance to mean invalidation), the address information “25” of the IP count value 3
Disable. As described above, in the storage mode, an address is randomly generated, and image information is sequentially stored in a buffer storage area indicated by the address so as to be overwritable. In the present invention, in order to invalidate the address information of the image information erased by being overwritten, the address information stored in the address information storage area is set in advance to mean invalidation as described above. In addition to rewriting to specific information, it is realized by providing an overwrite information storage area that stores overwrite information indicating whether or not overwriting has been performed so as to be paired with each address information storage area of the address memory circuit May be.

On the other hand, in the read mode, the mode setting circuit 156, which has received a read request from the user through an operation unit (not shown), outputs a read request signal for reading from the buffer 13 to the address memory circuit 153. Then, the address memory circuit 153 is set by setting the address memory circuit 153 to a reading mode for reading image information from the buffer 13. In the read mode, the address memory circuit 153 counts up from the IP count value when the read request signal is input, and sequentially outputs the address information stored in each address storage area corresponding to each IP count value. Timing circuit 15
7 sequentially inputs address information from the address memory circuit 153, and when the address information is valid (not "99"), causes the image information to be read from the image storage area of the address indicated by the address information. On the other hand, for example, FIG.
As shown in (c), the IP from the address memory circuit 153
The address information corresponding to the count value 3 is invalid (“9
9)), the image information "FL2" is read from the image storage area at the address m indicated by the immediately preceding address information "m", that is, the image information "FL2" is read again. As described above, in the read mode, the image information stored in each buffer storage area is read in the oldest order, and instead of the image information invalidated by being overwritten, the image information read immediately before is read again. Information is sequentially read.

A memory is provided in the mode setting circuit 156 for previously storing the IP count value corresponding to the image information to be read first in the read mode in the storage mode, and together with the read request signal when the read mode is started. I from memory
By outputting the P count value to the address memory circuit 153 and resetting the IP counter to the IP count value, it is possible to search and read out instantaneously.

Here, in the storage mode of the present apparatus, the relationship between the timing of storing the image information in the buffer 13 and the probability of erasing the image information will be obtained. Now, if the number of addresses in the buffer 13 is m + 1, the address is specified at random, and if the number of frames (the number of frames) of the image information stored in the buffer 13 is t, the image information of the t-th frame Is m
^t-1 / (m + 1) ^t . Figure 3 shows the probability distribution curve.
Shown in In FIG. 3, it can be seen that as the number of frames of the stored image information increases, that is, the newly stored image information has a lower probability of being erased. In other words, the older the image information, the higher the probability of erasure, and it can be said that metabolic erasure is performed. Moreover, as is apparent from the shape of the probability distribution curve, image information for a relatively short period near the oldest period is significantly erased, while image information for a relatively long period near the new period is less likely to be erased. Therefore, for a relatively long period near the new period, it is possible to read out a moving image having a normal smooth motion. On the other hand, image information for a relatively short period near the oldest period is often deleted, resulting in an image of a jumpy and jerky movement, but the entire flow can be known. In addition, if the storage mode is terminated as soon as possible at the point when the image information that needs to be read in detail in a smooth moving image is completed, the moving image state near the necessary image information is almost complete. Can be read. As described above, the present invention is more practical than, for example, a case where image information is averaged and thinned out regardless of whether the storage time is new or old.

In the present invention, it is preferable to set the IP count to a sufficiently large value. Even in this case, since the address information has a much smaller amount of information than the image information, the memory configuration in this apparatus does not become large.

[0026]

The image temporary storage device according to the present invention randomly generates an address, sequentially stores image information in a buffer storage area indicated by the address so as to be overwritable, and receives a request to read from the buffer. In this case, the image information stored in each buffer storage area is sequentially read out in an old order, and the image information read immediately before is read again instead of the image information invalidated by overwriting. Because of the buffer control means, the problems of the tape type such as time lag can be solved, and the configuration of the memories is simple, small and inexpensive.

Also, the older image information is more likely to be erased, while the newer image information is more likely to be stored in its entirety, so that smooth reading of old image information cannot be expected, but the overall flow is I understand, it can be memorized for quite a long time, and its practicality is high.

Furthermore, new image information considered to be highly necessary can be reproduced in a smooth moving image in detail. Conversely, if the storage mode is terminated when the storage of the screen information to be read out in detail is particularly completed, the image information having a high necessity can be intentionally read out as a nearly perfect moving image.

Further, it is possible to instantly search for image information to start reading and start reading.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a temporary image storage device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a storage mode by the device shown in FIG.

FIG. 3 is a probability distribution diagram showing a relationship between a storage time of image information and a probability of erasure of image information by the device shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 image temporary storage device 11 analog / digital conversion circuit (ADC) 12 compression circuit 13 buffer 14 expansion circuit 15 buffer control means 16 digital / analog conversion circuit (DAC) 20 antenna 30 tuner 40 display 151 random number generation circuit 152 address generation circuit 153 Address memory circuit 154 Encoder 155 Decoder 156 Mode setting circuit 157 Timing circuit

Claims (6)

(57) [Claims] 1. An image temporary storage device having a buffer for sequentially storing each of sequentially input image information for each frame in each buffer storage area indicated by an address, wherein said address is randomly generated, and While the image information is sequentially stored in the buffer storage area indicated by, so that the image information can be overwritten, the image information stored in each buffer storage area is overwritten in the oldest order and overwritten when a request to read from the buffer is received. What is claimed is: 1. An image temporary storage device, comprising: buffer control means for sequentially reading out image information so as to read out the image information read immediately before, instead of the invalidated image information. 2. The buffer storage area includes an image storage area for storing the image information and an IP storage area for storing IP count information indicating an IP count value indicating a storage order of the image information. Information and the image information are stored in pairs, and the number of the addresses is m + 1 (m is a natural number), and the buffer control means stores the address based on a random number generated by a random number generation circuit. An address generation circuit that randomly generates the image information in the buffer storage area indicated by the address in the image storage area so that the image information can be overwritten.
In a storage mode for storing image information in the buffer, an IP counter that repeatedly counts up the 0th to n-th (n is a natural number satisfying n> m) IP counters and corresponds to each of the IP count values An address memory circuit comprising: an address memory for sequentially storing each address from the address generation circuit as address information in the 0th to nth address storage areas provided; and the IP which counts up the address memory circuit. An encoder that encodes a count value as IP count information and stores the IP count information in the IP storage area of the buffer storage area indicated by the address generated by the address generation circuit, and the buffer storage area indicated by the address generated by the address generation circuit Decrypts the IP count information stored in the IP storage area of A decoder for invalidating the address information stored in the address storage area indicated by the IP count value, and a read request signal for reading from the buffer to the address memory circuit; A mode setting circuit for setting the address memory circuit to a read mode for reading the image information from the buffer, wherein the address memory circuit comprises:
In the read mode, the address information stored in each of the address storage areas corresponding to each IP count value is counted up from the IP count value when the read request signal is input, and is sequentially output. ,
The address information is sequentially input from the address memory circuit, and when the address information is valid, the image information is read from the image storage area at the address indicated by the address information. 2. The temporary image storage device according to claim 1, further comprising a timing circuit for reading out the image information from the image storage area at the address indicated by the input address information. 3. The invalidation of the address information stored in the address storage area by the decoder by storing specific information different from the address information in the address storage area in place of the address information. The image temporary storage device according to the above. 4. The mode setting circuit includes a memory for preliminarily storing an IP count value corresponding to image information to be read first in a read mode in a storage mode, wherein the read request is issued when the read mode is started. 4. The image temporary storage device according to claim 2, wherein an IP count value is output from the memory to the address memory circuit together with a signal, and the IP counter is reset to the IP count value. 5. A compression circuit for compressing sequentially input normal density image information in a frame and outputting the compressed information to the buffer,
5. The image temporary storage device according to claim 1, further comprising: a decompression circuit for decompressing the intra-frame compressed image information from the buffer within the frame and outputting the image information as normal density image information. 6. An analog / digital conversion circuit which digitizes analog image information which is sequentially input and outputs the digitized image information to the compression circuit, and converts the digitized image information from the decompression circuit into analog image information. 6. The image temporary storage device according to claim 5, further comprising a digital / analog conversion circuit for outputting.