JP2819668B2 - Instruction optimization method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a compiler for generating an object program for a central processing unit (hereinafter abbreviated as CPU) having a data cache. Regarding the optimization method.

[Conventional technology]

Conventionally, in this type of instruction optimization method, the hit ratio of the data cache has not been considered.

[Problems to be solved by the invention]

In the conventional instruction optimization method described above, the hit ratio of the data cache was not taken into account, so
When the data cache is frequently flushed, there is a disadvantage that the program execution time is required.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to sort load instructions in the order of operand addresses so as to increase the data cache hit rate, thereby suppressing the occurrence of a table cache flush and shortening the program execution time. An object of the present invention is to provide an instruction optimization method as described above.

[Means for solving the problem]

An instruction optimizing method according to the present invention is an instruction allocating means for inputting an instruction from an input intermediate text and allocating the instruction to a load instruction and other instructions in a data approach phase of a compiler for generating an object program of a CPU having a data cache. And a load instruction analyzing means for analyzing the load instruction distributed by the instruction distributing means and passing it to the load instruction stack means, and stacking the load instruction passed from the load instruction analyzing means in a load instruction stack area. The load instruction stack means for calling a load instruction exchange means if there is a load instruction already saved in the load instruction stack area; and a load stacked in the load instruction stack area when called from the load instruction stack means. Sort instructions by operand address A load instruction exchange means that the instruction other than the load instruction which is distributed by the instruction distributing unit, when an instruction which does not change the data cache outputs the instruction directly to output intermediate text,
If the instruction is to flush the data cache, the load instruction output means is called to output all load instructions in the load instruction stack area to the output intermediate text in the sorted order, and then execute the instruction to flush the data cache. Output to intermediate text,
If the reference instruction refers to a register to which the contents of the memory are transcribed by the load instruction in the load instruction stack area, the load instruction output means is called to operate the operand having an address smaller than the address of the operand referred to by the reference instruction. Other instruction analyzing means for outputting the reference instruction to the output intermediate text after outputting all the load instructions for transcribing to the register to the output intermediate text in the order sorted from the load instruction stack area, and the other instruction analyzing means The load instruction output means for outputting the load instructions stacked in the load instruction stack area to the output intermediate text in the sorted order when called from the load instruction stack area.

[Action]

In the instruction optimizing method of the present invention, the instruction distributing means inputs instructions from the input intermediate text and distributes them to load instructions and other instructions, and the load instruction analyzing means analyzes the load instructions distributed by the instruction distributing means. To the load instruction stack means, and the load instruction stack means stacks the load instruction passed from the load instruction analysis means on the load instruction stack area. If there is a load instruction already saved in the load instruction stack area at this time, The load instruction exchange means is called, and when the load instruction exchange means is called from the load instruction stack means, the load instructions stacked in the load instruction stack area are sorted in the order of operand addresses, and the other instruction analysis means is distributed by the instruction distribution means. An instruction other than the load instruction If there is no instruction, the instruction is output to the output intermediate text as it is, and if it is an instruction to flush the data cache, the load instruction output means is called to sort all the load instructions in the load instruction stack area. An instruction for flushing the data cache after sequentially outputting to the output intermediate text is output to the output intermediate text. If the reference instruction refers to a register to be transferred to the memory by a load instruction in the load instruction stack area, a load instruction output means Is called and the operand of the address smaller than the address of the operand referred to by the reference instruction is transferred to the register.All load instructions are output from the load instruction stack area to the output intermediate text in the order in which they are sorted, and then the reference instruction is output. And load instruction output Stage is output to the output intermediate text in the order in which they are sorted load instructions that are stacked in the load instruction stack area when called from another instruction analysis means.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a data approach phase of a compiler to which an instruction optimization method according to an embodiment of the present invention is applied. The data approach phase includes an instruction distributing means 2 for inputting an instruction from the input intermediate text 1 and distributing the instruction to a load instruction and other instructions, and a load instruction analyzing means 3 for analyzing the load instruction distributed by the instruction distributing means 2. And other instruction analyzing means 4 for analyzing an instruction other than the load instruction distributed by the instruction distributing means 2 and outputting it to the output intermediate text 5, and loading the load instruction into the load instruction stack area 9 according to the instruction from the load instruction analyzing means 3. Load instruction stack means 6 for stacking, load instruction exchange means 7 for sorting load instructions stacked in the load instruction stack area 9 in accordance with instructions from the load instruction stack area 6 in the order of operand addresses, and other instruction analysis means 4. Load instruction stack area 9 by instruction
And a load instruction output means 8 for outputting the load instructions stacked on the output intermediate text 5 in the sorted order.

The input intermediate text 1 is an intermediate text output by a code generation phase (not shown) preceding the data approach phase, and contains machine language instructions corresponding to a source program in the form of an intermediate text.

The load instruction stack area 9 is an area where a plurality of intermediate texts can be saved as they are.

Next, the operation of the instruction optimizing method of the present embodiment configured as described above will be described.

The instruction distributing means 2 classifies one machine language instruction input from the input intermediate text 1 whose operand address is resolved (this is resolved by the existing technique of the data approach phase) into a load instruction and an instruction that is not. A load instruction here is an instruction to transfer the contents of memory to a register, and the address of the operand is obtained statically at the time of translation (there is no modification by the index register or a base register whose contents change dynamically). Point to. The instruction distribution unit 2 passes the load instruction to the load instruction analysis unit 3 and passes instructions other than the load instruction to the other instruction analysis unit 4.

The load instruction analysis unit 3 analyzes the load instruction passed from the instruction distribution unit 2 and passes it to the load instruction stack unit 6. Specifically, in the load instruction analysis processing, the load instruction analysis unit 3 analyzes the relationship between the instruction and the operand, and generates an object necessary for the operation of converting a logical register into a physical register and accessing data ( The same processing is performed in the other instruction analysis means 4, but it is a general processing and will not be described).

The load instruction stacking means 6 includes the load instruction analyzing means 3
Is stacked in the load instruction stack area 9. At this time, if there is a load instruction already saved in the load instruction stack area 9, the load instruction stack means 6 calls the load instruction exchange means 7.

The load instruction exchange means 7 sorts the load instructions stacked in the load instruction stack area 9 in ascending order of operand addresses.

On the other hand, the other-instruction analysis unit 4 converts an instruction other than the load instruction passed from the instruction distribution unit 2 into an instruction that does not change the data cache, such as a branch instruction, and a base register that is modified by an index register or whose contents change dynamically. And a reference instruction which refers to a register to which the contents of the memory are transcribed by the load instruction in the load instruction stack area 9, such as a load instruction in a broad sense having the following.

When an instruction that does not change the data cache comes, the other instruction analysis means 4 outputs the instruction to the output intermediate text 5 as it is.

Further, when an instruction to flush the data cache comes, the other instruction analysis unit 4 calls the load instruction output unit 8. The load instruction output means 8 outputs all load instructions in the load instruction stack area 9 to the output intermediate text 5 in the sorted order. Thereafter, the other-instruction analyzing unit 4 outputs an instruction to flush the data cache to the output intermediate text 5.

Further, when a load instruction in the load instruction stack area 9 causes a reference instruction to refer to a register to which the contents of the memory are to be transferred, the other instruction analysis means 4 calls the load instruction output means 8. The load instruction output means 8 outputs to the output intermediate text 5 all load instructions which transfer an operand having an address smaller than the address of the operand referred to by the reference instruction to the register in the order in which the load instructions are sorted from the load instruction stack area 9. Thereafter, the other-instruction analyzer 4 outputs a reference instruction to the output intermediate text 5 that refers to the register to which the contents of the memory are transcribed by the load instruction.

Next, regarding the operation of the instruction optimization method of the present embodiment,
This will be specifically described with reference to FIG.

It is assumed that the input intermediate text 1 in FIG. 2 contains three machine language instruction texts 11, 12, and 13 in this order (the addresses of the operands are written in a resolved form. Resolution is also performed during the data approach phase). The data approach phase includes three machine language instruction texts 12 and 11 as a result of applying the instruction optimization method of the present embodiment.
And 13 are rearranged in this order and output to the output intermediate text 5.

As a result, at the time of execution of the program, when the load instruction 12 accesses the operand at the relative address of the base register BR0 at 100, the data from the relative address of the base register BR0 enters the data cache of the CPU, and the base at the next load instruction 11 Hits data stored in the data cache when accessing the operand at relative address 110 of register BR0. As a result, the flushing of the data cache is suppressed and the program is processed at a higher speed than in the case where the load instruction 11 remains preceding the load instruction 12.

[Effects of the Invention] As described above, the present invention is provided with instruction distribution means, load instruction analysis means, other instruction analysis means, load instruction stack means, load instruction exchange means and load instruction output means, and stores them in a data cache. By rearranging the load instructions in the order of the addresses of the operands so that the extracted data hits continuously, there is an effect that the flush of the data cache can be suppressed and the execution time of the program can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data approach phase to which an instruction optimization method according to an embodiment of the present invention is applied, and FIG. 2 shows an example of an application result of the instruction optimization method of the present embodiment. FIG. In the figure, 1 ... input intermediate text, 2 ... command distribution means, 3 ...
... Load instruction analysis means, 4 ... Other instruction analysis means, 5 ...
Output intermediate text, 6: load instruction stack means, 7: load instruction exchange means, 8: load instruction output means, 9: load instruction stack area, 11: load instruction,
12 ... load instruction, 13 ... reference instruction.

Claims (1)

(57) [Claims] 1. An instruction distributing means for inputting an instruction from an input intermediate text and distributing the instruction into a load instruction and other instructions in a data approach phase of a compiler which generates an object program of a CPU having a data cache. Load instruction analysis means for analyzing the load instruction distributed by the means and passing the load instruction to the load instruction stack means; and stacking the load instruction passed from the load instruction analysis means in a load instruction stack area. The load instruction stack means for calling the load instruction exchange means if there is a load instruction saved in the area, and the load instruction stacked in the load instruction stack area when called from the load instruction stack means, and the operand address. Load instruction to sort in order When an instruction other than a load instruction distributed by the exchange unit and the instruction distribution unit is an instruction that does not change the data cache, the instruction is to output the instruction as it is to the output intermediate text and flush the data cache. The load instruction output means is called to output all load instructions in the load instruction stack area to the output intermediate text in the sorted order, and then output an instruction to flush the data cache to the output intermediate text. If the reference instruction refers to a register to which the contents of the memory are transcribed by the load instruction in the instruction stack area, the load instruction output means is called, and an operand having an address smaller than the address of the operand referred to by the reference instruction is registered. All load instructions to be posted to Another instruction analyzing means for outputting the reference instruction to the output intermediate text after outputting to the output intermediate text in the order sorted from the load instruction stack area, and the load instruction when called from the other instruction analyzing means And a load instruction output unit that outputs the load instructions stacked in the stack area to the output intermediate text in the sorted order.