KR830000821B1 - Data processing systems - Google Patents

Abstract

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Description

Data processing systems

1 is a data processing system block diagram in accordance with an embodiment of the present invention.

FIG. 2 shows the element addresses used in the FIG. 1 system. FIG.

3 is a diagram showing a basic form of an instruction used in the data processing system of the present invention.

4 is a plot of the stack contents in the system of FIG. 1 when the equation E = (A + B) * (1 + B + C) * D is calculated.

5 is a block diagram of a data processing system according to another embodiment of the present invention.

6 is a table showing element addresses that may be used in the FIG. 5 system.

7 is a block diagram of a data processing system according to another embodiment of the present invention.

8 is a table showing element addresses that may be used in the FIG. 7 system.

9 is a block diagram of a data processing system according to another embodiment of the present invention.

FIG. 10 is a table showing element addresses that may be used in the FIG. 9 system. FIG.

The present invention relates to a data processing system, and more particularly, to a data processing system capable of performing logic and arithmetic operations in accordance with main memory, general purpose register files and / or data stored on a stack.

There are two types of computer architecture in a conventional data processing system: a stack device that uses a stack to perform an operation, and a register device that uses a general purpose register file to perform an operation.

The stack device has a main memory and a stack as its resources and performs operations on the stack device and / or data accumulated on the stack.

The stack has several elements, each of which is a fixed length of one word length. One of these elements is indicated by the stack pointer (SP).

The element pointed to by this SP is named Top of the Stack (TOS). Writing data from the storage to the stack or reading data from the stack into the storage can only be performed in the TOS described above in accordance with the so-called last-in first-out method (LIFO).

Operations on data accumulated on the stack can only be performed between data accumulated in the TOS and data stored in the element next to the TOS.

The register device has a main memory and a general purpose register file as its resources and performs operations based on the data accumulated in the main memory and / or the general register file.

General purpose register files also have multiple elements, each of which is one word length and one fixed length.

The characteristics of the stack and register devices are complementary to each other because of the configuration of these machines mentioned earlier.

First, the stack apparatus is advantageous in obtaining the values of calculations and logical expressions, so that the equations can be easily and effectively obtained. This is because the stack device dynamically and automatically allocates main memory so only the minimum number of places to remember is used.

Furthermore, all modern compilers in register devices, whether native or implicit, translate any operation or logical expression into reverse-polish form and then translate it into machine language. Since the reverse-pullish type exactly matches the required stack device instruction sequence, the compiler on the stack device does not need to do a secondary translation.

In contrast, the compiler in the register must do a secondary translation from the register device instruction requested from the reverse-flash type. The most appropriate time for secondary translation depends on the structure of the number of elements in the register file, making it difficult to produce machine language efficiently.

Next, the stack device does not need to reserve any reserve space for the called program and can dynamically accumulate the called program on the stack at any required moment during dynamic allocation and writing to the stack is non-destructive. Therefore, the stack device is suitable for program sequential control such as dynamic reservation of temporary area and dynamic release of temporary area, servo program call operation or interruption processing.

In contrast, a register device is not suitable for program sequential control because the register device needs to reserve an accumulation area for dynamic allocation in advance and writing to a register is destructive.

However, stack devices generally have the following disadvantages. The first disadvantage is that the number of steps to perform in the stack is greater than that in the register device.

For example, in the case where an operation of adding data A and B accumulated in the storage device is performed, the stack device requires three steps: PUSH A, PUSH B, and ADD. Register devices, on the other hand, do not require more than two levels.

In other words, LOAD A, ADD B. The second disadvantage of stack devices is that their operating speed is too slow compared to register devices.

This is because the operation on the data accumulated on the stack can be performed only between the data in the TOS and the element accumulated data next to the TOS as described above, so that the stack device is like a device having only one accumulator.

Compared to stacking devices, register devices can access any element in a general purpose register file quickly, so the automatic speed is very high compared to stacking devices.

Therefore, the proper structure for operation and address designation is not a stack device but a register device.

In the prior art, the stack device and the register device are other structures having the complementary characteristics as described above. For stack devices, there are three types of transfer commands:

And there can be one form of a binary operation such as

Here, and later, Mi and Mj are the operands of the i th and j th elements in the main memory respectively, and ↓ TOS represents a push-down operation to the stack and ↑ TOS from the stack. The point between the operands in a binary operation instruction that represents a pop-up operation means an arithmetic or logical operation.

In the register device, four types of transfer commands are as follows.

And six types of binary operation instructions as follows.

Here, hereinafter, Ri, Rj, and Rk are operands of the i, j, and k th elements of the general register file, respectively. Each device has two address format commands.

Now consider a "hybrid" device made by simply combining a stack device and a register device with the advantages of both a stack device and a register device. A "mixed" device must have three resources: a main memory, a general register file, and a stack.

In order to use these resources effectively, many commands may be required as follows. There are 12 transfer commands required.

There are 32 (8x4) binary operations as follows.

Here the "TOS" surface without arrows indicates the top of the stack when the stack is used as a conventional register without stack operation.

Thus, in a "hybrid" device that simply consists of a combination of register and stack devices, the number of instructions is more than required when used with only register devices or stack devices, such as increasing the number of storage locations for accumulating results. .

In addition, since the instruction format is address form 3 or form 2 and form 3, the mixed growth has the disadvantage of having a complicated instruction set and an increased storage area, and the size of the instruction is also increased. As a result, the data processing capacity of the "hybrid" device is low, so the "hybrid" device cannot be used practically.

The primary purpose of the present invention is to obtain a high data processing capacity of a data processing system having three resources, namely, a main memory, a general register and a stack.

Another object of the present invention is to provide a data processing system as described above in which the number of instructions is reduced and the instruction set is simplified.

Referring now to FIG. 1, the data processing system of the present embodiment includes a main memory 1 which is connected to the main bus 3 in the processing apparatus (invisible) and is a resource of the system. The system is also another resource of the system and includes a general register file 5 connected to the main bus 3.

In the embodiment of FIG. 1, the register file 5 has eight elements R ₀ -R ₇ . The system is also another resource of the system and also includes a stack 7 connected to the main bus bar 3.

The top TOS of the stack 7 corresponds to the element R _O in the general purpose register file in this embodiment and is indicated according to the stack indicator SP 9. The stack indicator 9 is controlled by a controller 21 connected to the mode designator 15 in the command register 11.

The instruction register 11 includes one instruction code, two operands and a mode designator 15. Each operand includes an address portion 13 that accumulates one element address among the elements to be accessed R ₀ -R ₇ and a mode designation 15 which specifies an unconnected or connected mode.

If a disconnected mode is specified in the operand, the contents of the stack directive 9 will not change even if the stack's TOS is accessed.

In other words, in a disconnected mode, the stack operates as an element R ₀ of the register file 5. On the other hand, if the connection mode is specified in the operand, the contents of the stack indicator 9 change when the TOS is accessed, and the stack operates as the stack itself, not as a register file.

The address 13 of the instruction register 11 is connected to a code decoder 17 which decodes the binary code from the address 13 to designate one of the elements R ₀ -R ₇ . If the decoding result by the decoder 17 designates the element R _O , the switch 19 connected between the main bus 3 and the stack 7 connects the stack 7 to the main bus 3. Activated by a signal from the decoder 17 to connect.

On the other hand, if the decryption result is to specify one of the elements R ₁ -R ₇ , then the specified element in the general register file 5 is accessed. The operation of the data processing system of FIG. 1 is as follows.

The address section 13 accumulates command addresses recorded in the machine code or intermediate code. Such instructions are common to the various embodiments described below. In the embodiment of FIG. 1, address 13 includes four bits, i.e., bit 3-bit 0, as shown in FIG. Bit 2 bit 0 specifies one of the elements R ₀ -R ₇ in the case of "0" as in bit 3 of the address.

When the value of bit 3 is " 1 ", bit 2-bit 0 designates the addressing mode for accessing main storage 1. To avoid redundant description, FIG. 2 shows the case where the value of bit 3 is "0". Claim in the case of Figure 2 the value of the bit 2-0 is "0", yongso (R ₀₎ is made, and specify that the access element (R _0), the stack indicator (9) to match the TOS of the stack to specify As a result, the TOS is actually chosen to be accessed.

In this case, the connection mode is selected when the flag "0" in the mode designation unit 15 is selected.

In the connection mode of operation, the selected TOS acts as a stack. In other words, when data is written to the TOS or when the TOS is used as a destination, the contents of the stack indicator 9 are changed to indicate the upper element following the original TOS (Figure 1), and by the stack indicator 9 The specified element becomes a new TOS.

The above operation of the stack for writing data therein is commonly called a pushdown operation. On the other hand, when the data is read from the TOS or when the TOS is used as a resource, the contents of the stack indicator 9 are changed to point to the lower element following the original TOS (Figure 1) and indicated by the stack indicator 9. Element becomes the new TOS. The above operation of the stack for reading data therefrom is usually called pop-up operation.

The disconnected mode is selected when the flag in the mode designator 15 is "1". The TOS selected with the value "0" of bit 2-0 in the disconnected mode acts as an element (R ₀ ) of the general register file with no stacking operation and thus control. 21 does not change the contents of the stack indicator 9 and writing data to the TOS is destructive.

In FIG. 2, the selected element to be accessed is one of the elements R ₁ -R ₇ if the value of bit 2-0 in the address 13 is one of " 0 "-" 111 ".

According to the data processing system embodiment shown in FIG. 1, since the TOS of the stack is matched to element R ₀ , three resources, namely main storage, general purpose register file 5 and stack 7 are two resources. That is, it can be accessed as the main memory and the general register file (5). Therefore, although three resources exist, the number of instructions required in the data processing system in this embodiment is the same as the number of instructions required in the register apparatus, as two address formats can be used as the instruction format used in this embodiment system. Equally reduced.

This effect obtained by the data processing system of FIG. 1 will be described in more detail with reference to FIGS. 3 and 4.

FIG. 3 shows the basic format of the instructions used in the present invention data processing system, in which "OP code" designates the specific operation to be performed and "Operland 1" and "Operland 2" are respectively shown in FIG. 2 is a part for designating the address of the operand.

Operation results such as the addition and subtraction specified by " OP code " are pushed down to the stack according to the present invention, whereby the reduced number of instructions and the two address formats can be realized in a non-destructive write state.

For example, in the case where an instruction such as "ADD R ₂ , R ₃ " is performed, the data processing system of FIG. 1 performs an operation "↓ TOS ← R ₂ + R ₃ ". That is, the adding and pushing down operation is executed according to a single instruction having two address types, and since the result of the operation is pushed down to the stack, the writing operation is non-destructive.

In contrast, a simple "hybrid" device that is simply a combination of a stacker and a raster device would require three commands to perform the above operation using the two address types,

PUSH R ₂ , TOS

PUSH R ₃ , TOS

ADD TOS, TOS

As such, the number of instructions will be increased to two when compared to that required by the present invention. In order to perform the operation in one command in a "hybrid" device, three address format commands will be required, such as "ADD R ₂ , R ₃ , TOS".

Now consider the operation of computing the following equation using the data processing system of FIG.

E = (A + B) * (A + B + C) * D

Where indications A, B, C, D and E are the main memory (1). Data accumulated in the general purpose register file 5 (FIG. 1) are shown.

First, the operations "ADD A, B" are performed and the result is pushed down to the TOS of the stack as shown in stem 2 of FIG.

The address to specify the TOS is R ₀ because the TOS of the stack matches the element R ₀ in the raster file 5. Therefore, the next command to be executed while the flag of the mode designator is "1" is "ADD R ₀ , C".

As a result of this operation, data A + B + C is pushed down to the stack's TOS and the preceding data A + B remains non-destructively in the lower element following the TOS as shown in step 3 of FIG. have.

The third command to be executed while the flag of the mode designation unit 15 is "0" is "MULTIPLY R ₀ , D".

As a result, data (A + B + C) that is the content of element R ₀ or the stack TOS is popped up. After the pop up operation, the state of the stack returns to the state of step 2 in FIG.

Then, the popped data A + B + C is multiplied by the data D in the processing unit (not shown), and the multiplication result is pushed down to the stack.

As a result of this operation, data A + B + C * C is present in the stack TOS and data A + B remains in the lower element following the TOS as shown in FIG.

The fourth command to be executed while the flag of the mode designation unit 15 is "0" is "MULTIPLY R ₀ , R ₀ ". As a result of this operation, the data accumulated on the stack as shown in FIG. 4, step 4 are successively popped, and the pop up data are multiplied with each other, and the multiplication result is pushed down to the TOS as shown in FIG. The last command to be executed when the local government's pollag is "0" is "MOVE R ₀ , E".

As a result of this operation, the data [(A + B) * (A + B + C) * D], the contents of the TOS, is popped up and then the element (in the general register file 5 or main memory 1) ( E) is delivered.

From the foregoing, it will be appreciated that according to the first embodiment of the present invention, the following advantages can be obtained.

(1) Operations on data accumulated in the stack, general purpose registers and / or main memory can be performed equally with a reduced number of instructions.

(2) Since there is no destructive resource at the time of writing and the stack is a temporary register, temporary accumulation operations to general registers or precious operations to general registers are not necessary during any operation, and thus have a high throughput. Red register is obtained.

(3) In this embodiment, this instruction set is simplified because only two address format instructions are required, and three address format instructions required by the conventional register apparatus are not required.

In the first embodiment, it is understood that the element R ₀ in the register file is made to conform to the TOS of the stack, but any other element can be made to conform to the TOS.

Further, in the first embodiment the general purpose register file 5 has eight elements, i.e., R ₀ -R ₇ , but more or fewer elements can be combined in the register file.

5 is a block diagram of a data processing system according to another embodiment of the present invention. The data processing system of FIG. 5 is almost similar to that of FIG. 1 so that only the mode designator 15 (FIG. 1) is not used in FIG. 5, but instead of the general register file 5 in the address 13, The difference is that the elements are configured to conform to the TOS of selection 7.

In the embodiment of FIG. 5, elements R ₁ and R ₂ are configured to conform to the TOS. If element R ₀ is specified at the abyss section 13, the decoder 17 is connected to the line " R ₀ &_quot; Decode bungee code of element (R ₀ ) to excite.

Since the excited line ("R ₀ ") is connected to the switch circuit 19 through the OR circuit, the signal decoded on the line "R ₀ " causes the main memory 1 to be stacked via the main bus 3 ( Activate the switch circuit 19 to connect 7), and at the same time the decoded signal on the line "R ₀ " is supplied to the controller 21 to control the contents of the stack indicator 9 as an operating connection mode.

On the other hand, when element R ₁ is designated at address 13, the decoded signal on line (“R ₁ ”) is also OR circuit 23 to connect main memory 1 to stack 7. The switch circuit 19 is activated through, but the contents of the stack indicator 0 are not changed since the wire ("R ₁ ") is not connected to the controller 21.

That is, in this case the disconnected mode is selected. Therefore, according to the fifth embodiment, the mode selection is performed by designating the address of the element R _O or R ₁ in the address 13.

For example, consider the following MOVE command.

MOVER ₀ , R ₃

This command means that the data accumulated in the TOS of the stack 7 is popped into the connection mode, and then the dumped data is transferred to the element R ₃ in the general register file 5. Now consider another move command:

MOVER ₁ , R ₃

These commands are TOS. This means that the accumulated data is decoded into non-destructive mode and then the decoded data is transferred to element R ₃ in register file 5.

6 is a table showing the addressing designations in the FIG. 5 system. In FIG. 6, the value of bit 3 in the address portion determines that a general purpose register (or stack) or main memory is accessed. FIG. 6 shows that the value of bit 3 is "0" as in the case of FIG. Only case is indicated.

The value of bit 2-bit 0 ("0") in address 13 designates element R ₀ which is configured to conform to the TOS as the connection mode. The value of bit 2-bit 0 ("1") specifies an element R _{1 that} is configured to conform to the TOS in a disconnected mode.

In the case of other values "10"-"111", the selected element is R ₂ -R ₇ as in the case of FIG.

Although elements R ₁ and R ₂ are made in FIG. 5 to be TOS-connected and unconnected, respectively, it should be noted that other elements can be configured to conform to TOS.

The operation of the FIG. 5 system is similar to that of the FIG. 1 system and is obvious to those working in the art. As such, detailed description of the operation of the FIG. 5 system is omitted.

7 shows a block diagram of a data processing system according to another embodiment of the present invention.

In FIG. 7, current stack indicator (CSI) 25 replaces the mode designator 15 in FIG. 1, and designates a flag that designates a connected or unconnected mode and one element considered to be the TOS of the stack. Used to accumulate street addresses.

The CSI 27 output is connected to the input of a second decoder 27 which decodes the numeric code at CSI 25. In accordance with the output signal decoded from the decoder 27, the multi-exchange device 29 couples one of the elements R ₀ -R ₇ with the TOS of the stack.

The controller 21 controls the operation of the stack indicator 9 according to the output signal from the decoder 27.

Other reference numerals used in FIG. 7 are the same as those used in FIGS. 1 and 5.

The rectangle shown in the upper part of FIG. 8 is a table which shows the structure of the current stack indicator 25. As shown in FIG. As shown in the rectangle, the CSI accumulates four bits, bits 3-bits zero.

The connection mode is specified when the value of bit 3 is "0" and the unconnected mode is specified when the value of bit 3 is "1". The value of bits 2-bit 0 in the CSI specifies one of the elements in the general register file connected to the TOS of the stack.

This mode selection and element designation will be better understood from the lower rectangle in Table 8, which indicates the TOS designation using CSI.

As can be seen from the table, the connection mode is selected when bit 3 is "0" and the unconnected mode is selected when 3 is "1". The element in the register to be connected to the TOS is specified according to the value of bits 2-bit 0.

So, for example, if the content of the CSI is "100", the element R ₄ is specified to be connected to the TOS as a connected mode and if the content of the CSI is "1010", the element R ₂ is connected to the unconnected mode. Specified to connect to the TOS.

If necessary, the CSI contents of FIG. 7 may be changed while the FIG. 7 system is operating. The benefits of having CSI by allowing any element to be connected to the TOS of the stack are as follows.

(1) High throughput of general purpose registers can be obtained. This is TOS. The elements that are configured to match are not fixed and can be freely changed while the system is running.

(a) If the system uses several elements for a particular purpose and the replacement element cannot be used for a particular purpose, any element except the special purpose element may be designated to conform to the TOS by using the CSI.

(b) If two or four operations are required in the general register and two or four consecutive elements are used for this operation, this continuity may be used for any element except CSI. Can be specified to match the TOS.

(2) A wide range of flexibility can be achieved when emulating other computers or virtual devices. That is, any stack or register device can be simply emulated by using the CSI in FIG.

9 shows a block diagram of a data system according to another embodiment of the present invention, in which there are two current stack indicators instead of CSI 25 in FIG. 7 ((SCI (1), CSI (2)). CSI (1) and CSI (2) accumulate three digits to designate the register file (5) elements, respectively, which are connected to the TOS, and the contents of these CSIs are also used while the system of FIG. Can be changed.

The CSI (1) 31 is connected to the multiple exchange device 1,35 via the decoder 33 and the CSI (2) 39 is connected to the multiple exchange device 2,37 via the decoder 41. Connected. If the contents specified in the addressing section 13 are the same as those in the CSI (1) 31, the TOS of the stack to which the designated elements of the general purpose register file 5 are connected via the central exchange unit 35 is accessed. The TOS acts as a disconnected mode.

The output of the decoder 41 is also connected to the controller 21 to control the stack indicator 9 operation. Therefore, the TOS of the stack where the specified elements of the general register file 5 are connected via the multiswitch 37 when the address specified in the address 13 is equal to the numeric code in the CSI (2) (39). Is accessed, in which case the TOS acts as a connection mode.

10. The contents of the CSI 1 and the CSI 2 and the TOS as the connected mode or the disconnected mode are denoted as "TOS". In FIG. 10, the CSI 1 and the CSI 2 are both composed of three bits, that is, bit 2-bit 0, and the contents of the CSI 1 and the contents of the CSI 2 are different from each other. Therefore, if the content in the CSI 1 is "0", the content that may be in the CSI 2 is any one of the codes "1"-"111".

If the content in the CSI 1 is "1", the content in the CSI 2 may be any one of "0"-"111" except for the code "1".

Thus, the two elements in a general register file are designated by CSI (1) and CSI (2), and are connected to the stack's TOS through multiple switch devices (1) and (2), respectively. For example, consider the case where the content of CSI 1 is "0" and the content of CSI 1 is "001".

In this case, if the code "000 'is corrected at the address 13, the TOS to which the element R ₀ is connected to the unconnected mode will be accessed and therefore the TOS is easily used as an element of the general purpose register file. If the address "1" is assigned to the address 13, the TOS to which the element R ₁ is connected to the connection mode will be accessed, in which case the contents of the stack indicator 9 change so that the TOS acts as a stack. Will be.

Although the number of elements of the general purpose register file is limited to eight in the previous four embodiments, there is no need to limit to eight and arbitrary number of elements is possible in the present invention.

Although the preferred embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and alterations could be made without departing from the spirit and scope of the invention as defined by the appended claims.

From the foregoing, it will be appreciated that according to the present invention, a data processing system having three resources, providing high processing capacity, reducing the number of instructions, and using two address format instructions can be provided. .

Claims (1)

1 and 2, which include a main memory, a general register file having a plurality of elements, a stack having a stack top, and a address section specifying each data address, and an instruction code specifying an operation to be performed. A data processing system consisting of an instruction register that accumulates operands of a figure and performing operations on a plurality of data, said data processing system further comprising at least one of said elements in said stack top (TOS) in a general purpose register file. First means (11, 17, 23, 25, 27, 29) for matching and second means (11, 21, 9, 17, 25, 27) for controlling the operation of the stack, whereby The upper end of the stack is selected by the first means when the element whose top of the stack coincides is designated by the bungee and the operation of the stack is controlled by the second means. Data processing system according to claim.

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