JP2819376B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate electrode, the gate
Porosity obtained by anodizing the site electrode
The present invention relates to a semiconductor device having at least an oxide layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, there has been known a configuration in which an insulating gate type field effect transistor (hereinafter referred to as a TFT) using a thin film semiconductor is integrated on a glass substrate or the like and used for an active matrix type liquid crystal display device or the like. . It is also known to use TFT for other integrated circuits.

As a configuration of a TFT used in the above-described device, a TFT having a configuration described below is known. This TFT is characterized in that a gate electrode is made of a material containing aluminum as a main component, and an oxide layer formed by an anodic oxidation process is formed around the gate electrode. This configuration,
Ion implantation into the source / drain region using the gate electrode and the oxide layer around the gate electrode as a mask realizes an offset gate structure to reduce electric field concentration between the source and channel and between the drain and channel Therefore, this is one of the most suitable configurations for a TFT intended to reduce off-state current.

[0004] Hereinafter, a manufacturing process of the TFT will be described with reference to FIG. FIG. 4 shows a top view thereof. FIG.
A cross section taken along line BB ′ in FIG. 3A corresponds to FIG. First, a silicon oxide film is formed as a base film 12 on a glass substrate 11 to a thickness of 2000 ° by a sputtering method. Next, an active layer 13 is formed by forming a silicon film for forming an active layer and performing element isolation patterning. The silicon film forming the active layer 13 is made of crystalline microcrystalline silicon, polycrystalline silicon, or amorphous silicon. Further, the semiconductor material forming the active layer is not limited to silicon, and may use another semiconductor.

Then, a silicon oxide film serving as the gate insulating film 14 is formed to a thickness of 1000 ° by a sputtering method.
Then, an aluminum film to be the gate electrode 15 is formed to a thickness of 6000.degree., And the aluminum film is subjected to the panning to form the gate electrode and the gate wiring 15.

Thereafter, an oxide layer 18 is formed around the gate electrode 15 by performing anodic oxidation. In a step shown in FIG. 3D, a contact hole to the gate electrode is formed. However, in connection with the necessity of providing the contact electrode 24, a problem described below occurs here.

It is necessary to form an electrode 24 on the gate electrode 15 through a contact hole. At this time, if an oxide layer 18 is formed on the surface of the gate electrode by anodic oxidation, a hole forming process is required. There is a problem that it becomes difficult. It is useful in the process to simultaneously perform a hole forming step for the contact electrode 24 to the gate electrode 15 and a hole forming step for the contact to the source / drain region (23/25 in FIG. 4). At this time, the silicon oxide film 14 serving as a gate electrode and the interlayer insulator 22 are formed on the source / drain regions, but the oxide layer 18 and the interlayer insulator 22 are formed on the gate electrode 15. ing.

Since the etching rate of the oxide layer of the aluminum film is smaller than the etching rate of the silicon oxide film, the drilling of the gate electrode 15 is completed even after the drilling of the source / drain regions is completed. Without this, the gate contact cannot be made. Conversely, if the hole in the gate electrode 15 is completely formed, the source / drain region and the periphery of the contact portion are etched, and a defect occurs when the source / drain electrode is formed.

To solve this problem, the gate electrode 15
In this case, it is conceivable to separate the holes in the oxide layer 1 and the source / drain regions.
It is difficult to remove 8 by etching, which is not preferable in the process.

Therefore, at present, a mask 17 is provided at a contact portion to the gate electrode 15 so that this portion is not subjected to anodic oxidation. (FIG. 3 (C))

However, if a resist is used as the mask 17, the following problem occurs. -A resist cannot be formed on the aluminum electrode 15 which is a gate electrode with good adhesion, and an oxide layer will be formed under the resist in the anodization step. In particular, there is a problem that the oxidized portion is raised under the resist. In the anodizing step, a voltage of about 200 V is applied to the gate electrode 15, and at this voltage, the resist causes dielectric breakdown and does not function as a mask.

Therefore, it is conceivable to use polyimide as the mask 36 instead of the resist 36. However, since polyimide must be baked at a temperature of 300 ° C. or more, hillocks are generated on the surface of the aluminum electrode 35 at this time. When this hillock occurs, in a later ion implantation step for forming a source / drain region, impurity ions (for example, B) penetrate through the aluminum electrode 35 and reach the channel formation region via the hillock portion. I will. Therefore, it is important to prevent the occurrence of hillocks.

Furthermore, when forming the source / drain regions later, an annealing step for activating the source / drain regions is required.
Degree of heating (in the case of laser annealing, in the case of thermal annealing, a higher temperature is required). At this time, hillocks are generated on the surface of the gate electrode 15 where the oxide layer 18 is not formed (the contact hole portion for the gate contact 24). Then, a failure occurs in the electrical contact between the gate electrode 15 and the contact electrode 24.

As described above, there are various problems in forming a contact hole to the gate electrode 15.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a gate electrode.
Non-porous oxide layer by selective anodization of
To form, and it is an object material hillock constituting the gate electrode is to provide a semiconductor device and a manufacturing method thereof does not occur.

[0016]

(First Invention) To achieve the above object, a semiconductor device according to the present invention is provided.
Forming a gate electrode 15;
The gate electrode 15 is anodized to a thickness of 100
Step of forming non-porous first oxide layer 16 thinner than 0 °
And a gate capacitor in the non-porous first oxide layer 16.
Masking the tact portion, and the gate contact portion
By anodizing the gate electrode except for
Non-porous second oxide layer 18 thicker than first oxide layer 16
Characterized by a step of forming a. (Second Invention) A method for manufacturing a semiconductor device according to the present invention
Forming a gate electrode 5 and anodizing the gate electrode 15
Non-porous primary acid thinner than 1000 mm
Forming the oxide layer 16 and the non-porous first oxide
Masking the gate contact portion in layer 16
And the gate electrode except for the gate contact portion.
Electrode by oxidation, forming a second oxide layer 18 thicker than the first oxide layer 16 nonporous, the gate
Etching the first oxide layer 16 at the light contact portion
And a step of performing (Third Invention) A method for manufacturing a semiconductor device according to the present invention
5 is made of aluminum-based material
Features. (Fourth Invention) A semiconductor device according to the present invention comprises a gate electrode 15
Acid obtained by anodizing gate electrode 15
And at least one oxide layer, wherein the oxide
The layers are a non-porous first oxide layer 16 and a non-porous second oxide layer.
A region comprising a layer 18 and the non-porous first oxide layer 1
6. The non-porous first oxide having a region consisting of only 6
The thickness of the layer 16 is thinner than that of the non-porous second oxide layer 18.
It is characterized by that. (Fifth Invention) In the semiconductor device according to the present invention, the thickness of the first oxide layer 16 is
Is thinner than 1000 °. (Sixth invention) In the semiconductor device of the present invention, the gate electrode 15 is made of aluminum.
Characterized by being composed of a material mainly composed of
You.

In the above structure, the thickness of the first oxide layer is preferably smaller than 1000 °, and the thickness of the second oxide layer is preferably larger than 1000 °. The main configuration of the present invention will be described below with reference to FIGS.
1 and 2 are cross-sectional views of a TFT using the present invention. A cross section taken along line AA ′ of FIG. 1A corresponds to FIG. 2A. FIG. 4 shows a top view of this TFT. A cross section taken along line BB ′ of FIG. 4A corresponds to FIG.
The cross section taken along the line CC ′ in FIG. 2A corresponds to FIG. Furthermore, the manufacturing process diagrams shown in FIGS. 1 and 2A to 2D correspond to each other.

In this TFT, the gate electrode is denoted by reference numeral 15. The gate electrode is mainly composed of aluminum, and an oxide layer 18 formed by an anodic oxidation process is formed around the gate electrode. This oxide layer 18
Is a mask for forming an offset gate region at the time of ion implantation for forming the source / drain regions 19 and 21 and is extremely effective.

Prior to forming the oxide layer 18, a thin oxide layer 16 is formed as shown in step (B).

[0020]

By forming a thin first oxide layer, generation of hillocks on the surface of a gate electrode containing aluminum as a main component can be prevented. Further, it becomes easy to form a mask on the surface of the gate electrode.

[0021]

1 and 2 show the steps of manufacturing a TFT according to this embodiment. The cross section taken along the line AA ′ in FIG.
This corresponds to (A). Drawings corresponding to the respective steps in FIGS. 1 and 2 correspond to FIGS. 1A and 2A, respectively. 4A corresponds to FIG. 1D, and the cross section taken along CC ′ in FIG. 4A corresponds to FIG. 4B and FIG. D). FIG. 2
(D) and FIG. 4 (B) show the same cross section.

The TFT shown in this embodiment can be used for a liquid crystal display device, an image sensor, and an integrated circuit using a thin film transistor.

The manufacturing process of this embodiment will be described below mainly with reference to FIGS. First, a silicon oxide film is formed as a base film 12 on a glass substrate 11 to a thickness of 2000 mm by a sputtering method. Further, a crystalline silicon film constituting the active layer 13 is formed. This silicon film is formed by plasma CVD.
An amorphous silicon film is formed by a method and crystallized by heating. Alternatively, crystallization by irradiation with laser light or equivalent strong light may be used. Then, the active layer 13 is formed by patterning. Further, a silicon oxide film 14 serving as a gate insulating film is formed to a thickness of 1000 °.

Next, an aluminum film constituting the gate electrode 15 is formed to a thickness of 6000.degree. And patterned as a gate electrode. In the aluminum film, one or more elements selected from scandium, palladium, and silicon are added in an amount of 1 to 5% by weight in order to form an oxide in a favorable state in the subsequent anodic oxidation step.

[0025] Then, the first anodic oxidation process forms a thin oxide layer 16 on the surface of the gate electrode 15. The oxide layer 16 is formed to a thickness of about 500 ° around the gate electrode and the gate wiring 35 by an anodic oxidation process in an ethylene glycol electrolytic solution containing 3% by weight of tartaric acid and 5% by weight of aqueous ammonia. It is formed. This oxide layer 1
The film thickness of No. 6 may be set to a thickness of 100 ° to 1000 °. However, if the thickness is large, the subsequent hole making step becomes difficult, so that it is meaningless. Anodizing in the above electrolytic solution
Is performed, the surface becomes a non-porous insulating film. (Figure 1
(B), FIG. 2 (B))

After the formation of the oxide layer 16, a resist mask 17 is formed. Mask 17 of this resist
During the formation of the resist, a baking step of 300 degrees or more is required to bake the resist. However, since the thin oxide layer 16 is formed in advance, hillocks are generated in the electrode 15 mainly composed of aluminum. Can be prevented.

When a thin anodic oxide layer is formed as described above, the adhesiveness of the resist is improved. Therefore, if the voltage applied in the subsequent anodic oxidation step is reduced,
Resist can be used instead of polyimide. However, in this case, it is necessary to lengthen the time of the anodic oxidation step.

The second anodic oxidation step comprises
A second oxide layer is formed to a thickness of about
Was 2500 mm thick. This process is also the first anode
As in the oxidation step, tartaric acid is 3% by weight and ammonia water is 5 %.
When anodizing is performed in an electrolytic solution of ethylene glycol mixed with the weight %, a nonporous insulating film having a dense surface is obtained .
The thickness of the oxide layer was controlled by the anodic oxidation time. The control of the film thickness can also be performed by controlling the applied voltage.

This second anodic oxidation step almost determines the thickness of the oxide layer 18, and the thickness determines the length of the offset gate region. The length of the offset gate region is determined according to the embodiment,
If the angle is less than 1500 °, a great effect cannot be obtained.
Therefore, in order to increase the thickness to 1500 ° or more, in the second anodic oxidation step, the oxide layer is formed to 1000 ° or more.
It is necessary that the thickness be larger than that of the oxide layer formed in the first anodic oxidation step so that the thickness becomes 2000 mm or more.

Thus, the state shown in FIGS. 1C and 2C is obtained. Next, source / drain regions 19 and 21 are formed in the active layer 13 by ion implantation of a P or B element. Here, if a P element is implanted, an N-channel type T
If the FT implants a B element, a P-channel TFT can be formed.

At the time of this ion implantation, the oxide layers 16 and 18
Forms an offset gate region. After that, the source / drain regions are activated by laser light irradiation or strong light irradiation equivalent thereto. At the time of laser light irradiation, it is effective to perform laser light irradiation while performing heating at about 300 degrees. The annealing by irradiation with strong light is called rapid thermal annealing (RTA), and is performed for a short time (several seconds to several minutes).
Irradiation of infrared light makes the irradiated surface 1000 to 120
This is a method of performing annealing by heating to about 0 degrees. This method utilizes the fact that absorption of infrared light (eg, halogen lamp light having a wavelength of 1.3 μm) is small in a glass substrate and large in a silicon film. This is a useful method that can selectively thermally anneal the film. In any case, since a thin oxide layer 16 is formed on the surface of the gate electrode 15 in this step, generation of hillocks on the surface of the gate electrode can be prevented.

Then, a silicon oxide film or polyimide is formed as the interlayer insulator 22. Then, contact holes for forming the source / drain electrodes 23 and 25 and the gate contact 24 are simultaneously formed by etching with buffered hydrofluoric acid. At this time, when forming the contact holes for the source / drain electrodes 23 and 25, the interlayer insulator 22 and the silicon oxide film 14 are etched. The formation of a contact hole for forming the gate contact 24 is performed by etching the oxide layer 16 and the interlayer insulator 22 formed by the first anodic oxidation.

Since the thickness of the oxide layer 16 is as thin as about 500 °, the oxide layer 1
The influence of the etching of No. 6 is hardly a problem. That is, the formation of the contact hole for the gate contact 24 and the formation of the contact hole for the source / drain electrodes 23 and 25 can be performed simultaneously. Then, the source / drain electrodes 23 and 25 and the gate contact 24
Is completed to complete the TFT. (Figure 1
(D), FIG. 2 (D))

The gist of the present invention is that a thin oxide layer is first formed on a gate electrode mainly composed of aluminum in order to prevent hillocks, and a second oxide layer is formed in a portion other than the gate contact portion. It is characterized by the following. Therefore, other configurations, for example, the formation method and film thickness of the active layer,
Furthermore, the method for forming the gate insulating film, the film thickness, and the like are not particularly limited, and may be determined according to the implementation.

[0035]

According to the present invention, anodization is performed.
Thus, a thin nonporous first oxide layer is formed on the gate electrode.
Since it is formed, a resist formed on the gate electrode
Good adhesion, and a second oxide layer is formed under the resist
I can't cut it. According to the present invention, the resist
Baking, the non-porous first oxidation having the above-mentioned thickness is small.
Since the material layer is formed on the gate electrode,
Hillock does not occur. According to the present invention, the gate electrode
Since hillocks are not generated, the source area and drain
When adding impurity ions to the In region, the hillock
Does not reach the channel region via.
According to the present invention, it is possible to form a hole in the gate contact portion and
And drilling in source and drain regions
The difference in rate is due to the first oxide thin only in the gate contact part
It can be adjusted by forming a layer. That is, the first
In the second anodic oxidation step, a thin oxide layer is formed around the gate electrode, and in the second anodic oxidation step, a thick oxide layer is formed except for the contact portion, so that a hillock is formed on the gate electrode. And the problem of forming a contact hole in a gate electrode can be solved at the same time.

When the thickness of the oxide layer formed around the gate electrode is increased in order to lengthen the offset gate region, for example, when the thickness of the oxide layer is 5000 ° or more, the first By forming the oxide layer thin, a structure in which contact with the gate electrode can be easily performed can be obtained.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of an example.

FIG. 2 shows a manufacturing process of an example.

FIG. 3 shows a manufacturing process of a conventional TFT.

FIG. 4 shows a top view of a conventional or example TFT.

[Explanation of symbols]

 11 Glass substrate 12 Base film (silicon oxide film) 13 Active layer (silicon film) 14 Gate insulating film (silicon oxide film) 15 Gate electrode (Aluminum film) 16 oxide layer 17 mask (polyimide) 18 oxide layer 19 source / drain region 20 channel formation region 21・ Drain / source region 22 ・ ・ ・ ・ Interlayer insulator 23 ・ ・ ・ ・ Source / drain electrode 24 ・ ・ ・ ・ Gate contact 25 ・ ・ ・ ・ Drain / source electrode

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Satoshi Teramoto 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Laboratory Co., Ltd. (56) References JP-A-51-134587 (JP, A) JP-A-63-140579 ( JP, A) JP-A-5-114724 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/336 H01L 29/786 H01L 21/3205 H01L 21/28 301 H01L 29 / 40

Claims (6)

(57) [Claims] Forming a gate electrode by anodizing the gate electrode to form a gate electrode having a thickness of 100 nm;
Forming a non-porous first oxide layer thinner than 0 °, masking a gate contact portion in the non-porous first oxide layer, and excluding the gate contact portion. Anodizing the electrode
By reduction, a method for manufacturing a semiconductor device characterized by having a step of forming a second oxide layer of the first oxide layer thicker nonporous <br/>. 2. A step of forming a gate electrode, and anodizing the gate electrode so as to have a thickness of 100%.
Forming a non-porous first oxide layer thinner than 0 °; and a gate contact portion in the non-porous first oxide layer.
Masking, and anodizing the gate electrode except for the gate contact portion.
Forming a non-porous second oxide layer thicker than the first oxide layer by etching, and etching the first oxide layer of the gate contact portion.
The method for manufacturing a semiconductor device characterized by comprising the steps of grayed, the. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is made of a material containing aluminum as a main component. 4. The method according to claim 1 , wherein said gate electrode is anodized.
At least an oxide layer obtained by
To a semiconductor device, the oxide layer, a first non-porous oxide layer and the non-porous second
A region comprising an oxide layer and the non-porous first oxide layer
And the thickness of the non-porous first oxide layer is equal to the thickness of the non-porous second oxide layer.
A semiconductor device characterized by being thinner than an oxide layer. 5. The method of claim 4, the semiconductor device where the thickness of the first oxide layer is equal to or smaller than 1000 Å. 6. The method according to claim 4, wherein the gate electrode is made of aluminum.
Characterized by being composed of a material mainly composed of
Semiconductor device.