JP2817285B2 - Field-effect transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a MOS field effect transistor suitable for high integration and high speed operation.

[Prior Art] A conventional MOS field effect transistor is shown in FIG.
As shown in FIG. 1, a gate oxide film 302, a gate electrode 303, and a high-concentration impurity region (source and drain) 304 of the second conductivity type are formed on one main surface of a first conductivity type single crystal silicon substrate 301. ing.

In order to achieve high integration and high speed of an integrated circuit, the size of the MOS transistor must be reduced, and as a result, the operation characteristics of a MOS transistor with a small gate length will be adversely affected. The short channel effect exerted has become significant. Therefore, in order to suppress this short channel effect, as shown in FIG. 3B, a region 30 having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is used.
The structure in which 5 is formed is often used.

[Problems to be Solved by the Invention] In the conventional MOS transistor described above, a relatively high-concentration impurity region of the same conductivity type as the semiconductor substrate is formed inside the semiconductor substrate entirely under the active region to suppress punch-through. Have been. Therefore, there is a disadvantage that the junction capacitance of the PN junction formed between the region and the high-concentration source and drain regions having the conductivity type opposite to that of this region is increased, and the switching speed of the transistor is hardly improved.

[Differences from the Prior Art of the Invention] In the above-described conventional MOS transistor, the impurity concentration of the silicon substrate is increased to suppress punch-through, or an impurity region having a relatively high concentration is present under the entire active region. On the other hand, in the present invention, the insulating film is present on the inner surface of the groove in which the source and the drain are formed, so that it is not necessary to increase the impurity concentration of the substrate or to form a relatively high impurity region. Have a point.

Means for Solving the Problems The gist of the present invention is to provide a semiconductor substrate of a first conductivity type having a low impurity concentration, an impurity layer of a first conductivity type having a high impurity concentration provided on the semiconductor substrate, An electric field comprising a source / drain region of the second conductivity type provided apart from each other on the impurity layer and a gate structure for controlling a channel between the source / drain regions provided above and between the source / drain regions. In the effect transistor, a groove is provided in the impurity layer below the source / drain region, and at least one surface of the groove is covered with an insulating film, and the source / drain region extends in the groove.

[Operation of the Invention] The insulating film in the trench prevents the generation of a depletion layer between the source / drain region and the high concentration impurity. Therefore, the parasitic capacitance is reduced and the switching speed of the field effect transistor is improved.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. FIG. 1 shows a P-channel type MOS transistor.

101 is a single crystal N-type silicon substrate, 102 is a gate oxide film,
Reference numeral 103 denotes a gate electrode made of polycrystalline silicon doped with phosphorus at a concentration of about 10 ²⁰ cm ⁻³ , and 104 denotes polycrystalline silicon in which a high-concentration P-type impurity is diffused, and functions as a source and a drain. 105 is a low-concentration P-type impurity region, 106 is a groove formed by separating the gate electrode 103 from the silicon substrate 101, 107 is an oxide film, 108 is a nitride film, and 109 is a sidewall formed of an insulating film. And 110 are regions of the same conductivity type as the substrate and having a higher impurity concentration than the substrate. Oxide film 107
Assuming that the film pressure is 1000Å, the capacity per unit area is
3.45 × 10 ⁻⁸ F / cm ² . If the impurity concentration of the N-type impurity region 110 is 5 × 10 ¹⁶ cm ⁻³ or more, the capacitance of the oxide film 107 on the bottom surface of the source and drain and the depletion layer capacitance extending to the N-type semiconductor region below the oxide film are connected in series. The capacitance is formed between the source and the drain and the substrate in the absence of the oxide film 108
The capacitance of the PN junction can be smaller than 7 to 10 × 10 ⁻⁸ F / cm ² .

As described above, even if the well structure is the same, if an oxide film is provided below the source / drain, the bottom component of the diffusion layer capacitance can be reduced. In addition, since the diffusion from the source / drain having a high impurity concentration can be suppressed by the oxide film, the depth of the diffusion layer can be reduced and the short channel effect can be suppressed.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.
Since the parasitic resistance of the LDD is determined by the low-concentration P-type region on the source side, a sidewall is formed only on the drain type, and the lateral concentration gradient is steep on the source side. With this structure, a MOS transistor can be configured by satisfying three of the enhancements of punch-through resistance, low parasitic resistance, and hot carrier resistance.

[Effects of the Invention] As described above, according to the present invention, the capacitance between the source and the drain and the substrate can be reduced by providing the insulating film on the inner surface of the groove in which the source or the drain is formed.

[Brief description of the drawings]

1 is a longitudinal sectional view showing a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention, and FIG.
FIG. 2B is a longitudinal sectional view showing a conventional MOS transistor. 101, 201, 301 ... single crystal N-type silicon substrate, 102, 202, 302 ... gate insulating film, 103, 203 ... P-type impurity region, 104, 204, 303 ... gate electrode, 105, 205 ... high concentration P-type conductive film, 305 ... 1st conductivity type impurity Region, 106,206... Low-concentration P-type impurity region, 107,207... Groove, 108,109,208,209... Insulating film, 110,210.

Claims (1)

(57) [Claims] A first conductivity type semiconductor substrate having a low impurity concentration; a high impurity concentration first conductivity type impurity layer provided on the semiconductor substrate; and a first impurity layer provided on the impurity layer so as to be separated from each other. A source / drain region of the second conductivity type,
A gate structure provided above the drain region and controlling a channel between the source and drain regions, wherein a groove is provided in the impurity layer below the source / drain region, and at least one of the grooves is provided. A field effect transistor wherein the surface is covered with an insulating film, and the source / drain regions extend in these trenches.