JP2815115B2 - Light emitting device and manufacturing method thereof - Google Patents

Light emitting device and manufacturing method thereof

Info

Publication number
JP2815115B2
JP2815115B2 JP18606889A JP18606889A JP2815115B2 JP 2815115 B2 JP2815115 B2 JP 2815115B2 JP 18606889 A JP18606889 A JP 18606889A JP 18606889 A JP18606889 A JP 18606889A JP 2815115 B2 JP2815115 B2 JP 2815115B2
Authority
JP
Japan
Prior art keywords
layer
substrate
cladding
active
cladding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18606889A
Other languages
Japanese (ja)
Other versions
JPH0352284A (en
Inventor
秀司 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP18606889A priority Critical patent/JP2815115B2/en
Priority to DE69009329T priority patent/DE69009329T2/en
Priority to EP90113874A priority patent/EP0410307B1/en
Priority to US07/554,905 priority patent/US5115284A/en
Publication of JPH0352284A publication Critical patent/JPH0352284A/en
Application granted granted Critical
Publication of JP2815115B2 publication Critical patent/JP2815115B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】 本発明は、発光装置及びその作製方法に係り、特に複
数の発光部を有する発光装置及びその作製方法に関す
る。
The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly, to a light emitting device having a plurality of light emitting portions and a method for manufacturing the same.

本発明は、複数の異なったあるいは同一の波長の光を
発光する半導体レーザ、LED等に好適に用いられるもの
である。
INDUSTRIAL APPLICABILITY The present invention is suitably used for semiconductor lasers, LEDs, and the like that emit light of a plurality of different or the same wavelengths.

〔従来の技術〕[Conventional technology]

従来、異なる波長の光を1本のファイバに伝送するこ
とにより多くの情報を同時に送るという光波長多重通信
を行なう場合、送信部として伝送する波長の数と同数の
発光素子を必要としていた。さらにこれら複数の発光素
子からの光を1本のファイバへ伝送するために、光を結
合させる光合波器(FOP,Vol.4,No7,P45,1979,小島敬基
等)を用いる必要があった。そしてこれらの複数の発光
素子と光合波器を光学的に損失が少なくなるように、精
度よく結合していた。
2. Description of the Related Art Conventionally, when performing optical wavelength division multiplexing communication in which a large amount of information is transmitted simultaneously by transmitting light of different wavelengths to one fiber, a light emitting element of the same number as the number of wavelengths to be transmitted is required as a transmission unit. Further, in order to transmit the light from the plurality of light emitting elements to one fiber, it is necessary to use an optical multiplexer (FOP, Vol. 4, No. 7, P45, 1979, Keiki Kojima, etc.) for coupling the light. Was. Then, the plurality of light emitting elements and the optical multiplexer are coupled with high precision so as to reduce optical loss.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、上記従来技術では複数の発光素子,光
合波器を製作した後、高精度で配置していたために、次
のような課題があった。
However, in the above-described conventional technology, a plurality of light emitting elements and optical multiplexers are manufactured and then arranged with high accuracy, and thus have the following problems.

複数の発光素子,光合波器を有するために、送信部
のサイズが大きくなる。
Since a plurality of light emitting elements and an optical multiplexer are provided, the size of the transmitting unit is increased.

発光素子と光合波器との結合、光合波器とファイバ
との結合が必要となり、機械的な結合が複数個存在する
ために全体での結合損失が大きくなり、効率が悪くな
る。
The coupling between the light emitting element and the optical multiplexer and the coupling between the optical multiplexer and the fiber are required, and the presence of a plurality of mechanical couplings increases the coupling loss as a whole, resulting in poor efficiency.

複数個の素子を独立に作製し、結合するためにプロ
セスが複雑となる。
The process is complicated because a plurality of elements are independently manufactured and combined.

多くの素子を必要とし、プロセスも複雑なために、
コストが高くなる。
Because it requires many elements and the process is complicated,
The cost is high.

本発明の目的は、上記従来技術の問題点を解決し、安
価に作製出来、且つ、コンパクトで効率の良い発光装置
及びその作製方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a compact and efficient light emitting device which can be manufactured at low cost and a method for manufacturing the same.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の発光装置は、基体と、該基体上の一部に形成
された第1のクラッド層と、前記基体上の第1のクラッ
ド層の外周部に形成され、電流が注入されることによっ
て光を発する第1の活性層と、前記基体上の第1の活性
層の外周部に形成された第2のクラッド層と、前記基体
上の第2のクラッド層の外周部に形成された絶縁又は高
抵抗層と、前記基体上の絶縁又は高抵抗層の外周部に形
成された第3のクラッド層と、前記基体上の第3のクラ
ッド層の外周部に形成され、電流が注入されることによ
って光を発する第2の活性層と、前記基体上の第2の活
性層の外周部に形成された第4のクラッド層と、前記第
1及び第2の活性層に電流を供給するための電極とから
成り、前記第1の活性層、第1及び第2のクラッド層
は、前記基体の表面にほぼ垂直な接合面を有する第1の
ダブルヘテロ構造を構成し、前記第2の活性層、第3及
び第4のクラッド層は、前記基体の表面にほぼ垂直な接
合面を有する第2のダブルヘテロ構造を構成することを
特徴とする。
The light emitting device according to the present invention includes a substrate, a first cladding layer formed on a part of the substrate, and an outer peripheral portion of the first cladding layer on the substrate. A first active layer that emits light, a second cladding layer formed on the outer periphery of the first active layer on the base, and an insulation formed on the outer periphery of the second cladding layer on the base. Alternatively, a high-resistance layer, a third cladding layer formed on the outer periphery of the insulating or high-resistance layer on the base, and an outer periphery of the third cladding layer on the base are injected with current. A second active layer that emits light, a fourth cladding layer formed on the outer periphery of the second active layer on the base, and a current supply to the first and second active layers. Wherein the first active layer, the first and second cladding layers are provided on the surface of the base. Forming a first double heterostructure having a substantially vertical bonding surface, wherein the second active layer, the third and the fourth cladding layers have a second double heterostructure having a bonding surface substantially perpendicular to the surface of the substrate. It is characterized by constituting a hetero structure.

また、本発明の発光装置の作製方法は、基体の表面の
一部に、他の部分よりも大きい核形成密度を有し、且
つ、この上で結晶が単一核のみより成長するように充分
小さい面積を有する核形成面を形成する過程と、前記核
形成面を含む基体上の微小領域に単結晶半導体から成る
第1のクラッド層を単一核より成長させる過程と、前記
基体上の第1のクラッド層の外周部に単結晶半導体から
成る第1の活性層を成長させる過程と、前記基体上の第
1の活性層の外周部に単結晶半導体から成る第2のクラ
ッド層を成長させる過程と、前記基体上の第2のクラッ
ド層の外周部に単結晶半導体から成る絶縁又は高抵抗層
を成長させる過程と、前記基体上の絶縁又は高抵抗層の
外周部に単結晶半導体から成る第3のクラッド層を成長
させる過程と、前記基体上の第3のクラッド層の外周部
に単結晶半導体から成る第2の活性層を成長させる過程
と、前記基体上の第2の活性層の外周部に単結晶半導体
から成る第4のクラッド層を成長させる過程と、前記成
長した第1及び第2の活性層、第1乃至第4のクラッド
層及び絶縁又は高抵抗層の上部を平坦化する過程と、前
記第1及び第2の活性層に電流を供給するための電極を
形成する過程とから成り、前記第1の活性層、第1及び
第2のクラッド層は、前記基体の表面にほぼ垂直な接合
面を有する第1のダブルヘテロ構造を構成し、前記第2
の活性層、第3及び第4のクラッド層は、前記基体の表
面にほぼ垂直な接合面を有する第2のダブルヘテロ構造
を構成することを特徴とする。
In addition, the method for manufacturing a light-emitting device of the present invention has a structure in which a part of the surface of the base has a higher nucleation density than other parts, and a crystal grows on this part from only a single nucleus. Forming a nucleation surface having a small area, growing a first cladding layer made of a single crystal semiconductor from a single nucleus in a minute region on the substrate including the nucleation surface, A process of growing a first active layer made of a single crystal semiconductor on an outer peripheral portion of one clad layer, and a process of growing a second clad layer made of a single crystal semiconductor on an outer peripheral portion of the first active layer on the substrate. A step of growing an insulating or high-resistance layer made of a single-crystal semiconductor on an outer peripheral portion of the second cladding layer on the base, and a step of growing a single-crystal semiconductor on the outer peripheral portion of the insulating or high-resistance layer on the base. Growing a third cladding layer; Growing a second active layer made of a single crystal semiconductor on an outer peripheral portion of the upper third clad layer, and forming a fourth clad layer made of a single crystal semiconductor on an outer peripheral portion of the second active layer on the substrate Growing the first and second active layers, the first to fourth cladding layers, and insulating or high-resistance layers, and the first and second active layers. Forming an electrode for supplying current to the first active layer, the first and second cladding layers, the first active layer, the first and second cladding layers having a junction surface substantially perpendicular to the surface of the substrate. A structure, wherein the second
The third active layer, the third and fourth cladding layers constitute a second double heterostructure having a bonding surface substantially perpendicular to the surface of the base.

〔作用〕[Action]

核形成密度の小さい非核形成面と、単一核のみより結
晶成長するに充分小さい面積を有し、該非核形成面の核
形成密度より大きい核形成密度を有する核形成面とが隣
接して配された自由表面を有する基体に、結晶形処理を
施して単結晶を形成する方法については、既に特開昭64
−723号公報に開示されており、所望の下地基板上の所
望の位置に核形成面を中心として単結晶を成長させるこ
とができる結晶形成方法である。
A non-nucleation surface having a low nucleation density and a nucleation surface having an area small enough for crystal growth than a single nucleus and having a nucleation density higher than the nucleation density of the non-nucleation surface are arranged adjacent to each other. A method for forming a single crystal by subjecting a substrate having a free surface to a crystal shape treatment has already been disclosed in
No.-723 discloses a crystal formation method capable of growing a single crystal at a desired position on a desired base substrate with a nucleation surface as a center.

本発明はこのような結晶形成方法を用いて、単結晶を
成長させる段階で、単結晶材料,組成比、不純物材料等
の製造条件を変えることで複数のダブルヘテロ構造を有
し、且つ各々のダブルヘテロ構造部間に絶縁層又は高抵
抗層を有する単結晶を成長させ、この単結晶を平坦化す
ることで複数のダブル構造部を露出させ、複数の発光部
を構成するものである。
The present invention has a plurality of double heterostructures by changing manufacturing conditions of a single crystal material, a composition ratio, an impurity material, and the like at the stage of growing a single crystal using such a crystal formation method, and A single crystal having an insulating layer or a high resistance layer between the double hetero structure portions is grown, and the single crystal is flattened to expose a plurality of double structure portions, thereby forming a plurality of light emitting portions.

なお、本発明においてダブルヘテロ構造部間に絶縁層
又は高抵抗層を設けたのは、所望のダブルヘテロ構造部
に電流を注入する場合、隣接するダブルヘテロ構造部に
漏れる電流を防ぐためである。即ち、このような構成に
よって本発明の発光素子は、前記目的を達成し、更によ
り高効率で雑音の小さい発光が行なえるものである。
In the present invention, the reason why the insulating layer or the high resistance layer is provided between the double hetero structure portions is to prevent a current leaking to an adjacent double hetero structure portion when a current is injected into a desired double hetero structure portion. . That is, with such a configuration, the light-emitting element of the present invention achieves the above-described object, and can emit light with higher efficiency and less noise.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を用いて詳細に説明
する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

まず、本発明の発光装置及びその作製方法の実施態様
例について説明する。
First, an embodiment of the light emitting device of the present invention and a manufacturing method thereof will be described.

第1図は、本発明の発光装置の第一実施態様例の構造
を示す平面図及び縦断面図であり、第2図(a)〜
(e)は、その製造工程を示す工程図である。
FIG. 1 is a plan view and a longitudinal sectional view showing the structure of a first embodiment of the light emitting device of the present invention, and FIGS.
(E) is a process drawing showing the manufacturing process.

まず、第2図(a)に示すように、SiO2,Al2O3等の非
晶質基板10の表面を非核形成面2とし、この非核形面2
上に微細な堆積膜を形して核形成面1とする。
First, as shown in FIG. 2A, the surface of an amorphous substrate 10 such as SiO 2 , Al 2 O 3 is defined as a non-nucleation surface 2.
A nucleation surface 1 is formed by forming a fine deposited film thereon.

次に、第2図(b)に示すように、非核形成面2と核
形成面1の核形成密度の差を利用して、有機金属気相成
長法(MOCVD法)を用いて、選択的に核形成面1にGaAs
単結晶粒7を形成する。成長はトリメチルガリウム(TM
G)ターシャリーブチルアルシン(TBAs)AsH3などの原
料を用いて行なう。成長温度は一般には500〜800℃、望
ましくは570〜760℃、最適には600〜700℃で行ない、圧
力は一般には1〜80Torr望ましくは1〜30Torr、最適に
は1〜10Torrで行なう。
Next, as shown in FIG. 2 (b), by utilizing the difference in nucleation density between the non-nucleation surface 2 and the nucleation surface 1, selective metalorganic vapor phase epitaxy (MOCVD) is used. GaAs on nucleation surface 1
A single crystal grain 7 is formed. Growth is trimethylgallium (TM
It performed using raw materials such as G) tertiary butyl arsine (TBAs) AsH 3. The growth temperature is generally from 500 to 800 ° C, preferably from 570 to 760 ° C, most preferably from 600 to 700 ° C, and the pressure is generally from 1 to 80 Torr, preferably from 1 to 30 Torr, most preferably from 1 to 10 Torr.

次に、第2図(c)に示すように、圧力を一般には50
〜760Torr、望ましくは100〜760Torr、最適には300〜76
0Torrに変え、原料の供給量を増し、トリメチルアルミ
ニウム(TMAl)などのAl原料を加え、クラッド層3a、活
性層4a、クラッド層3b、高抵抗層8、クラッド層3c、活
性層4b、クラッド層3dを順次形成する。
Next, as shown in FIG.
~ 760 Torr, preferably 100 ~ 760 Torr, optimally 300 ~ 76
Change to 0 Torr, increase the supply amount of raw material, add Al raw material such as trimethyl aluminum (TMAl), and add cladding layer 3a, active layer 4a, cladding layer 3b, high resistance layer 8, cladding layer 3c, active layer 4b, cladding layer 3d is sequentially formed.

ここで成長法はMOCVD法にかぎらずガスソース分子線
成長法(ガスソースMBE法),液相成長法(LPE法)を用
いてもよい。また、ここで形成する単結晶はInPなどの
他のIII−V族化合物半導体でもかまわない。
Here, the growth method is not limited to the MOCVD method, and a gas source molecular beam growth method (gas source MBE method) or a liquid phase growth method (LPE method) may be used. The single crystal formed here may be another III-V compound semiconductor such as InP.

次に、第2図(d)に示すように、結晶表面を平坦化
し、クラッド層3a、活性層4a、クラッド層3b、高抵抗
8、クラッド層3c、活性層4b、クラッド層3dを露出させ
る。
Next, as shown in FIG. 2 (d), the crystal surface is flattened to expose the clad layer 3a, the active layer 4a, the clad layer 3b, the high resistance 8, the clad layer 3c, the active layer 4b, and the clad layer 3d. .

次に、第2図(e)に示すように、形成された単結晶
層の露出したクラッド層3a,3b,3c,3d上に電極層5を形
成し、クラッド層3a,3b,3c,3dの上のそれぞれの電極層
に電極配線6a,6b,6c,6dを接続させる。
Next, as shown in FIG. 2 (e), the electrode layer 5 is formed on the exposed clad layers 3a, 3b, 3c, 3d of the formed single crystal layer, and the clad layers 3a, 3b, 3c, 3d are formed. The electrode wirings 6a, 6b, 6c, 6d are connected to the respective electrode layers above.

このようにして、第1図に示す本発明に係る発光装置
を作製することができる。なお、作製された発光装置の
活性層4a,4bは第1図の平面図に示すように、多角形形
状となっており、かかる活性層4a,4bから光が放出され
る。活性層4a、活性層4bから放出される光の波長は、導
入される単結晶材料、組成比、等を変えることで、任意
に設定することができ、同一波長とすることも可能であ
る。
Thus, the light emitting device according to the present invention shown in FIG. 1 can be manufactured. The active layers 4a and 4b of the manufactured light emitting device have a polygonal shape as shown in the plan view of FIG. 1, and light is emitted from the active layers 4a and 4b. The wavelength of light emitted from the active layers 4a and 4b can be arbitrarily set by changing the introduced single crystal material, composition ratio, and the like, and can be the same wavelength.

第3図は、本発明の発光装置の第二実施態様例の構造
を示す平面図及び縦断面図であり、第4図(a)〜
(e)は、その製造工程を示す工程図である。
FIG. 3 is a plan view and a longitudinal sectional view showing the structure of a second embodiment of the light emitting device of the present invention, and FIGS.
(E) is a process drawing showing the manufacturing process.

まず、第4図(a)に示すように、Al2O3等の支持基
板19上にSiO2等の非核形成面12を形成する層を形成す
る。その後この層に不純物イオンを打ち込み、核形成面
11を形成する。
First, as shown in FIG. 4A, a layer for forming the non-nucleation surface 12 such as SiO 2 is formed on a support substrate 19 such as Al 2 O 3 . Then, impurity ions are implanted into this layer, and the nucleation surface
Form 11.

次に、第4図(b)に示すように、第2図(b)を用
いて既に説明した第一実施態様例と同様にして、非核形
成面12と核形成面11の核形成密度の差を利用して、有機
金属気相成長法(MOCVD法)を用いて、選択的に核形成
面11にGaAs単結晶粒7を形成する。成長はトリメチルガ
リウム(TMG)、ターシャリ−ブチルアルシン(TBAs)A
sH3などの原料を用いて行なう。成長温度は一般には500
〜800℃、望ましくは570〜760℃と最適には600〜700℃
で行ない、圧力は一般には1〜80Torr望ましくは1〜30
Torr、最適には1〜10Torrで行なう。
Next, as shown in FIG. 4 (b), the nucleation density of the non-nucleation surface 12 and the nucleation surface 11 is calculated in the same manner as in the first embodiment already described with reference to FIG. 2 (b). Utilizing the difference, GaAs single crystal grains 7 are selectively formed on the nucleation surface 11 by using a metal organic chemical vapor deposition (MOCVD) method. Growth is trimethylgallium (TMG), tert-butylarsine (TBAs) A
carried out using raw materials such as sH 3. Growth temperature is generally 500
~ 800 ℃, preferably 570 ~ 760 ℃ and optimally 600 ~ 700 ℃
The pressure is generally 1 to 80 Torr, preferably 1 to 30 Torr.
Torr, optimally at 1-10 Torr.

次に、第4図(c)に示すように、第2図(c)を用
いて既に説明した第一実施態様と同様にして、圧力を一
般には50〜760Torr、望ましくは100〜760Torr、最適に
は300〜760Torrに変え、原料の供給量を増し、トリメチ
ルアルミニウム(TMAl)などのAl原料を加え、クラッド
層13a、活性層14a、クラッド層13b、高抵抗層18a、クラ
ッド層13c、活性層14b、クラッド層13d、高抵抗層18b、
クラッド層13e、活性層14c、クラッド層13fを順次形成
する。
Next, as shown in FIG. 4 (c), in the same manner as in the first embodiment already described with reference to FIG. 2 (c), the pressure is generally 50 to 760 Torr, preferably 100 to 760 Torr. To 300 to 760 Torr, increase the supply of raw materials, add an Al raw material such as trimethyl aluminum (TMAl), and add cladding layer 13a, active layer 14a, cladding layer 13b, high resistance layer 18a, cladding layer 13c, and active layer. 14b, cladding layer 13d, high resistance layer 18b,
A clad layer 13e, an active layer 14c, and a clad layer 13f are sequentially formed.

なお、結晶成長法はMOCVD法に限られず、単結晶がGaA
s以外の半導体材料であってもよいことは、第一実施態
様例と同じである。
The crystal growth method is not limited to the MOCVD method.
The semiconductor material other than s may be the same as in the first embodiment.

次に、第4図(d)に示すように、結晶表面を平坦化
し、クラッド層13a、活性層14a、クラッド層13b、高抵
抗層18a、クラッド層13c、活性層14b、クラッド層13d、
高抵抗層18b、クラッド層13e、活性層14c、クラッド層1
3fを露出させる。
Next, as shown in FIG. 4 (d), the crystal surface is flattened, and the cladding layer 13a, the active layer 14a, the cladding layer 13b, the high-resistance layer 18a, the cladding layer 13c, the active layer 14b, the cladding layer 13d,
High resistance layer 18b, cladding layer 13e, active layer 14c, cladding layer 1
Expose 3f.

次に、第4図(e)に示すように、形成された単結晶
層の露出したクラッド層13a,13b,13c,13d,13e,13f上に
電極層15を形成し、クラッド層13a,13b,13c,13d,13e,13
f上のそれぞれの電極層15に電極配線16a,16b,16c,16d,1
6e,16fを接続させる。
Next, as shown in FIG. 4 (e), an electrode layer 15 is formed on the exposed clad layers 13a, 13b, 13c, 13d, 13e, 13f of the formed single crystal layer, and the clad layers 13a, 13b are formed. , 13c, 13d, 13e, 13
The electrode wirings 16a, 16b, 16c, 16d, 1
Connect 6e and 16f.

このようにして、第3図に示す本発明に係る発光装置
を作製することができる。なお、作製された発光装置の
活性層14a,14b,14cは第3図の平面図に示すように、多
角形形状となっており、かかる活性層14a,14b,14cから
光が放出される。活性層14a,14b,14cから放出される光
の波長は、導入される単結晶材料、組成比、等を変える
ことで、任意に設定することができ、同一波長とするこ
とも、異なる波長とすることも可能である。
Thus, the light emitting device according to the present invention shown in FIG. 3 can be manufactured. The active layers 14a, 14b, 14c of the manufactured light emitting device have a polygonal shape as shown in the plan view of FIG. 3, and light is emitted from the active layers 14a, 14b, 14c. The wavelength of the light emitted from the active layers 14a, 14b, and 14c can be arbitrarily set by changing the single crystal material to be introduced, the composition ratio, and the like. It is also possible.

以下、上述した実施態様にかかわる実施例について説
明する。
Hereinafter, an example related to the above-described embodiment will be described.

(実施例1) 本実施例は第一実施態様例にかかわるものであり、i
−GaAs,i−Ga0.9Al0.1Asの二つの活性層をもつ半導体レ
ーザを作製したものである。なお半導体レーザの構造及
び製造工程は第1図,第2図を引用しながら説明するも
のとする。
(Example 1) This example relates to the first embodiment example, and
A semiconductor laser having two active layers of -GaAs and i-Ga 0.9 Al 0.1 As was manufactured. The structure and manufacturing process of the semiconductor laser will be described with reference to FIGS.

第2図(a)に示すように、非晶質基板10たるSiO2
板上にAl2O3を蒸着し、微細な領域(1.2μm□)を残
し、他はエッチングにより取り去ることにより、非核形
成面(SiO2)2と核形成面(Al2O3)1とを形成する。
As shown in FIG. 2 (a), Al 2 O 3 is vapor-deposited on the SiO 2 substrate as the amorphous substrate 10, leaving a fine region (1.2 μm square), and removing the others by etching to obtain a non-nucleus. A formation surface (SiO 2 ) 2 and a nucleation surface (Al 2 O 3 ) 1 are formed.

次に第2図(b)のようにMOCVD法により、成長温度6
00℃、キャリアガス流量(H2)3/min、原料ソースと
してターシャリーブチルアルシン(TBAs)を3×10-4mo
l/min、トリメチルガリウム(TMG)を3×10-5mol/mi
n、トリメチルアルミニウ(TMAl)を1×10-5mol/min、
ドーピング原料としてジエチルジンク(DEZn)を用い、
単結晶粒7たるp−Ga0.75Al0.25As単結晶粒を核形成す
る。
Next, as shown in FIG.
00 ° C, carrier gas flow rate (H 2 ) 3 / min, tertiary butyl arsine (TBAs) as raw material source 3 × 10 -4 mo
l / min, trimethylgallium (TMG) 3 × 10 -5 mol / mi
n, trimethylaluminum (TMAl) at 1 × 10 -5 mol / min,
Using diethyl zinc (DEZn) as a doping material,
The single crystal grains 7 as p-Ga 0.75 Al 0.25 As single crystal grains are nucleated.

次に、第2図(c)に示すようにMOCVD法により成長
温度600℃、キャリアガス流量10/min、圧力100Torr、
III−V族化合物半導体材料(V/III比=50)で、原料ソ
ースとしてアルシン(AsH3),TMG,TMAlを用い、ドーピ
ング原料としてDEZn,シラン(SiH4)を用いる。そし
て、原料ソース、ドーピング原料の切り換えにより、ク
ラッド層3aたるp−Ga0.75Al0.254Asクラッド層、活性
層40たるi−GaAs活性層、クラッド層3bたるn−Ga0.75
Al0.25Asクラッド層、高抵抗層8たるi−Ga0.7Al0.3As
高抵抗層、クラッド層3cたるn−Ga0.75Al0.25Asクラッ
ド層、活性層4bたるi−Ga0.9Al0.1As活性層、クラッド
層3dたるp−Ga0.75Al0.25Asクラッド層を成長する。
Next, as shown in FIG. 2 (c), the growth temperature was 600 ° C., the carrier gas flow rate was 10 / min, the pressure was 100 Torr by MOCVD.
A group III-V compound semiconductor material (V / III ratio = 50), arsine (AsH 3 ), TMG, TMAl is used as a raw material source, and DEZn and silane (SiH 4 ) are used as a doping raw material. Then, by switching the material source and the doping material, the p-Ga 0.75 Al 0.254 As clad layer as the clad layer 3a, the i-GaAs active layer as the active layer 40, and the n-Ga 0.75 as the clad layer 3b are formed.
Al 0.25 As clad layer, high resistance layer 8 i-Ga 0.7 Al 0.3 As
A high resistance layer, an n-Ga 0.75 Al 0.25 As clad layer as a clad layer 3c, an i-Ga 0.9 Al 0.1 As active layer as an active layer 4b, and a p-Ga 0.75 Al 0.25 As clad layer as a clad layer 3d are grown.

次に、第2図(d)に示すように、結晶表面をRIBEに
より平坦化し、クラッド層3aたるp−Ga0.75Al0.25Asク
ラッド層、クラッド層3bたるn−Ga0.75Al0.25Asクラッ
ド層、クラッド層3cたるn−Ga0.75Al0.25Asクラッド
層、クラッド層3dたるp−Ga0.75Al0.25Asクラッド層を
露出させ、さらに第2図(e)に示すように、その露出
面に電極層5たる導電層を形成し、この導電層をそれぞ
れ電極配線6a,6b,6cたるAu等の電極配線を接続して半導
体レーザを作製する。
Next, as shown in FIG. 2 (d), the crystal surface was flattened by RIBE, and a p-Ga 0.75 Al 0.25 As clad layer as a clad layer 3a, an n-Ga 0.75 Al 0.25 As clad layer as a clad layer 3b, cladding layer 3c serving n-Ga 0.75 Al 0.25 as cladding layer, the cladding layer 3d serving to expose the p-Ga 0.75 Al 0.25 as cladding layer, as shown in more second view (e), the electrode layer 5 on the exposed surface A conductive laser layer is formed, and the conductive layer is connected to electrode wirings such as Au serving as the electrode wirings 6a, 6b, and 6c, respectively, to manufacture a semiconductor laser.

以上のように作製した半導体レーザにおいて、室温パ
ルス動作で活性層4aたるi−GaAs活性層のしきい値電流
200mA、活性層4bたる−Ga0.9Al0.1As活性層のしきい値
電流410mAの半導体レーザが得られる。
In the semiconductor laser fabricated as described above, the threshold current of the i-GaAs active layer as the active layer 4a was measured at room temperature pulse operation.
A semiconductor laser having a threshold current of 200 mA and a threshold current of the active layer 4b of -Ga 0.9 Al 0.1 As active layer of 410 mA is obtained.

(実施例2) 本実施例は第二実施態様例にかかわるものであり、i
−GaAs,i−Ga0.95Al0.05As,i−Ga0.9Al0.1Asの三つの活
性層をもつLEDを作製したものである。なおLEDの構造及
び製造工程は第3図,第4図を用いて説明した発光装置
と同様なので、第3図,第4図を引用しながら説明する
ものとする。
(Example 2) This example is related to the second embodiment example, and i
An LED having three active layers of -GaAs, i-Ga 0.95 Al 0.05 As and i-Ga 0.9 Al 0.1 As was produced. Since the structure and manufacturing process of the LED are the same as those of the light emitting device described with reference to FIGS. 3 and 4, the description will be made with reference to FIGS. 3 and 4.

第4図(a)に示すように支持基板19たるセラミック
基板上に非核形成面12を形成するSiO2層を蒸着し、微細
な領域(1.2μm□)にAsイオンを打ち込み、核形成密
度を高めて、核形成面11を形成する。
As shown in FIG. 4 (a), a SiO 2 layer for forming the non-nucleation surface 12 is deposited on a ceramic substrate as a support substrate 19, and As ions are implanted into a fine region (1.2 μm square) to reduce the nucleation density. Raised to form the nucleation surface 11.

次に第4図(b)示すように、MOCVD法により、成長
温度600℃、III−V族化合物半導体材料(V/III比)=1
0、圧力10Torr、原料ソースとしてTBAs,TMG,TMAlを用
い、ドーピング原料としてSiH4を用いて単結晶粒17たる
n−Ga0.8Al0.2As単結晶粒を核形成する。
Next, as shown in FIG. 4 (b), a growth temperature of 600 ° C. and a III-V compound semiconductor material (V / III ratio) = 1 by MOCVD.
0, pressure 10 Torr, using TBAs, TMG, a TMAl as a raw material source, a single crystal grain 17 serving n-Ga 0.8 Al 0.2 As the single crystal grain nuclei formed using SiH 4 as a raw material for doping.

次に第4図(c)に示すようにMOCVD法により、成長
温度600℃ V/III比=50、圧力100Torrで原料ソースとし
てAsH3,TMG,TMAl,ドーピグ原料としてDEZn,SiH4を用
い、原料ソース、ドーピング原料の切り換えにより、ク
ラッド層13aたるn−Ga0.8Al0.2Asクラッド層、活性層1
4aたるi−GaAs活性層、クラッド層13bたるp−Ga0.8Al
0.2Asクラッド層、高抵抗層18aたるi−Ga0.7Al0.3As高
抵抗層、クラッド層13cたるp−Ga0.8Al0.2Asクラッ
ド、活性層14bたるi−Ga0.95Al0.05As活性層、クラッ
ド層13dたるn−Ga0.8Al0.2Asクラッド層、高抵抗層18b
たるi−Ga0.7Al0.3As高抵抗層、クラッド層13eたるp
−Ga0.8Al0.2Asクラッド層、活性層14cたるi−Ga0.9Al
0.1As活性層、クラッド層13fたるn−Ga0.8Al0.2Asクラ
ッド層を成長させる。
Next, as shown in FIG. 4 (c), by MOCVD method, using AsH 3 , TMG, TMAl as source material, DEZn, SiH 4 as dope source at a growth temperature of 600 ° C., V / III ratio = 50, pressure of 100 Torr, By switching the material source and the doping material, the n-Ga 0.8 Al 0.2 As clad layer 13a serving as the clad layer 13a and the active layer 1 are formed.
4a, i-GaAs active layer as a clad layer, p-Ga 0.8 Al as a clad layer 13b
0.2 As clad layer, i-Ga 0.7 Al 0.3 As high resistance layer 18a, i-Ga 0.7 Al 0.3 As high resistance layer, clad layer 13c p-Ga 0.8 Al 0.2 As clad, active layer 14b i-Ga 0.95 Al 0.05 As active layer, clad layer 13d n-Ga 0.8 Al 0.2 As clad layer, high resistance layer 18b
Barrel i-Ga 0.7 Al 0.3 As high resistance layer, cladding layer 13e barrel p
-Ga 0.8 Al 0.2 As clad layer, active layer 14c, i-Ga 0.9 Al
An n-Ga 0.8 Al 0.2 As clad layer serving as a 0.1 As active layer and a clad layer 13f is grown.

次に、第4図(d)に示すように表面をRIBEにより平
坦化し、クラッド層13aたるn−Ga0.8Al0.2Asクラッド
層、クラッド層13bたるp−Ga0.8Al0.2Asクラッド層、
クラッド層13cたるp−Ga0.8Al0.2Asクラッド層、クラ
ッド層13dたるn−Ga0.8Al0.2Asクラッド層、クラッド
層13eたるp−Ga0.8Al0.2Asクラッド層、クラッド層13f
たるn−Ga0.8Al0.2Asクラッド層を露出させ、さらに第
4図(e)に示すように、電極層15たる導電層を形成
し、この導電層にそれぞれ電極配線16a,16b,16c,16d,16
e,16fたるAu等の電極配線を接続してLEDを作製する。
Next, as shown in FIG. 4 (d), the surface is flattened by RIBE, and an n-Ga 0.8 Al 0.2 As clad layer as a clad layer 13a, a p-Ga 0.8 Al 0.2 As clad layer as a clad layer 13b,
Cladding layer 13c serving p-Ga 0.8 Al 0.2 As cladding layer, the cladding layer 13d serving n-Ga 0.8 Al 0.2 As cladding layer, the cladding layer 13e serving p-Ga 0.8 Al 0.2 As cladding layer, the cladding layer 13f
The n-Ga 0.8 Al 0.2 As clad layer is exposed, and a conductive layer as an electrode layer 15 is formed as shown in FIG. 4 (e). Electrode wirings 16a, 16b, 16c, 16d are formed on the conductive layer, respectively. , 16
e, LED electrodes are made by connecting electrode wirings such as 16f Au.

以上のように作製した発光素子は、室温パルス動作で
クラッド層13dたるn−Ga0.8Al0.2Asクラッド層上の電
極配線を接地し、活性層14bたるi−Ga0.95Al0.05As活
性層に100mA電流注入したところ、他の活性層との光出
力の強度比が−20dBとなった。
The light emitting device manufactured as described above was grounded at room temperature with a pulsed operation at room temperature, and the electrode wiring on the n-Ga 0.8 Al 0.2 As clad layer 13d was grounded, and 100 mA was applied to the active layer 14b, i-Ga 0.95 Al 0.05 As active layer. When current was injected, the intensity ratio of the light output to the other active layers became -20 dB.

〔発明の効果〕〔The invention's effect〕

以上詳細に説明したように、本発明によれば、各々の
ダブルヘテロ構造部間に絶縁層又は高抵抗層を形成する
ことで、目的とするダブルヘテロ構造部以外への漏れ電
流が低減でき、その結果として半導体レーザの低しきい
値化が実現でき、目的とするダブルヘテロ構造部以外か
らの発光も防げることができる。
As described above in detail, according to the present invention, by forming an insulating layer or a high-resistance layer between each double hetero structure portion, it is possible to reduce leakage current to other than the intended double hetero structure portion, As a result, the threshold value of the semiconductor laser can be reduced, and light emission from portions other than the target double hetero structure portion can be prevented.

また本発明は通常の半導体プロセスで作製可能なた
め、特別な装置を必要とすることがなく、製造工程を複
雑化することなく作製することができる。
Further, since the present invention can be manufactured by an ordinary semiconductor process, it can be manufactured without requiring a special device and without complicating a manufacturing process.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、本発明の発光装置の第一実施態様例の構造を
示す平面図及び縦断面図である。 第2図(a)〜(e)は、上記第一実施態様例の製造工
程を示す工程図である。 第3図は、本発明の発光装置の第二実施態様例の構造を
示す平面図及び縦断面図である。 第4図(a)〜(e)は、上記第二実施態様例の製造工
程を示す工程図である。 1,11……核形成面、2,12……非核形成面、3a,3b,3c,3d,
13a,13b,13c,13d,13e,13f……クラッド層、4a,4b,14a,1
4b,14c……活性層、5,15……電極層、6a,6b,6c,6d,16a,
16b,16c,16d,16e,16f……電極配線、7,17……単結晶
粒、8,18a,18b……高抵抗層。
FIG. 1 is a plan view and a longitudinal sectional view showing the structure of a first embodiment of the light emitting device of the present invention. 2 (a) to 2 (e) are process diagrams showing the manufacturing process of the first embodiment. FIG. 3 is a plan view and a longitudinal sectional view showing the structure of a second embodiment of the light emitting device of the present invention. FIGS. 4 (a) to 4 (e) are process diagrams showing the manufacturing process of the second embodiment. 1,11… nucleation surface, 2,12… non-nucleation surface, 3a, 3b, 3c, 3d,
13a, 13b, 13c, 13d, 13e, 13f …… cladding layers, 4a, 4b, 14a, 1
4b, 14c: Active layer, 5, 15: Electrode layer, 6a, 6b, 6c, 6d, 16a,
16b, 16c, 16d, 16e, 16f: electrode wiring, 7, 17: single crystal grain, 8, 18a, 18b: high resistance layer.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01S 3/18 H01L 33/00──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 6 , DB name) H01S 3/18 H01L 33/00

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基体と、該基体上の一部に形成された第1
のクラッド層と、前記基体上の第1のクラッド層の外周
部に形成され、電流が注入されることによって光を発す
る第1の活性層と、前記基体上の第1の活性層の外周部
に形成された第2のクラッド層と、前記基体上の第2の
クラッド層の外周部に形成された絶縁又は高抵抗層と、
前記基体上の絶縁又は高抵抗層の外周部に形成された第
3のクラッド層と、前記基体上の第3のクラッド層の外
周部に形成され、電流が注入されることによって光を発
する第2の活性層と、前記基体上の第2の活性層の外周
部に形成された第4のクラッド層と、前記第1及び第2
の活性層に電流を供給するための電極とから成り、前記
第1の活性層、第1及び第2のクラッド層は、前記基体
の表面にほぼ垂直な接合面を有する第1のダブルヘテロ
構造を構成し、前記第2の活性層、第3及び第4のクラ
ッド層は、前記基体の表面にほぼ垂直な接合面を有する
第2のダブルヘテロ構造を構成する発光装置。
A first substrate formed on a part of the substrate;
A first active layer formed on an outer peripheral portion of the first clad layer on the substrate and emitting light by current injection, and an outer peripheral portion of the first active layer on the substrate A second cladding layer formed on the substrate, an insulating or high-resistance layer formed on the outer periphery of the second cladding layer on the substrate,
A third cladding layer formed on the outer periphery of the insulating or high-resistance layer on the base and a third cladding layer formed on the outer periphery of the third cladding layer on the base and emitting light by current injection; A second active layer, a fourth cladding layer formed on an outer peripheral portion of the second active layer on the base, and the first and second active layers.
And an electrode for supplying a current to the active layer, wherein the first active layer, the first and second cladding layers have a first double heterostructure having a bonding surface substantially perpendicular to the surface of the base. Wherein the second active layer, the third and the fourth cladding layers constitute a second double heterostructure having a junction surface substantially perpendicular to the surface of the base.
【請求項2】前記基体は、核形成密度の小さい非核形成
面と、該比核形成面よりも大きい核形成密度を有し、且
つ、この上で結晶が単一核のみより成長するように充分
小さい面積を有する、前記非核形成面に隣接して配され
た核形成面とを有し、前記第1のクラッド層は前記核形
成面を含む基体上の微小領域に形成されている請求項1
に記載の発光装置。
2. The substrate has a non-nucleation surface having a low nucleation density, a nucleation density higher than the specific nucleation surface, and a crystal on which only single nuclei grow. A nucleation surface disposed adjacent to said non-nucleation surface having a sufficiently small area, wherein said first cladding layer is formed in a small area on a substrate including said nucleation surface. 1
A light-emitting device according to claim 1.
【請求項3】前記第1及び第2の活性層は、互いに波長
の異なる光を発する請求項1に記載の発光装置。
3. The light emitting device according to claim 1, wherein said first and second active layers emit light having different wavelengths from each other.
【請求項4】基体の表面の一部に、他の部分よりも大き
い核形成密度を有し、且つ、この上で結晶が単一核のみ
より成長するように充分小さい面積を有する核形成面を
形成する過程と、前記核形成面を含む基体上の微小領域
に単結晶半導体から成る第1のクラッド層を単一核より
成長させる過程と、前記基体上の第1のクラッド層の外
周部に単結晶半導体から成る第1の活性層を成長させる
過程と、前記基体上の第1の活性層の外周部に単結晶半
導体から成る第2のクラッド層を成長させる過程と、前
記基体上の第2のクラッド層の外周部に単結晶半導体か
ら成る絶縁又は高抵抗層を成長させる過程と、前記基体
上の絶縁又は高抵抗層の外周部に単結晶半導体から成る
第3のクラッド層を成長させる過程と、前記基体上の第
3のクラッド層の外周部に単結晶半導体から成る第2の
活性層を成長させる過程と、前記基体上の第2の活性層
の外周部に単結晶半導体から成る第4のクラッド層を成
長させる過程と、前記成長した第1及び第2の活性層、
第1乃至第4のクラッド層及び絶縁又は高抵抗層の上部
を平坦化する過程と、前記第1及び第2の活性層に電流
を供給するための電極を形成する過程とから成り、前記
第1の活性層、第1及び第2のクラッド層は、前記基体
の表面にほぼ垂直な接合面を有する第1のダブルヘテロ
構造を構成し、前記第2の活性層、第3及び第4のクラ
ッド層は、前記基体の表面にほぼ垂直な接合面を有する
第2のダブルヘテロ構造を構成する発光装置の作製方
法。
4. A nucleation surface having a greater nucleation density on one portion of the surface of the substrate than on the other portion and having a sufficiently small area thereon that crystals grow from only a single nucleus. Forming a first cladding layer made of a single crystal semiconductor from a single nucleus in a minute region on the substrate including the nucleation surface; and forming an outer peripheral portion of the first cladding layer on the substrate. Growing a first active layer made of a single crystal semiconductor on the substrate, growing a second cladding layer made of a single crystal semiconductor on the outer periphery of the first active layer on the substrate, Growing an insulating or high-resistance layer made of a single-crystal semiconductor on the outer periphery of the second cladding layer, and growing a third cladding layer of a single-crystal semiconductor on the outer periphery of the insulating or high-resistance layer on the substrate And forming a third cladding layer on the substrate. Growing a second active layer made of a single crystal semiconductor on a peripheral portion, growing a fourth cladding layer made of a single crystal semiconductor on an outer peripheral portion of the second active layer on the base; First and second active layers,
A step of flattening the upper portions of the first to fourth cladding layers and the insulating or high-resistance layer, and a step of forming electrodes for supplying current to the first and second active layers. The first active layer, the first and second cladding layers constitute a first double heterostructure having a bonding surface substantially perpendicular to the surface of the base, and the second active layer, the third and fourth cladding layers. A method for manufacturing a light-emitting device in which a cladding layer has a second double heterostructure having a bonding surface substantially perpendicular to a surface of the base.
JP18606889A 1989-07-20 1989-07-20 Light emitting device and manufacturing method thereof Expired - Fee Related JP2815115B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18606889A JP2815115B2 (en) 1989-07-20 1989-07-20 Light emitting device and manufacturing method thereof
DE69009329T DE69009329T2 (en) 1989-07-20 1990-07-19 Light-emitting device and method for its production.
EP90113874A EP0410307B1 (en) 1989-07-20 1990-07-19 Light-emitting device and method for producing the same
US07/554,905 US5115284A (en) 1989-07-20 1990-07-20 Light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18606889A JP2815115B2 (en) 1989-07-20 1989-07-20 Light emitting device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0352284A JPH0352284A (en) 1991-03-06
JP2815115B2 true JP2815115B2 (en) 1998-10-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP18606889A Expired - Fee Related JP2815115B2 (en) 1989-07-20 1989-07-20 Light emitting device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2815115B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3660501B2 (en) 1998-05-28 2005-06-15 日立建機株式会社 Engine speed control device for construction machinery

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Jpn.J.Appl.Phys.Part2 31[12A](1992)p.L1710−L1713

Also Published As

Publication number Publication date
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