JP2812326B2 - Manufacturing method of chip type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a chip-type semiconductor device, and more particularly to a method for manufacturing a chip-type semiconductor device having a built-in semiconductor element.

[0002]

2. Description of the Related Art Conventionally, as a method of manufacturing a chip-type semiconductor device having a built-in semiconductor element, a method of manufacturing a chip-type semiconductor device in which a plurality of elements can be capped at once has been known. (Japanese Patent Laid-Open No. 4-1485
No. 53). In this conventional manufacturing method, as shown in FIG. 6, a plurality of upper and lower electrodes are provided on each of the upper and lower surfaces of a parent substrate 24 including a plurality of substrates, and the upper and lower electrodes are connected. A through-hole 25 is provided, conduction is provided by the through-hole 26, and elements 27 are respectively mounted on the parent substrate 24 between the adjacent through-holes 26, and each of the elements 27 and the upper surface electrode are electrically connected by a wire 28. Connecting.

[0003] Next, as shown in FIG.
The sealing parent lid 31 formed with is formed on the parent substrate 24 from above the elements 27, and each element 27 is sealed in the recess 32. Thereafter, the parent substrate 24 and the sealing lid 31 are cut off for each element 27 along the line CC in FIG.
A plurality of chip components 41 as shown in FIG.

[0004]

However, in the above-mentioned conventional method, a plurality of semiconductor elements 27 are mounted on the parent substrate 24, and the semiconductor elements 27 are sealed with the sealing parent lid 31 having the recess 32. Therefore, in consideration of the mounting accuracy of the semiconductor element 27 and the wiring material between the semiconductor element 27 and the mother board 24, the space of the recess 32 of the sealing lid 31 is 2
This is about 00 μm, and it is very difficult to make the size of the outer shape of the chip type component 41 close to the size of the semiconductor element 27.

The speed at which the element 27 is mounted on the mother board 24 is at most 0.6 seconds / piece, and it is not possible to expect a remarkable increase in the mounting speed. There is a problem that the productivity is limited by the mounting speed, and a remarkable improvement in productivity cannot be expected.

[0006] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of manufacturing a chip-type semiconductor device capable of manufacturing a small chip-type semiconductor device.

Another object of the present invention is to provide a method of manufacturing a chip-type semiconductor device with improved production capacity per unit time.

Another object of the present invention is to provide a method of manufacturing a chip-type semiconductor device with improved productivity and yield.

[0009]

In order to achieve the above object, according to the present invention, a metal bump is formed on an electrode of a semiconductor element of a semiconductor wafer having a plurality of semiconductor elements formed at known positions on a surface. A first step of forming, bonding the electrode pattern side of the insulating substrate having the electrode pattern formed at a known position on the surface and the semiconductor element forming surface side of the semiconductor wafer, and joining the electrode pattern and the metal bumps A second step of cutting the semiconductor wafer out of the semiconductor wafer and the insulating substrate bonded in the second step, and a third step of cutting and dividing only the semiconductor wafer into individual semiconductor elements. A fourth step of pouring and curing the liquid resin into the grooves and the semiconductor wafer, and simultaneously cutting the cured resin and the insulating substrate to form individual semiconductor devices each having a semiconductor element. It is obtained to include a fifth step of separating.

According to the present invention, a surface of a semiconductor wafer on which a plurality of semiconductor elements are formed is attached to an insulating substrate on which an electrode pattern is formed, and a metal bump of the semiconductor element is bonded to the electrode pattern of the insulating substrate. Therefore, a step of mounting individual semiconductor elements on a substrate can be omitted.

Further, in the present invention, a semiconductor wafer on which a plurality of semiconductor elements are formed is attached to an insulating substrate as it is, and a metal pump of the semiconductor element and an electrode pattern of the insulating substrate are joined. The semiconductor element can be sealed with a thin and uniform layer of the sealing resin without variation in mounting accuracy of each semiconductor element on the insulating substrate.

The shape and size of the insulating substrate are the same as the shape and size of the semiconductor wafer, and the electrode pattern of the insulating substrate is determined by using position coordinate data of the electrodes of the semiconductor element on the semiconductor wafer. Since it is formed at the determined position, the positioning between the metal pump of the semiconductor element and the electrode pattern of the insulating substrate can be facilitated.

According to another aspect of the present invention, there is provided a semiconductor wafer on which a plurality of semiconductor elements having electrode patterns are formed at known positions on a surface of a semiconductor wafer, the side being opposite to a semiconductor element forming surface. A first step of curing the first resin on the surface of the semiconductor wafer, and a second step of bonding an insulating substrate to the semiconductor element forming surface of the semiconductor wafer having the cured first resin.
A third step of forming a via hole exposing a part of the electrode pattern of the semiconductor wafer on the insulating substrate and a cutting recognition pattern; and a fourth step of forming a metal bump connected to the electrode pattern via the via hole. And the fifth step of simultaneously cutting and removing the semiconductor wafer and the insulating substrate to the size of each semiconductor element using the cut recognition pattern.
A step of embedding and curing the second resin in the region cut and removed by the fifth step, and a step of cutting the cured second resin together with the cured first resin. And a seventh step of separating the semiconductor device into individual semiconductor devices having semiconductor elements.

In the present invention, a cut recognition pattern is formed on an insulating substrate, and by using the cut recognition pattern, both the semiconductor wafer and the insulating substrate are simultaneously cut and removed to the size of each semiconductor element.

Here, the insulating substrate used in the present invention has no electrode pattern formed thereon, and the cut surface of the semiconductor element and the cut surface of the insulating substrate of the semiconductor device separated and manufactured in the seventh step. Is protected by the second resin cured in the sixth step. Further, the first and second resins are liquid resins of the same material, respectively. Further, the present invention may further include an eighth step of connecting a lead electrode to the metal bump of the semiconductor device separated and manufactured in the seventh step.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view for explaining each step of an embodiment of a method of manufacturing a chip type semiconductor device according to the present invention, and FIG. 2 is a supplementary explanatory view of FIG. In this embodiment, first, as shown in FIG. 1A, a semiconductor wafer 1 having a large number of semiconductor elements 2 formed on a surface is prepared. The electrode 3 is formed on the semiconductor element 2 as shown in FIG. Next, as shown in FIGS. 1B and 2B, the metal bumps 4 are formed on the electrodes 3 of the semiconductor element 2.
To form The metal bump 4 is usually formed by a ball bump method using a gold wire or a method of printing a solder bump, but the metal bump may be formed by another method.

Next, as shown in FIG. 1C, an insulating substrate 5 on which an electrode pattern is printed is bonded to the surface of the semiconductor wafer 1, and the metal bumps 4 of the semiconductor element 2 and the electrodes of the insulating substrate 5 are formed. Join the patterns. FIG. 2C is an enlarged view of an example of the insulating substrate 5. In the case of this example, a groove 7 is formed in the insulating substrate 5, the electrode pattern 6 is metallized through the side surface of the groove 7, and reaches the back surface (not shown) of the insulating substrate 5. The electrode pattern 6 may be formed by using a through hole.

Here, in order for the metal bumps 4 of the semiconductor element 2 and the electrode pattern 6 of the insulating substrate 5 to be accurately overlapped, position coordinate data of the electrode 3 of the semiconductor element 2 on the semiconductor wafer 1 is used. Thus, the position of the electrode pattern 6 on the insulating substrate 5 is determined, and the electrode pattern 6 is formed.

The insulating substrate 5 has the same size and shape as the semiconductor wafer 1, and the same orientation flat 8 'as the orientation flat 8 used for positioning in the semiconductor manufacturing process provided on the semiconductor wafer 1 is used as the insulating substrate. It is provided on the substrate 5.

Therefore, when forming the electrode pattern 6,
Although a printing technique is used, the electrode pattern 6 can be formed at the same position as the electrode 3 on the semiconductor wafer 1 side. Therefore, the positioning when bonding the semiconductor wafer 1 and the insulating substrate 5 only needs to match the orientation flats 8 and 8 'with the respective outer peripheral portions. At the time of bonding, several portions other than the metal bumps 4 and the electrode patterns 6 are bonded with an insulating adhesive.

As shown in FIG. 1D, the semiconductor wafer 1
After bonding the semiconductor substrate 1 and the insulating substrate 5 as described above, only the semiconductor wafer 1 is cut to the size of the semiconductor element 2 ′. That is, only the semiconductor wafer 1 positioned on the orientation flat 8 and the outer periphery is cut by determining the cutting position using the position coordinate data of the semiconductor element 2. A dicing saw is used for the cutting, but the groove width (cutting width) of the dicing groove 9 is made wider (about 60 μm).

Next, as shown in FIG. 1E, a liquid resin 10 for sealing is poured so as to cover the semiconductor element 2 'divided by the dicing groove 9, and the resin 10 is cured.
As the resin 10, a resin that is cured by a heat curing process or a light curing process is used.

Next, as shown in FIG.
With the insulating substrate 5 so as to be separated into individual components. The groove width of the dicing groove 9 'at this time is shown in FIG.
Is smaller than the groove width of the dicing groove 9 shown in FIG.
0 μm).

Each of the individual parts cut in this manner is, as shown in a partially cutaway perspective view in FIG.
0 is the cut surface 11 by the dicing groove 9 ', and constitutes the chip-type semiconductor device 12 in which the semiconductor element 2 is mounted on the cut insulating substrate 5'. The outer surface of the semiconductor element 2 is defined by a dicing groove 9.

According to the present embodiment, the semiconductor wafer 1 on which the plurality of semiconductor elements 2 are mounted is bonded to the insulating substrate 5 on which the electrode patterns 6 are formed, so that the mounting positions of the semiconductor elements vary. Further, since the semiconductor element is sealed with a thin uniform resin 10 and then cut into individual pieces, the size of the chip type semiconductor device 12 is reduced to the size of the semiconductor element 2 as shown in FIG. Can be very close.

Further, since the semiconductor elements 2 are mounted on the semiconductor wafer 1 in a lump, the productivity per semiconductor element is significantly improved. For example, in the case of a transistor on a semiconductor wafer having a diameter of 125 mm, even if it is assumed that about 70,000 elements take 5 minutes to bond, the rate is 0.004 seconds / piece, which is 150 times as large as when individual semiconductor elements are mounted. Performance will be improved.

In the above embodiment, the insulating substrate 5 has the same shape and size as the semiconductor wafer 1.
In addition, in order to use an electrode pattern printed on the surface so as to overlap the metal bump 4 of the semiconductor element 2,
There is not much versatility and it is difficult to achieve mass production effects sufficiently.

The position of the electrode pattern 6 on the insulating substrate 5 is determined based on the coordinate data of the position of the electrode 3 of the semiconductor element 2 on the semiconductor wafer 1 to determine the cutting section position. In order to read the position coordinate data on the wafer 1, the position coordinate data must be read through the insulating substrate 5,
There is a possibility that the cutting position may be erroneous due to a data recognition deviation (such as a refractive index) during transmission.

Further, in the step shown in FIG. 1D, only the semiconductor wafer 1 is cut to the size of the semiconductor element 2 'while the semiconductor wafer 1 and the insulating substrate 5 are bonded to each other.
Since the distance between the semiconductor wafer 1 and the insulating substrate 5 is short, there is a possibility that a cutting defect such as chipping of the semiconductor wafer 1 may occur.

Therefore, another embodiment of the present invention which solves the above problems will be described below. FIG. 4 is a cross-sectional view for explaining each step of another embodiment of the method of manufacturing a chip-type semiconductor device according to the present invention.

First, as shown in FIG. 4A, the liquid resin 17 is cured on the back surface of the semiconductor wafer 14 on which the semiconductor elements 15 are formed (corresponding to the semiconductor wafer 1 on which the semiconductor elements 2 are formed). , Electrode pattern 1 of semiconductor element 15
The surface on which 6 is formed (the surface of the semiconductor wafer 14) and the insulating substrate 18 are bonded. Unlike the insulating substrate 5 of the above embodiment, the insulating substrate 18 has no electrode pattern.

Next, a photoresist is applied on the surface of the insulating substrate 18 shown in FIG. 4A, a printing pattern is formed on the photoresist, and this photoresist is used as a mask, as shown in FIG. 4B. As described above, the via holes 19 and the cut recognition patterns 20 are formed in the insulating substrate 18 by etching, and then the photoresist is removed. Here, the formation of the via hole 19 exposes a part of the electrode pattern 16. Incidentally, the photoresist 13 in FIG. 4A is a photoresist in the case of being formed in a defective manner, and will be described later.

Next, as shown in FIG. 4C, a metal bump 21 for connecting to an external element is formed in the via hole 1.
9 formed on the electrode pattern 16 through the semiconductor element 1
5 and an external element can be connected.

Subsequently, as shown in FIG. 4D, the semiconductor wafer 14 and the insulating substrate 18 are cut using the cutting recognition pattern 20 so that the size of each semiconductor element 15 remains.
Are simultaneously cut and removed. Thereby, the cutting area 2
2, the cured resin 17 is exposed. At the time of this cutting (at the time of dicing), the cutting recognition pattern 20 formed on the insulating substrate 18 can be directly recognized, so that the cutting position can be accurately determined, and erroneous recognition is performed even in the operation of the automatic recognition cutting device. Never.

FIG. 4D shows the cut recognition pattern 2
Although 0 is located in the cutting region 22 and has disappeared by cutting, the cutting recognition pattern 20 may be formed and left on the insulating substrate 18 in the semiconductor element 15.

Next, as shown in FIG. 4E, the exposed cured resin 17 is filled so as to fill the inside of the cut region 22.
A liquid resin 17 ′ is poured into the upper surface, the semiconductor element 15, and the side surfaces of the insulating substrate 18 and then cured. At this time, resin 1
7 and 17 'are in close contact. As shown in FIG. 4E, even if the liquid resin 17 'is poured, the semiconductor wafer 1
Since the gap (corresponding to the height of the electrode pattern 16) between the substrate 4 and the insulating substrate 18 is extremely small, the resin 17 ′ does not reach the side surface of the electrode pattern 16.

Finally, as shown in FIG. 4F, the cured resins 17 and 17 'are cut at the same time, and the semiconductor element 15 is separated to obtain a chip-type semiconductor device. Therefore, the size of the chip-type semiconductor device of this embodiment can be very close to the size of the semiconductor element 15. The cutting width shown in FIG. 4F is smaller than the cutting width shown in FIG. 4D, and as a result, the side surfaces of the semiconductor element 15 and the insulating substrate 18 in the cutting region 22 are formed as shown in FIG. (F)
The resin 17 'is formed and remains as shown in FIG.

In this embodiment, the alignment with the electrode pattern 16 at the time of forming the via hole 19 in FIG. 4B utilizes the alignment recognition pattern formed in advance on the semiconductor wafer 14. In order to read the alignment recognition pattern through the substrate 18, it is visually confirmed whether or not the alignment is correct by using an infrared transmission microscope. At this time, as shown in FIG. 4A, the opening position of the photoresist 13 for forming the via hole 19 is different from the actual position of the electrode pattern 16 due to the refractive index of the insulating substrate 18 and other factors. As indicated by arrow X.

When the above-described positional deviation is detected by checking the print pattern of the photoresist 13,
The photoresist 13 is entirely removed by an organic solvent, O ₂ plasma asher, or the like, and a photoresist patterned again is formed on the insulating substrate 18. By this reprocessing, the alignment with the electrode pattern 16 at the time of forming the via hole 19 can be accurately performed.

Note that, for example, as shown in FIG. 5, a step of connecting the lead electrode 23 to the metal bump 21 can be further added to the chip-type semiconductor device manufactured as described above.

[0041]

Next, an embodiment of the present invention will be described with reference to FIG. As shown in FIG.
Numeral 4 is made of GaAs having a thickness of about 100 μm, and a liquid resin 18 is applied to the back surface and cured. Insulating substrate 18
Is a high-resistance GaAs substrate having a thickness of about 100 μm,
For bonding to the semiconductor wafer 14, polyimide or photoresist is used.

Next, as shown in FIG. 4B, a 40 μm square via hole 19 is formed in the insulating substrate 18 so as to be located inside the 80 μm square electrode pattern 16 on the semiconductor wafer 14. In forming the via hole 19, a GaAs dry etching technique is used, and a photoresist technique is used for the patterning. The alignment between the via hole pattern and the electrode pattern 16 formed on the insulating substrate 18 by the photoresist technique is confirmed using infrared rays transmitted through both, and if there is a misalignment, re-processing is performed. Failure can be prevented from occurring. In forming the via hole, a cut recognition pattern is also formed at the same time.

Next, as shown in FIG. 4C, a metal bump 21 is formed on the electrode pattern 16 exposed by the via hole 19 to have a function of connecting the external element and the semiconductor element 15.

Next, as shown in FIG. 4D, the size of the semiconductor element 15 is reduced to 15
Cut by dicing with a width of 0 μm. Next, FIG.
As shown in (e), a liquid resin 17 ′ of the same material as the resin 17 is poured into the cut region 22 having a width of 150 μm and hardened. Next, as shown in FIG. 4F, the center of the resin 17 ′ is cut at a width of 30 μm to separate the semiconductor element 15.

[0045]

As described above, according to the present invention,
The semiconductor wafer on which a plurality of semiconductor elements are formed is attached to an insulating substrate, and the metal pump of the semiconductor element and the electrode pattern of the insulating substrate are bonded to each other, whereby the mounting accuracy of each semiconductor element on the insulating substrate varies. No, because the semiconductor element can be sealed with a thin uniform layer of sealing resin,
The size of the chip-type semiconductor device can be reduced to a size very close to the size of the semiconductor element.

According to the present invention, the surface of the semiconductor wafer on which the plurality of semiconductor elements are formed is attached to the insulating substrate on which the electrode pattern is formed, and the metal bumps of the semiconductor element and the electrode pattern of the insulating substrate are bonded. Can eliminate the need for the step of mounting individual semiconductor elements on a substrate, thereby significantly improving the productivity of mounting semiconductor elements.
Thus, the productivity of the chip-type semiconductor device can be significantly improved.

Further, according to the present invention, the shape and size of the insulating substrate are the same as the shape and size of the semiconductor wafer, and the electrode pattern of the insulating substrate corresponds to the electrode pattern of the semiconductor device on the semiconductor wafer. Improving the productivity and reliability of chip-type semiconductor devices by making it easier to position the metal pump of the semiconductor element and the electrode pattern of the insulating substrate by forming it at the position determined using the position coordinate data can do.

Further, according to the present invention, a cut recognition pattern is formed on an insulating substrate, and by using the cut recognition pattern, both the semiconductor wafer and the insulating substrate are simultaneously cut and removed to the size of each semiconductor element. By doing so, it is possible to directly recognize the cutting recognition pattern, so that the cutting position at the time of dicing can be accurately determined, thereby improving the yield. In addition, since the semiconductor wafer and the insulating substrate are cut at the same time, defects such as chipping during dicing can be prevented.

Further, since the insulating substrate used in the present invention has no pattern, the same insulating substrate can be used for semiconductor wafers having different electrode patterns of semiconductor elements. The flexible substrate can be provided with versatility, and a mass production effect can be obtained.
Furthermore, since the first and second resins are liquid resins of the same material, respectively, they have excellent adhesion and can sufficiently protect the semiconductor element and the insulating substrate.

[Brief description of the drawings]

FIG. 1 is a perspective view for explaining each step of an embodiment of the manufacturing method of the present invention.

FIG. 2 is a supplementary explanatory diagram of FIG. 1;

FIG. 3 is a partially cutaway perspective view of a chip-type semiconductor device manufactured by the manufacturing method of FIG. 1;

FIG. 4 is a cross-sectional view for explaining each step of another embodiment of the manufacturing method of the present invention.

FIG. 5 is a sectional view of another example of a chip-type semiconductor device manufactured by the manufacturing method of the present invention.

FIG. 6 is an apparatus sectional view of a first step of an example of a conventional manufacturing method.

FIG. 7 is an apparatus cross-sectional view of a second step of an example of a conventional manufacturing method.

FIG. 8 is a perspective view of an example of a chip-type component manufactured by the manufacturing method of FIGS. 6 and 7;

[Description of Signs] 1, 14 Semiconductor wafer 2, 15 Semiconductor element 3 Electrode 4, 21 Metal bump 5, 18 Insulating substrate 5 'Insulating substrate 6, 16 After cutting Electrode pattern 7 Groove 8, 8' Orientation flat 9 , 9 'Dicing groove 10, 17, 17' Resin 11 Cutting surface 12 Chip type semiconductor device 13 Photoresist 19 Via hole 20 Cutting recognition pattern 22 Cutting region 23 Lead electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 23/12 H01L 21/56

Claims (10)

(57) [Claims] A first step of forming a metal bump on an electrode of the semiconductor element on a semiconductor wafer having a plurality of semiconductor elements formed at a known position on the surface; and forming an electrode pattern at a known position on the surface. A second step of bonding the electrode pattern side of the insulated substrate and the semiconductor element forming surface side of the semiconductor wafer, and bonding the electrode pattern and the metal bumps; and A third step of cutting and dividing only the semiconductor wafer out of the semiconductor wafer and the insulating substrate to the size of each of the semiconductor elements; and a step of cutting and dividing the semiconductor wafer with a liquid resin on the semiconductor wafer. A fourth step of pouring and curing; and a step of simultaneously cutting the cured resin and the insulating substrate and separating each into individual semiconductor devices having the semiconductor elements. Method of manufacturing a chip-type semiconductor device which comprises a step. 2. The method according to claim 1, wherein the shape and size of the insulating substrate are the same as the shape and size of the semiconductor wafer. 3. The semiconductor device according to claim 1, wherein the electrode pattern of the insulating substrate is formed at a position determined using position coordinate data of the electrode of the semiconductor element on the semiconductor wafer. A method for manufacturing a chip-type semiconductor device. 4. The semiconductor device according to claim 3, wherein the third step determines a cutting section position by using position coordinate data of the semiconductor element on the semiconductor wafer and cuts only the semiconductor wafer. 2. The method for manufacturing a chip-type semiconductor device according to item 1. 5. The method of manufacturing a chip-type semiconductor device according to claim 1, wherein the width of the cutting groove in the cutting section in the third step is wider than the width of the cutting groove in the fifth step. 6. A first step of curing a first resin on a surface of a semiconductor wafer on which a plurality of semiconductor elements having electrode patterns are formed at known positions on the surface, the surface being opposite to the semiconductor element forming surface. A second step of bonding an insulating substrate to the semiconductor element forming surface of the semiconductor wafer having the cured first resin; and a via exposing a part of the electrode pattern of the semiconductor wafer to the insulating substrate. A third step of forming a hole and a cut recognition pattern; a fourth step of forming a metal bump connected to the electrode pattern via the via hole; and a step of forming each of the semiconductor elements by using the cut recognition pattern. A fifth step of simultaneously cutting and removing the semiconductor wafer and the insulating substrate to a size, and embedding a second resin in a region cut and removed by the fifth step. A sixth step of cutting the hardened second resin together with the hardened first resin, and separating the hardened second resin into individual semiconductor devices each having the semiconductor element. A method for manufacturing a chip-type semiconductor device. 7. The method according to claim 6, wherein the insulating substrate has no electrode pattern formed thereon. 8. The cut surface of the semiconductor element and the cut surface of the insulating substrate of the semiconductor device separated and manufactured in the seventh step are respectively formed of the second resin cured in the sixth step. 7. The method for manufacturing a chip-type semiconductor device according to claim 6, wherein the method is protected. 9. The semiconductor device according to claim 7, wherein a lead electrode is connected to the metal bump of the semiconductor device separated and manufactured in the seventh step.
7. The method for manufacturing a chip-type semiconductor device according to claim 6, further comprising the step of: 10. The method according to claim 6, wherein the first and second resins are liquid resins of the same material.